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change ref clk in adrv9361-z7035

Hello,

I am using adrv9361-z7035 and change the internal clock in your devicetree

to an external one of 26 MHz and frecuency accuracy 1ppm.

Changes made:

clocks {

        clock@0 {
            #clock-cells = <0x00>;
            compatible = "adjustable-clock";
        clock-frequency = <0x18cba80>;
        clock-accuracy = <0x1a>;
        clock-output-names = "TCXO_26MHz";
            linux,phandle = <0x0b>;
            phandle = <0x0b>;
        };

        clock@2 {
            #clock-cells = <0x00>;
            compatible = "fixed-clock";
            clock-frequency = <0x16e3600>;
            clock-output-names = "24MHz";
            linux,phandle = <0x0c>;
            phandle = <0x0c>;
        };

        clock@3 {
            #clock-cells = <0x00>;
            compatible = "fixed-clock";
            clock-frequency = <0x17d7840>;
            clock-output-names = "ad9517_refclk";
            linux,phandle = <0x07>;
            phandle = <0x07>;
        };

        audio_clock {
            compatible = "fixed-clock";
            #clock-cells = <0x00>;
            clock-frequency = <0xbb8000>;
            linux,phandle = <0x0e>;
            phandle = <0x0e>;
        };
    };

    ad9361-refclk-gpio-gate@0 {
        #clock-cells = <0x00>;
        compatible = "gpio-gate-clock";
        clocks = <0x0b>;
       enable-gpios = <0x06 0x69 0x01>;
        clk-set-rate-parent-enable;
        clock-output-names = "ad9361_ext_refclk";
        linux,phandle = <0x05>;
        phandle = <0x05>;
    };

First I would like to know if this change is correct.

Second, I would like to know how I can confirm that my board is using the new oscillator. I use Linux.


Thanks a lot,
Nicole.

  • This looks fine.

    To check if the clock is used you can look at the clock summary on the board:

    cat /sys/kernel/debug/clk/clk_summary

    -Travis

  • Thanks

    When I turn on the board the following appears:

    Where appears tuning rx failed.

    Also when entering what you told me, I get the following:


    Does this have to do with the external oscillator not working?

  • What is the level of your external reference clock?

    -Travis

  • I was able to measure the output signal of my oscilloscope with an oscilloscope. 
    And I got the following signal:

    It is within the maximum value requested by the ad9361_clk input. I can't find what the problem may be.

    Nicole
  • Did you actually read  /sys/kernel/debug/clk/clk_summary ?

    It says that your refclk is 40.000078 MHz!

    And if the real rate is 26MHz then things fail for sure.

    There are two possibilities here.

    1) Your devices tree doesn't specify 26MHz, which I doubt because it shows the revises clock name.

    2) Something is changing the adjustable clock. That can be for example OSC when when it starts. Or some other script.

    You can prevent that by using:

     compatible = "fixed-clock";

    -Michael

  • I made the change you proposed and when I see what is shown by
    I keep seeing that the frequency is 40000008 Hz.
    The configuration is like the one I showed above. 
    If this is fine and the oscillator is working, what would be the problem?
  • This is my modified device tree:

    DOCX

    and This is the result of cat/sys/kernel/debug/clk/clk_summary:

  • ok - I tested the entire process here:

    1. Modified the dts source file
    2. Rebuild the dtb
    3. Copied to the SD card 

    michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ git diff
    diff --git a/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi b/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
    index 48ad6894b65a..215e4fb60d3b 100644
    --- a/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
    +++ b/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
    @@ -23,10 +23,10 @@
            clocks {
                    xo_40mhz_fixed_clk: clock@0 {
                            #clock-cells = <0>;
    -                       compatible = "adjustable-clock";
    -                       clock-frequency = <40000000>;
    +                       compatible = "fixed-clock";
    +                       clock-frequency = <39999123>;
                            clock-accuracy = <200000>; /* 200 ppm (ppb) */
    -                       clock-output-names = "XO_40MHz";
    +                       clock-output-names = "XO_39p999123MHz";
                    };
     
                    usb_ulpi_fixed_clk: clock@2 {
    
    michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ make zynq-adrv9361-z7035-fmc.dtb
      DTC     arch/arm/boot/dts/zynq-adrv9361-z7035-fmc.dtb
    
    michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ cp arch/arm/boot/dts/zynq-adrv9361-z7035-fmc.dtb /media/michael/BOOT/devicetree.dtb 
    
    

    After the board booted - I can see both - the name and frequency change

    root@analog:~# cat /sys/kernel/debug/clk/clk_summary 
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     spi0.0-tx_lo_dummy                   0        0        0  1225000000          0     0  50000
     spi0.0-rx_lo_dummy                   0        0        0  1200000000          0     0  50000
     audio_clock                          1        1        0    12288000          0     0  50000
     ad9517_refclk                        0        0        0    25000000          0     0  50000
     24MHz                                0        0        0    24000000          0     0  50000
        usb-ulpe-gpio-gate                0        0        0    24000000          0     0  50000
     XO_39p999123MHz                      1        1        0    39999123     200000     0  50000
        ad9361-refclk-gpio-gate           4        4        0    39999123     200000     0  50000
           spi0.0-bb_refclk               1        1        0    39999123     200000     0  50000
              spi0.0-bbpll_clk            1        1        0   983040008     200000     0  50000
                 spi0.0-adc_clk           1        1        0   245760002     200000     0  50000
                    spi0.0-dac_clk        1        1        0   122880001     200000     0  50000
                       spi0.0-t2_clk       1        1        0   122880001     200000     0  50000
                          spi0.0-t1_clk       1        1        0    61440000     200000     0  50000
                             spi0.0-clktf_clk       1        1        0    30720000     200000     0  50000
                                spi0.0-tx_sampl_clk       1        1        0    30720000     200000     0  50000
                    spi0.0-r2_clk         0        0        0   122880001     200000     0  50000
                       spi0.0-r1_clk       0        0        0    61440000     200000     0  50000
                          spi0.0-clkrf_clk       0        0        0    30720000     200000     0  50000
                             spi0.0-rx_sampl_clk       0        0        0    30720000     200000     0  50000
           spi0.0-rx_refclk               1        1        0    79998246     200000     0  50000
              spi0.0-rx_rfpll_int         1        1        0  1200000000     200000     0  50000
                 spi0.0-rx_rfpll          1        1        0  1200000000     200000     0  50000
           spi0.0-tx_refclk               1        1        0    79998246     200000     0  50000
              spi0.0-tx_rfpll_int         1        1        0  1224999999     200000     0  50000
                 spi0.0-tx_rfpll          1        1        0  1224999999     200000     0  50000
    

    Can you try to do the same on your end?

    -Michael

  • What is highlighted are the changes I made by following this link:

    https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_tips_tricks

         clock@0 {

        #clock-cells = <0x00>;

        compatible = "adjustable-clock";

        clock-frequency = <0x18cba80>;

        clock-accuracy = <0x1a>;

        clock-output-names = "TCXO_26MHz";

        phandle = <0x0b>;

        };

    ad9361-refclk-gpio-gate@0 {

        #clock-cells = <0x00>;

        compatible = "gpio-gate-clock";

        clocks = <0x0b>;

        enable-gpios = <0x06 0x69 0x01>;

        clock-output-names = "ad9361_ext_refclk";

        phandle = <0x05>;

        };

    Then I access my board and with cat / sys / kernel / debug / clk / clk_summary and the following appears:


    It is seen that the accuracy changes to 26 Hz and the name of the clock from OX_40MHz to TCXO_26MHz, but the value of the frequency does not change, the same frequency that appears when initializing the iio oscilloscope appears, the frequency of the internal clock. Could it be that something is changing the frequency?

    Thanks,
    Nicole.