change ref clk in adrv9361-z7035

This looks fine.

To check if the clock is used you can look at the clock summary on the board:

cat /sys/kernel/debug/clk/clk_summary

-Travis

This looks fine.

To check if the clock is used you can look at the clock summary on the board:

cat /sys/kernel/debug/clk/clk_summary

-Travis

Thanks

When I turn on the board the following appears:

Where appears tuning rx failed.

Also when entering what you told me, I get the following:

Does this have to do with the external oscillator not working?

What is the level of your external reference clock?

-Travis

I was able to measure the output signal of my oscilloscope with an oscilloscope. 
And I got the following signal:



It is within the maximum value requested by the ad9361_clk input.

I can't find what the problem may be.

Nicole

This is my oscillator:

https://suntsu.com/wp-content/uploads/2019/07/STC53K-Series.pdf  

Did you actually read  /sys/kernel/debug/clk/clk_summary ?

It says that your refclk is 40.000078 MHz!

And if the real rate is 26MHz then things fail for sure.

There are two possibilities here.

1) Your devices tree doesn't specify 26MHz, which I doubt because it shows the revises clock name.

2) Something is changing the adjustable clock. That can be for example OSC when when it starts. Or some other script.

You can prevent that by using:

 compatible = "fixed-clock";

-Michael

This is my modified device tree:

DOCX

and This is the result of cat/sys/kernel/debug/clk/clk_summary:

ok - I tested the entire process here:

1. Modified the dts source file
2. Rebuild the dtb
3. Copied to the SD card 

michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ git diff
diff --git a/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi b/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
index 48ad6894b65a..215e4fb60d3b 100644
--- a/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
+++ b/arch/arm/boot/dts/zynq-adrv9361-z7035.dtsi
@@ -23,10 +23,10 @@
        clocks {
                xo_40mhz_fixed_clk: clock@0 {
                        #clock-cells = <0>;
-                       compatible = "adjustable-clock";
-                       clock-frequency = <40000000>;
+                       compatible = "fixed-clock";
+                       clock-frequency = <39999123>;
                        clock-accuracy = <200000>; /* 200 ppm (ppb) */
-                       clock-output-names = "XO_40MHz";
+                       clock-output-names = "XO_39p999123MHz";
                };
 
                usb_ulpi_fixed_clk: clock@2 {

michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ make zynq-adrv9361-z7035-fmc.dtb
  DTC     arch/arm/boot/dts/zynq-adrv9361-z7035-fmc.dtb

michael@mhenneri-D06:~/devel/hdl/github-linux-build/linux$ cp arch/arm/boot/dts/zynq-adrv9361-z7035-fmc.dtb /media/michael/BOOT/devicetree.dtb 

After the board booted - I can see both - the name and frequency change

root@analog:~# cat /sys/kernel/debug/clk/clk_summary 
                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 spi0.0-tx_lo_dummy                   0        0        0  1225000000          0     0  50000
 spi0.0-rx_lo_dummy                   0        0        0  1200000000          0     0  50000
 audio_clock                          1        1        0    12288000          0     0  50000
 ad9517_refclk                        0        0        0    25000000          0     0  50000
 24MHz                                0        0        0    24000000          0     0  50000
    usb-ulpe-gpio-gate                0        0        0    24000000          0     0  50000
 XO_39p999123MHz                      1        1        0    39999123     200000     0  50000
    ad9361-refclk-gpio-gate           4        4        0    39999123     200000     0  50000
       spi0.0-bb_refclk               1        1        0    39999123     200000     0  50000
          spi0.0-bbpll_clk            1        1        0   983040008     200000     0  50000
             spi0.0-adc_clk           1        1        0   245760002     200000     0  50000
                spi0.0-dac_clk        1        1        0   122880001     200000     0  50000
                   spi0.0-t2_clk       1        1        0   122880001     200000     0  50000
                      spi0.0-t1_clk       1        1        0    61440000     200000     0  50000
                         spi0.0-clktf_clk       1        1        0    30720000     200000     0  50000
                            spi0.0-tx_sampl_clk       1        1        0    30720000     200000     0  50000
                spi0.0-r2_clk         0        0        0   122880001     200000     0  50000
                   spi0.0-r1_clk       0        0        0    61440000     200000     0  50000
                      spi0.0-clkrf_clk       0        0        0    30720000     200000     0  50000
                         spi0.0-rx_sampl_clk       0        0        0    30720000     200000     0  50000
       spi0.0-rx_refclk               1        1        0    79998246     200000     0  50000
          spi0.0-rx_rfpll_int         1        1        0  1200000000     200000     0  50000
             spi0.0-rx_rfpll          1        1        0  1200000000     200000     0  50000
       spi0.0-tx_refclk               1        1        0    79998246     200000     0  50000
          spi0.0-tx_rfpll_int         1        1        0  1224999999     200000     0  50000
             spi0.0-tx_rfpll          1        1        0  1224999999     200000     0  50000

Can you try to do the same on your end?

-Michael

What is highlighted are the changes I made by following this link:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynq_tips_tricks

     clock@0 {

    #clock-cells = <0x00>;

    compatible = "adjustable-clock";

    clock-frequency = <0x18cba80>;

    clock-accuracy = <0x1a>;

    clock-output-names = "TCXO_26MHz";

    phandle = <0x0b>;

    };

ad9361-refclk-gpio-gate@0 {

    #clock-cells = <0x00>;

    compatible = "gpio-gate-clock";

    clocks = <0x0b>;

    enable-gpios = <0x06 0x69 0x01>;

    clock-output-names = "ad9361_ext_refclk";

    phandle = <0x05>;

    };

Then I access my board and with cat / sys / kernel / debug / clk / clk_summary and the following appears:

It is seen that the accuracy changes to 26 Hz and the name of the clock from OX_40MHz to TCXO_26MHz, but the value of the frequency does not change, the same frequency that appears when initializing the iio oscilloscope appears, the frequency of the internal clock. Could it be that something is changing the frequency?

Thanks,
Nicole.

My guess is that OSC changes the frequency.

OSC saves settings in a file called .osc_profile.ini which is either under /root or /home/analog

Can you try to delete both files if they exist?

I asked you to use 

compatible = "fixed-clock";

to prevent this on the lowest level.

-Michael