register read not working in AD7606b parallel interface

I'm a bit confused here, since the AD7606B is only supported in SPI interface mode.

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad7606_spi.c#L345

And for SPI reg_read() and reg_write() callbacks are implemented.

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad7606_spi.c#L300

For the Par interface they are not.

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad7606_par.c#L44

-Michael

Hi Michael,

we have used and modified ADI parallel interface HDL code also written linux driver code on top of https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad7606_par.c . our driver is working as we are getting ADC data on parallel bus for all channel, we have made Par interface reg_read andreg_write implemented from our side.Reg_write function is working properly but reg_read functionality is not. we have checked output waveform  from scope and is correctly alligned and executing but we getting a fixed range value. refer previously posted question. 

"Hi, We are using AD7606b in parallel mode though Linux drivers. we used HDL and linux driver from ADI reference source. for parallel interface we are able to get ADC reading. but we are facing with register read operation. we are using AD7606b in software mode, ADC reading are correctly coming, but when we try to read ADC register data we are getting 0x18CX value in return irrespective to any register address. we checked with oscilloscope , the register read in parallel mode waveform is same as datasheet , any we are even able to get register read command properly, but response from register_read from AD7606b is always in range 0x18CX for any register address we use. we even try to read register data at adders 0x2f for which we should get 0x14 but getting 0x18CX and for this we also check waveform on oscilloscope and AD7606B is actually transmitting 0x18C0. request you to kindly suggest any solution or points we might be missing out."

 is there any configuration we missing out kinldy guide us on this issue.

regards,

shivashankar thati.

Parallel register read/write is documented in the AD7606B datasheet page 35-37.

https://www.analog.com/media/en/technical-documentation/data-sheets/ad7606b.pdf

I would try to capture all bus cycles using a logic analyzer. 

If you have questions related to the interface and operation please post a question in the Precision ADC forum here: https://ez.analog.com/data_converters/precision_adcs

Regarding your driver modifications it's difficult to advice without seeing your changes.

-Michael

Hi,

we follow design as per datasheet itself, what we observe is that in parallel interface register read AD7606B returns ADC data only not the register data. we checked in oscilloscope our parallel read command goes like

read command (WR signal low) 0xAF00 (D15 = 1 , address = 0x2f) followed by read (RD signal low). but we get ADC data only in return  instead of value 0x14 as per datasheet. we checked on hardware  OS[2:0] =1, i.e its in software mode.

we initially posted this question in  Precision ADC forum from there we diverted to this forum.

request you to kindly suggest for our issue.

thanks,

shivashankar

Without seeing your code, we can't provide any further recommendations.

Please share the output of:

#git diff drivers/iio/adc

-Michael

0001-Ad7606b-Added-the-driver-code-for-ad7606b.txt

Hi ,

please find the attached changes fot the ad7606b.

Regards,

Shivashankar Thati

Thanks for posting, but the patch seems to be corrupted can you please upload it again?

Hi,

i uploaded the text file of the all modifications we have done for ad7606b.patch file is not uploading here.so i copied the content in the patch into text file and uploaded.

Regards,

Shivashankar Thati

Please see here:

/cfs-file/__key/communityserver-discussions-components-files/422/0001_2D00_Ad7606b_2D00_Added_2D00_the_2D00_driver_2D00_code_2D00_for_2D00_ad7606b.txt

The file is corrupted towards the end...

-Michael

5875.0001-Ad7606b-Added-the-driver-code-for-ad7606b.txt

sharing you new patch file .please find here.

Regards,

Shivashankar Thati

hi michael,

Did you get any clue from the code for our issue : register read not working in AD7606b parallel interface.

basically AD7606 is not entering register mode remains in ADC mode. we check all OS0-2 are set one. also R/W command is set 1 with WR low in 1st transaction with address 0x2f which make AD7606b move in register mode and WR latches the address in AD7606B. now in second transaction with RD low should return that address value but instead it sends ADC data not register data.(ADC mode).

kindly check and help us for the solution.

thanks and regards,

shivashankar.

It's really hard to tell without seeing a complete register read access cycle on a logic analyzer!

You have some HDL core doing those accesses, and it's difficult to say what they really do.

Two things worth looking into:

1) Maybe you need a memory barrier between the write and read?

• https://developer.arm.com/documentation/den0013/d/Memory-Ordering/Memory-barriers/Linux-use-of-barriers
• https://github.com/torvalds/linux/blob/master/Documentation/memory-barriers.txt

2) Maybe your write causes and additional access which resets register mode and transitions back to ADC mode.

You get certainty only by using a logic analyzer.

If you captured the entire access and things still don't work. All SW will be out of equitation and you can progress back to: https://ez.analog.com/data_converters/precision_adcs

-Michael

It's really hard to tell without seeing a complete register read access cycle on a logic analyzer!

You have some HDL core doing those accesses, and it's difficult to say what they really do.

Two things worth looking into:

1) Maybe you need a memory barrier between the write and read?

• https://developer.arm.com/documentation/den0013/d/Memory-Ordering/Memory-barriers/Linux-use-of-barriers
• https://github.com/torvalds/linux/blob/master/Documentation/memory-barriers.txt

2) Maybe your write causes and additional access which resets register mode and transitions back to ADC mode.

You get certainty only by using a logic analyzer.

If you captured the entire access and things still don't work. All SW will be out of equitation and you can progress back to: https://ez.analog.com/data_converters/precision_adcs

-Michael

Hi Michael,

we found the problem, we basically referred ADI AXI_AD7616 HDL code, and its logic was not able to meet WR_N signal specification. specs : WR_N low time  required min 88ns, actual having 60ns. 

so we modified the HDL code to make WR_N  low time to 100ns , and now  register read is working in AD7606B parallel mode.

thanks,

shivashankar thati