dac_fmc_ebz Reference Design with AD9171 & zcu102

I'm using the dac_fmc_ebz reference project for the zcu102 with the AD9171 eval board and modifying the config.tcl script to create a single-link project for the ad9171 in JESD mode 3.  It generates the BIT file without any issue.  Then I use the Linux repo from the ADI github and modify the ad9172 devicetree files for the ad9171.  Mostly by replacing ad9172 with ad9171 where needed and using JESD mode 3 as opposed to 10 and changing the octets per frame to 2. The board is attached to the zcu102's HPC0 FMC connector.

The DAC is configured to have a rate of 3GHz with 12x interpolation.  For the HMC settings, I tried many different options but mostly stuck to dividing the HMC's PLL 2.94912 GHz clock by 8 and 24.  8 was the default and generated a clock of ~365 MHz and 24 because that generated a clock of 122.88 MHz, which is 1/40 of the lane rate. 

However, no matter what settings I attempt, no JESD lanes on the dac moves past the CGS and SYNCn is never deasserted.  The dac's PLLs are locked but there is no other status or errors that I could find.  I verified I could write to and read from the dac with iio_reg.

dmesg doesn't report any errors

[ 6.054126] axi_adxcvr 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.02.a) using QPLL on GTH4 at 0x84A.
[ 6.065920] axi-jesd204-tx 84a90000.axi-jesd204-tx: AXI-JESD204-TX (1.06.a) at 0x84A90000. Encoder.
[ 6.079476] ad9172 spi1.1: AD916x DAC Chip ID: 4
[ 6.084092] ad9172 spi1.1: AD916x DAC Product ID: 9171
[ 6.089227] ad9172 spi1.1: AD916x DAC Product Grade: 0
[ 6.094356] ad9172 spi1.1: AD916x DAC Product Revision: 2
[ 6.099747] ad9172 spi1.1: AD916x Revision: 1.1.1
[ 6.104444] ad9172 spi1.1: PLL Input rate 122880000

[ 6.440347] ad9172 spi1.1: PLL lock status 1, DLL lock status: 1
[ 6.664302] ad9172 spi1.1: Serdes PLL Locked (stat: 3)
[ 6.776637] ad9172 spi1.1: code_grp_sync: 0
[ 6.780815] ad9172 spi1.1: frame_sync_stat: 0
[ 6.785163] ad9172 spi1.1: good_checksum_stat: 0
[ 6.789771] ad9172 spi1.1: init_lane_sync_stat: 0
[ 6.794467] ad9172 spi1.1: 2 lanes @ 4915200 kBps
[ 6.799729] ad9172 spi1.1: Probed.
[ 6.824532] cf_axi_dds 84a04000.axi-ad9171-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 02

And when I status jesd, it looks ok

Link is enabled
Measured Link Clock: 368.672 MHz
Reported Link Clock: 368.640 MHz
Measured Device Clock: 368.672 MHz
Reported Device Clock: 368.640 MHz
Desired Device Clock: 122.880 MHz
Lane rate: 4915.200 MHz
Lane rate / 40: 122.880 MHz
LMFC rate: 7.680 MHz
SYNC~: asserted
Link status: CGS
SYSREF captured: Yes
SYSREF alignment error: No

Note: When I set the ref clock have a divider of 24 at the HMC, the desired matches the measured & report device clock, but that doesn't effect anything.

Parents Reply
  • Michael,

    Thanks for the tip.  Doubling the rate (and setting clock dividers to match) got me past my problem.  It was still failing the ILA stage, but I was able to figure out that I had the wrong sysref frequency divider for the hmc and set that to the correct value.

    Do you have any more insight into why increasing the speed helped the problem?  The rate I had (~5Gbps) is within supported range given in the AD9171 datasheet.