Bring up AD9001 - Device driver error

Hi All,

during building of the AD-9001 at our custom board using the HDF repo: adrv9001_zed and DTS based on:  zynq-zed-adv7511-adrv9002

we got the following error during boot time:

adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Memory_ReadWrite_Validate, in line 357, variable name address.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Memory_Write, in line 403, variable name NULL.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_powermanagement.c, in function adi_adrv9001_powermanagement_Configure, in line 56, variable name NULL.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: adrv9002_power_mgmt_config, 2142: failed with "Invalid ARM Memory Address" (1)
adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Memory_ReadWrite_Validate, in line 357, variable name address.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_arm.c, in function adi_adrv9001_arm_Memory_Write, in line 403, variable name NULL.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: [ERROR]: Error number 1 (0x00000001), Recovery action -2.In file drivers/iio/adc/navassa/devices/adrv9001/public/src/adi_adrv9001_powermanagement.c, in function adi_adrv9001_powermanagement_Configure, in line 56, variable name NULL.Error message Invalid ARM Memory Address.
adrv9002 spi0.0: adrv9002_power_mgmt_config, 2142: failed with "Invalid ARM Memory Address" (1)
cf_axi_adc: probe of 44a00000.axi-adrv9002-rx-lpc failed with error -22
cf_axi_tdd 44a0c800.axi-adrv9002-core-tdd1-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.⚌
cf_axi_tdd 44a0cc00.axi-adrv9002-core-tdd2-lpc: Major version mismatch between PCORE and driver. Driver expected 1.00.a, PCORE reported 173.222.⚌
Division by zero in kernel.

the communication from FPGA layer to AD is based on SPI-0 (the I2C domain is disabled).

due to mention errors in the IIOScope utility we don`t see the RF response although it probably found the  IPC (Tx signals) as can you see here:

After investigate the device (9001) drive code: it seems that the issue come from the line: 

address >= ADRV9001_ADDR_ARM_START_PROG && address <= ADRV9001_ADDR_ARM_END_PROG (at File: adi_adrv9001_arm), it seems like an PL physically address error rather then issue at the dts / Linux (PS) side.

Please assist us to overcome this issue, the time is critical for us.

Thanks a`lot,

Roee.   



edit line
[edited by: Roee Zi at 9:36 PM (GMT -4) on 28 Jun 2021]
Parents
  • 0
    •  Analog Employees 
    on Jun 29, 2021 7:12 AM

    Hi Roee,

    It looks something very odd is going on as the TDD cores are also not coming up correctly. I will have to see if I can replicate this on my side... Are you using the master branches (on both hdl and linux) or are you using a release branch?

    - Nuno Sá

  • Hi,

    The kernel device driver are not the most update. but they exist.

    the Meta-ADI is point to 2019_R2 and the HDF design also.

    i don`t knew if it related but i build the project with PetaLinux 2019 R1 and not 2019 R2.

    i attached in the follow link the driver files as they appear my workstation.

    https://www.jumbomail.me/j/nbzMpoRiVkabqRc

    i can try to update the AD9001 kernel driver to latest master version, but don`t sure this is the reason for this issue.

    Thanks,

    Roee.  

  • 0
    •  Analog Employees 
    on Jul 6, 2021 7:41 AM in reply to Roee Zi

    Hi,

    Unfortunately no. This is the place where we are allowed to do support...

    - Nuno Sá

  • Hi Nsa, 

    There is some process.... 

    After investigation again the describe issues, we found that all of them are coming from heat conditions, the ADI chip was far beyond this temperature limit (around 120 Celsius). with damage the SPI communication.

    We fixed it and now we process to new issue: mismatch between major version: PCORE (expected: 1.00) and driver report (173.222).

    As you can see below.

    We think that our base ADI git repo is the issue here, please tell us how to fix it.

    Thanks again,

    Roee.  

  • 0
    •  Analog Employees 
    on Jul 9, 2021 7:53 AM in reply to Roee Zi

    Hi Roee,

    Glad that you're making progress.

    axi_sysid 45000000.axi-sysid-0: [adrv9001] on [zed] git <4ae19031c0b8302472d081c01ca946cee3b84db7> clean [2021-06-13 11:58:35] UTC

    Looking closely at this it looks like your hdl build still does not have support for TDD. Your commit point here. While, the core only started to be supported here. Hence, you need to have a more recent build of the 2019_R2 branch if you want to use this core. Alternatively, if you don't really need it (this only makes sense if you intend to use Time Division Duplex based profiles), you can remove from the design to save space.

    - Nuno Sá

  • Hi,

    can you be more specific on your offer solutions:

    a. If i want align PS and PL what GIT repo should i take and where to set it ? (in what file in the PetaLinux build files).

    b. If i want to remove the support of TDD, where I set it ? delete nodes from the system_user.dtsi files? which nodes...

    Thanks a lot,

    Roee. 

  • 0
    •  Analog Employees 
    on Jul 9, 2021 10:38 AM in reply to Roee Zi

    Hi,

    As for a), you need to rebuild your hdl project and base it on the latest 2019_r2 branch so that you have the tdd core available and possible some other fixes for the adrv9001 core. Then, you need to rebuild your petalinux project with the new *.hdf file.

    For b), you need to think if you need/want the core or not. If you do not want it, you have to remove it from the hdl project and rebuild it. On the petalinux side, you can then delete the nodes in system_user.dtsi as you are saying... Here and here are the nodes.

    If you want to go with b) and remove the TDD cores from the hdl project let me know as I will have to ask someone from the team to help and assist you in this thread on how to do it.

    - Nuno Sá

Reply
  • 0
    •  Analog Employees 
    on Jul 9, 2021 10:38 AM in reply to Roee Zi

    Hi,

    As for a), you need to rebuild your hdl project and base it on the latest 2019_r2 branch so that you have the tdd core available and possible some other fixes for the adrv9001 core. Then, you need to rebuild your petalinux project with the new *.hdf file.

    For b), you need to think if you need/want the core or not. If you do not want it, you have to remove it from the hdl project and rebuild it. On the petalinux side, you can then delete the nodes in system_user.dtsi as you are saying... Here and here are the nodes.

    If you want to go with b) and remove the TDD cores from the hdl project let me know as I will have to ask someone from the team to help and assist you in this thread on how to do it.

    - Nuno Sá

Children
  • Hi Nsa,

    Thank you about your detailed answer. 

    Secondly, we have question about TDD_SYNC signal that exist on Zed EVB:

    How should I use the TDD_SYNC signal after adding it to the HDL project?

    The TDD_SYNC pin is connected to JA1.JA1 PMOD connector on the Zedboard.

    But it is not clear what physical signal should be connected to this pin. 

    Thanks,

    Roee. 

     

  • Hi Nuno Sá.

    My name is Amir and I'm working with Roee on this project.

    I'm the FPGA designer of the project.

    I would like to consult with you about the correct GIT version that we should use for building the FPGA PL project which is based on a Zedboard EVB.

    I have built the project after cloning it from the branch of HDL_2019_R2, which uses the Vivado 2019.1 version. But on this basic branch, as was cloned from the GIT, there was no support in TDD_Sync functionality.

    Next, I have cloned and built the project by using the branch of Master, which requires the using of Vivado 2020.1. On this project the TDD_Sync is supported but the Vivado's Block-Diagram requires some IP's to be upgraded. Once they were upgraded, there was appeared a mismatch between the IP's and the source files. (The TDD_Sync and some RX_Enable / TX_Enable signals are not supported.)
    I've also seen that these IP's versions were originally equal the recommended version. So I don't understand why there were needed to be upgraded?
    May I ignore this IPs upgrade requirement?
    And, can I use the IP's from this project (branch Master) for building the project of Vivado 2019.1 (of branch HDM_2019_R2)?

    I have also tried using this branch link:
    https://github.com/analogdevicesinc/hdl/tree/2cbb4f7b75cdb20b0b6c125dc493b86cdb837242

    but while building the project (by invoking the "make" command) I got the error:

    ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'

    I would like to ask if there is a stable version of the project that I can use with the Vivado 2019.1?

    Thanks,

    Amir

     

  • 0
    •  Analog Employees 
    on Jul 12, 2021 12:12 PM in reply to Amir_M

    Hi Amir,

    I would like to consult with you about the correct GIT version that we should use for building the FPGA PL project which is based on a Zedboard EVB.

    You can still use "HDL_2019_R2". You just have to update your local branch so that you use the newest code base. TDD_SYNC is already supported in 2019_R2 (just not on your git local copy). So, just sync up you git branch with our 2019_R2 and you should be fine with TDD...

    And, can I use the IP's from this project (branch Master) for building the project of Vivado 2019.1 (of branch HDM_2019_R2)?

    Probably not a good idea...

    Note that I'm not an hdl/FPGA engineer (I concentrate on the linux side), so if you still have some FPGA questions, let me know and I will ask the right person to jump in this thread...

    I would like to ask if there is a stable version of the project that I can use with the Vivado 2019.1

    Just to reinforce, the current stare of 2019_R2 should be stable... Just update your local copy.

    - Nuno Sá

  • Hi Nuno,

    I have succeeded in downloading the updated branch of HDL_2019_R2, which contains the TDD_Sync functionality and some additional improvements since the last released branch.

    We would like if you can answer us the question of Roee:

    How should we use the TDD_SYNC signal after adding it to the HDL project?

    What signal mechanism should drive the pin JA1.JA1 at the PMOD connector on the Zedboard?

    Thanks,

    Amir

  • 0
    •  Analog Employees 
    on Jul 14, 2021 11:08 AM in reply to Amir_M

    Hi Amir, 

    the tdd_sync can be driven with an external pps signal, the TDD core from the AXI_ADRV9001 will resynchronize to that every time it receives a pulse.   If TDD is not required you can ignore this signal.  

    From HDL you can disable the TDD core by setting the TDD_DISABLE parameter of the IP.

    https://github.com/analogdevicesinc/hdl/blob/master/library/axi_adrv9001/axi_adrv9001.v#L41

    Thank you,

    Laszlo