HMC7044 Configuration on ADRV9009-ZU11EG with FMCOMMS8

Hi,

We are looking to design a custom carrier board to support the ZU11EG SOM and FMCOMMS8 daughterboard and I wanted to raise a few questions about the proper configuration of the HMC7044(s)

  • It seems that the HMC7044 on the carrier board is required to provide common, length matched CLKIN/RFSYNCIN inputs into the HMC7044s on the SOM and the FMCOMMS8. Is this correct or is there some way to achieve synchronization between the SOM and the daughterboard without a separate HMC7044 on the carrier?
  • Our clock source will be a GPS module with both a 10 MHz and 1 PPS output. On 2019R2, we have attempted to configure the SOM HMC7044 for a 10 MHz input on CLKIN2. However, when we attempt to configure this via the device tree, it seems the hmc7044 driver comes up with some improper values for the PLL dividers, including setting the OSCIN prescaler value at 0x0020 to 0. We were only able to achieve lock to 10 MHz by manually writing several registers. Does the driver not support a 10 MHz input and will we need update this for our application?
  • On 2019R2, it appears that the SOM and daughterboard HMC7044s are both configured to favor CLKIN1 for PLL1 and then uses CLKIN0/RFSYNC as RFSYNC. It seems like both of these are fed from the carrier HMC7044 outputs at 30.72 MHz (/96 on those outputs). Separately, it also seems that the SYNC inputs are also fed by 3.84 MHz (/768 on those outputs) outputs from the carrier HMC7044. Is this correct? Are both SYNC and RFSYNC required are are those the correct input frequencies?
  • Based on the above, it would seem that what we would need to do to clock off of the GPS module would be to configure the carrier HMC7044 to accept 10 MHz on CLKIN1 and then the SOM and the daughterboard will be fed from the carrier outputs? Should we also use the 1PPS_SYNC output as a RF SYNC on CLKIN0/RFSYNC or can we connect 1 PPS to the SYNC input on the carrier HMC7044?

Thanks!

Top Replies

    •  Analog Employees 
    May 21, 2021 +2 verified
    It seems that the HMC7044 on the carrier board is required to provide common, length matched CLKIN/RFSYNCIN inputs into the HMC7044s on the SOM and the FMCOMMS8. Is this correct or is there…
Parents
  • +1
    •  Analog Employees 
    on May 21, 2021 1:58 PM
    It seems that the HMC7044 on the carrier board is required to provide common, length matched CLKIN/RFSYNCIN inputs into the HMC7044s on the SOM and the FMCOMMS8. Is this correct or is there some way to achieve synchronization between the SOM and the daughterboard without a separate HMC7044 on the carrier?

    The HMC7044 on the carrier is required. Especially if you want to synchronize multiple carriers.

    We can alternatively use two different clock distribution strategies.

    Reference distribution: (used today)

    A low 30.720MHz reference clock is used between the different HMC7044 clock chips in the topology. In this mode PLL1 and PLL2 are used and the clock tree is synchronized using SYNC (don’t confuse with RFSYNC) SYNC can be used to synchronize across PLL1 and PLL2.

    Clock distribution:

    A high reference clock is distributed and the downstream HMC7044 clock chips accept this clock via FIN/CLKIN1 and the system is synchronized using RFSYNC/CLKIN0. In this mode the downstream HMC7044s are used like HMC7043 and PLL1 and PLL2 are bypassed.  

    Our clock source will be a GPS module with both a 10 MHz and 1 PPS output. On 2019R2, we have attempted to configure the SOM HMC7044 for a 10 MHz input on CLKIN2. However, when we attempt to configure this via the device tree, it seems the hmc7044 driver comes up with some improper values for the PLL dividers, including setting the OSCIN prescaler value at 0x0020 to 0. We were only able to achieve lock to 10 MHz by manually writing several registers. Does the driver not support a 10 MHz input and will we need update this for our application?

    This sounds like a SW bug we need to investigate. However, using 10MHz to lock the 122.880MHz VCXO requires very large dividers, which are suboptimal form a phase noise performance point of view. And are therefore not recommended. On the ZU11EG carrier we have a AD9545 which can accept a 1PPS or 10MHz reference, clean it up and provide a 30.72 or 122.880 clock output which is then used by the HMC7044 as reference.

    We’re currently testing this, and SW support will be committed soon.

    On 2019R2, it appears that the SOM and daughterboard HMC7044s are both configured to favor CLKIN1 for PLL1 and then uses CLKIN0/RFSYNC as RFSYNC. It seems like both of these are fed from the carrier HMC7044 outputs at 30.72 MHz (/96 on those outputs). Separately, it also seems that the SYNC inputs are also fed by 3.84 MHz (/768 on those outputs) outputs from the carrier HMC7044. Is this correct? Are both SYNC and RFSYNC required are are those the correct input frequencies?

    For reference distribution we use SYNC. You only need a single pulse; however we configure it suitable for JESD204 SYSREF to a multiple of the LMFC. But then we request single pulses, aligned to the LMFC.

    Based on the above, it would seem that what we would need to do to clock off of the GPS module would be to configure the carrier HMC7044 to accept 10 MHz on CLKIN1 and then the SOM and the daughterboard will be fed from the carrier outputs? Should we also use the 1PPS_SYNC output as a RF SYNC on CLKIN0/RFSYNC or can we connect 1 PPS to the SYNC input on the carrier HMC7044?

    Stay tuned for the AD9545 support.

    -Michael

Reply
  • +1
    •  Analog Employees 
    on May 21, 2021 1:58 PM
    It seems that the HMC7044 on the carrier board is required to provide common, length matched CLKIN/RFSYNCIN inputs into the HMC7044s on the SOM and the FMCOMMS8. Is this correct or is there some way to achieve synchronization between the SOM and the daughterboard without a separate HMC7044 on the carrier?

    The HMC7044 on the carrier is required. Especially if you want to synchronize multiple carriers.

    We can alternatively use two different clock distribution strategies.

    Reference distribution: (used today)

    A low 30.720MHz reference clock is used between the different HMC7044 clock chips in the topology. In this mode PLL1 and PLL2 are used and the clock tree is synchronized using SYNC (don’t confuse with RFSYNC) SYNC can be used to synchronize across PLL1 and PLL2.

    Clock distribution:

    A high reference clock is distributed and the downstream HMC7044 clock chips accept this clock via FIN/CLKIN1 and the system is synchronized using RFSYNC/CLKIN0. In this mode the downstream HMC7044s are used like HMC7043 and PLL1 and PLL2 are bypassed.  

    Our clock source will be a GPS module with both a 10 MHz and 1 PPS output. On 2019R2, we have attempted to configure the SOM HMC7044 for a 10 MHz input on CLKIN2. However, when we attempt to configure this via the device tree, it seems the hmc7044 driver comes up with some improper values for the PLL dividers, including setting the OSCIN prescaler value at 0x0020 to 0. We were only able to achieve lock to 10 MHz by manually writing several registers. Does the driver not support a 10 MHz input and will we need update this for our application?

    This sounds like a SW bug we need to investigate. However, using 10MHz to lock the 122.880MHz VCXO requires very large dividers, which are suboptimal form a phase noise performance point of view. And are therefore not recommended. On the ZU11EG carrier we have a AD9545 which can accept a 1PPS or 10MHz reference, clean it up and provide a 30.72 or 122.880 clock output which is then used by the HMC7044 as reference.

    We’re currently testing this, and SW support will be committed soon.

    On 2019R2, it appears that the SOM and daughterboard HMC7044s are both configured to favor CLKIN1 for PLL1 and then uses CLKIN0/RFSYNC as RFSYNC. It seems like both of these are fed from the carrier HMC7044 outputs at 30.72 MHz (/96 on those outputs). Separately, it also seems that the SYNC inputs are also fed by 3.84 MHz (/768 on those outputs) outputs from the carrier HMC7044. Is this correct? Are both SYNC and RFSYNC required are are those the correct input frequencies?

    For reference distribution we use SYNC. You only need a single pulse; however we configure it suitable for JESD204 SYSREF to a multiple of the LMFC. But then we request single pulses, aligned to the LMFC.

    Based on the above, it would seem that what we would need to do to clock off of the GPS module would be to configure the carrier HMC7044 to accept 10 MHz on CLKIN1 and then the SOM and the daughterboard will be fed from the carrier outputs? Should we also use the 1PPS_SYNC output as a RF SYNC on CLKIN0/RFSYNC or can we connect 1 PPS to the SYNC input on the carrier HMC7044?

    Stay tuned for the AD9545 support.

    -Michael

Children