Help with two ADRV9008-2W/PCBZ on ZCU102

Hi,

I know this topic pops up regularly on EngineerZone forums. I have read a lot of posts and tried to follow all advices. Still, I am stuck at the moment and hope I can get some help to move further.

What I am trying to do is to make a ZCU102 with 2 ADRV9008-2 eval boards working with an adapted HDL reference design and AD Linux with an adapted device tree. My experiments are based on the 2019-R2 release.

What I did so far:

- Modified the ADRV9008-2W/PCBZ hardware to feed dev_clk and dev_sysref signals from the AD9528 on the first card (on FMC HPC0) to the second card (on FMC HPC1) according to instructions from Design support forum. The signals are there but still I am not sure if the hardware setup is correct.

- Modified the HDL reference design to include a second ADRV9008-2W/PCBZ on HPC0, the double number of lanes and converters, and hopefully connected all lanes, clocks, handshake signals etc. accordingly. The first card at HPC0 is connected to SPI0, the second one at HPC1 to SPI1. The design looks reasonable and builds fine, but still there might be errors.

- Use zynqmp-zcu102-rev10-adrv9008-2-jesd204-fsm.dts and includes as a start for a modified device tree. I added  clk1_ad9528:ad9528-2 and trx1_adrv9009:adrv9009-phy-b at spi1 and followed the example in zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts for the JESD204 setup.

The success is limited so far, see kernel log below. The second ad9528 is found, so spi2 seems to work. Apparently, there are problems with the JESD. The second adrv9009 is not found either.

My questions:

- Does any obvious configuration error spring to mind yet?

- What would be the next step to debug?

- What about MultichipSync initialization as required by UG1295? Do I have to do it explicitely (how?) or does the Linux kernel care for it?

Thank you in advance!

Best regards,

Erik

[ 1.530305] jesd204: created con: id=0, topo=0, link=0, /amba/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-tx@84a80000
[ 1.540914] jesd204: created con: id=1, topo=0, link=2, /amba/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@84a50000
[ 1.552332] jesd204: created con: id=2, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@84a50000 <-> /fpga-axi@0/axi-jesd204-rx-os@84ab0000
[ 1.564527] jesd204: created con: id=3, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@84a80000 <-> /fpga-axi@0/axi-jesd204-tx@84a90000
[ 1.576206] jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@84a90000 <-> /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000
[ 1.588420] jesd204: created con: id=5, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx-os@84ab0000 <-> /amba/spi@ff050000/adrv9009-phy-b@1
[ 1.600436] jesd204: created con: id=6, topo=0, link=0, /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000 <-> /amba/spi@ff050000/adrv9009-phy-b@1
[ 1.612666] jesd204: created con: id=7, topo=0, link=2, /amba/spi@ff050000/adrv9009-phy-b@1 <-> /amba/spi@ff040000/adrv9009-phy@1
[ 1.624241] jesd204: created con: id=8, topo=0, link=0, /amba/spi@ff050000/adrv9009-phy-b@1 <-> /amba/spi@ff040000/adrv9009-phy@1
[ 1.635819] jesd204: /amba/spi@ff040000/adrv9009-phy@1: JESD204[0] transition uninitialized -> initialized
[ 1.645408] jesd204: /amba/spi@ff040000/adrv9009-phy@1: JESD204[2] transition uninitialized -> initialized
[ 1.655009] jesd204: found 8 devices and 1 topologies
[ 3.013579] adi-axi-clkgen 83c00000.axi-clkgen: failed to get s_axi_aclk
[ 3.019176] adi-axi-clkgen 83c20000.axi-clkgen: failed to get s_axi_aclk
[ 3.412148] axi_sysid 85000000.axi-sysid-0: [adrv9009] on [zcu102] git <0> dirty [2021-04-29 12:11:06] UTC
[ 3.753705] zynqmp_clk_divider_set_rate() set divider failed for spi1_ref_div1, ret = -13
[ 4.114962] ad9528 spi1.0: spi1.0 supply vcc not found, using dummy regulator
[ 4.122124] ad9528 spi1.0: Linked as a consumer to regulator.0
[ 4.152846] jesd204: /amba/spi@ff040000/ad9528-1@0,jesd204:0,parent=spi1.0: Using as SYSREF provider
[ 4.162306] adrv9009 spi1.1: adrv9009_probe : enter
[ 4.172677] ad9528 spi2.0: spi2.0 supply vcc not found, using dummy regulator
[ 4.179854] ad9528 spi2.0: Linked as a consumer to regulator.0
[ 4.211481] adrv9009 spi2.1: adrv9009_probe : enter
[ 4.216558] adrv9009: probe of spi2.1 failed with error -2
[ 5.055369] cf_axi_dds 84a04000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9371
[ 5.072127] axi_adxcvr 84a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A50000. Number of lanes: 4.
[ 5.084505] axi_adxcvr 84a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTH4 at 0x84A80000. Number of lanes: 8.
[ 19.532190] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] invalid link state: initialized, exp: idle, nxt: idle
[ 19.532201] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'idle', got error -22
[ 19.532206] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: FSM completed with error -22
[ 19.532230] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] invalid link state: initialized, exp: idle, nxt: idle
[ 19.532236] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'idle', got error -22
[ 19.532241] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: FSM completed with error -22

  • 0
    •  Analog Employees 
    on Apr 30, 2021 11:32 AM

    Hi Erik,

    If you implement the jesd204-fsm, the driver and jesd204 subsystem will take are of multichip sync.

    You should first review this: https://wiki.analog.com/resources/tools-software/linux-drivers/jesd204/jesd204-fsm-framework

    BTW - there is a similar effort discussed here:

    https://ez.analog.com/linux-software-drivers/f/q-a/543712/how-to-configure-device-tree-to-use-more-than-one-adrv9009

    Maybe you get some pointers from it.

    Without your devicetrees it's hard to tell what's going on.

    -Michael

  • Hi Michael,

    thanks for the answer. I have already read the above links and tried to heed all advice as good as I could.

    My device tree is below, i.e. only the differences to the 2019-R2 distribution. The ### comments indicate that the following blocks are copied from the spi0 branches. I thought, in this short form it is more readable and hope I do not have forgotten something important. The gpio numbers reflect my HDL design. I have removed the adrv9009_gpio_?? lines since I could not find any usage of them within Linux driver. I will need some GPIOs for other purposes.

    As a next step I will check the ref_clk and sysref signals on the ADRC9008.2 boards using an oscilloscope, just in case.

    Best regards,

    Erik

    #include "zynqmp-zcu102-rev10-adrv9008-2-jesd204-fsm.dts"
    
    &spi1 {
        status = "okay";
    
        clk1_ad9528: ad9528-2@0 {
            ### ...
            ### copy of clk0_ad9528, changing ad9528-1 to ad9528-2
            ### only output channels 12 and 13
            ### ...
    	};
        trx1_adrv9009: adrv9009-phy-b@1 {
    		### ...
            ### copy of trx0_adrv9009	
            ### ...
        }
    }
    
    &trx0_adrv9009 {
        clock-output-names = "rx0_sampl_clk", "rx0_os_sampl_clk", "tx0_sampl_clk";
    
        jesd204-inputs =
            <&trx1_adrv9009 0 FRAMER_LINK_ORX>,
            <&trx1_adrv9009 0 DEFRAMER_LINK_TX>;
    };
    
    &trx1_adrv9009 {
        compatible = "adrv9008-2";
    
        clock-names = "jesd_tx_clk", "jesd_rx_os_clk",
            "dev_clk", "fmc_clk", "sysref_dev_clk", "sysref_fmc_clk";
    
        clocks = <&axi_adrv9009_tx_jesd>, <&axi_adrv9009_rx_os_jesd>,
            <&clk0_ad9528 8>, <&clk0_ad9528 5>, <&clk1_ad9528 12>, 
            <&clk1_ad9528 3>;
        clock-names = "jesd_tx_clk", "jesd_rx_os_clk",
            "dev_clk_1", "fmc_clk_1", "dev_sysref", "fmc_sysrev";
        clock-output-names = "rx1_sampl_clk", "rx1_os_sampl_clk", "tx1_sampl_clk";
    
        reset-gpios = <&gpio 121 0>;
        test-gpios = <&gpio 122 0>;
        sysref-req-gpios = <&gpio 127 0>;
        tx2-enable-gpios = <&gpio 125 0>;
        tx1-enable-gpios = <&gpio 126 0>;
    
        jesd204-device;
        jesd204-inputs =
            <&axi_adrv9009_rx_os_jesd 0 FRAMER_LINK_ORX>,
            <&axi_adrv9009_core_tx 0 DEFRAMER_LINK_TX>;
        /delete-property/ interrupts;
    };
    
    &clk0_ad9528 {
        ad9528_0_c5: channel@5 {
            reg = <5>;
            adi,extended-name = "FMC_CLK_1";
            adi,driver-mode = <DRIVER_MODE_LVDS>;
            adi,divider-phase = <0>;
            adi,channel-divider = <5>;
            adi,signal-source = <SOURCE_VCO>;
        };
    
        ad9528_0_c8: channel@8 {
            reg = <8>;
            adi,extended-name = "DEV_CLK_1";
            adi,driver-mode = <DRIVER_MODE_LVDS>;
            adi,divider-phase = <0>;
            adi,channel-divider = <5>;
            adi,signal-source = <SOURCE_VCO>;
        };
    
        ad9528_0_c7: channel@7 {
            reg = <7>;
            adi,extended-name = "DEV_SYSREF_1";
            adi,driver-mode = <DRIVER_MODE_LVDS>;
            adi,divider-phase = <0>;
            adi,channel-divider = <5>;
            adi,signal-source = <SOURCE_SYSREF_VCO>;
        };
    };
    
    &clk1_ad9528 {
        adi,sysref-src = <SYSREF_SRC_EXTERNAL>;
        adi,sysref-pattern-mode = <SYSREF_PATTERN_NSHOT>;
        /delete-property/ adi,sysref-request-enable;
        adi,sysref-nshot-mode = <SYSREF_NSHOT_8_PULSES>;
    };
    

  • 0
    •  Analog Employees 
    on Apr 30, 2021 1:11 PM in reply to EHeinz689

    HI Erik,

    [ 4.216558] adrv9009: probe of spi2.1 failed with error -2

    -2 means ENOENT 

    https://github.com/torvalds/linux/blob/master/include/uapi/asm-generic/errno-base.h#L6

    one things that caches my eyes  -

    clock-names = "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk_1", "fmc_clk_1", "dev_sysrev";

    You should not alter the clock-names otherwise the driver wont match them.

    In fact for the jesd204-fsm case you only need "dev_clk"

    So this should be sufficient:

    clocks = <&clk0_ad9528 8>;

    clock-names = "dev_clk";

    -Michael

  • Thanks Michael, this helped a lot. I got a step further now, see below. The remaining error messages are:

    [ 6.026004] adrv9009 spi2.1: adrv9009_jesd204_setup_stage1:5763 Unexpected MCS sync status (0x0)
    [ 6.034790] jesd204: /amba/spi@ff050000/adrv9009-phy-b@1,jesd204:2,parent=spi2.1: JESD204[2] got error from cb: -14
    [ 6.045224] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_setup', got error -14
    [ 6.293268] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: FSM completed with error -14

    By the way, so far I failed to measure  the actual ref_clk and sysref signals during operation, since they are not accessible from the top of the PCB. Don't know how ather people did it. So the hardware status is still not clear. Can I check by other means if the ADRV9008-2 gets proper ref_clk and sysref?

    Best regards,

    Erik

    [ 1.530623] jesd204: created con: id=0, topo=0, link=0, /amba/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-tx@84a80000
    [ 1.541243] jesd204: created con: id=1, topo=0, link=2, /amba/spi@ff040000/ad9528-1@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@84a50000
    [ 1.552660] jesd204: created con: id=2, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@84a50000 <-> /fpga-axi@0/axi-jesd204-rx-os@84ab0000
    [ 1.564855] jesd204: created con: id=3, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@84a80000 <-> /fpga-axi@0/axi-jesd204-tx@84a90000
    [ 1.576534] jesd204: created con: id=4, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@84a90000 <-> /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000
    [ 1.588748] jesd204: created con: id=5, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx-os@84ab0000 <-> /amba/spi@ff050000/adrv9009-phy-b@1
    [ 1.600764] jesd204: created con: id=6, topo=0, link=0, /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000 <-> /amba/spi@ff050000/adrv9009-phy-b@1
    [ 1.612994] jesd204: created con: id=7, topo=0, link=2, /amba/spi@ff050000/adrv9009-phy-b@1 <-> /amba/spi@ff040000/adrv9009-phy@1
    [ 1.624569] jesd204: created con: id=8, topo=0, link=0, /amba/spi@ff050000/adrv9009-phy-b@1 <-> /amba/spi@ff040000/adrv9009-phy@1
    [ 1.636147] jesd204: /amba/spi@ff040000/adrv9009-phy@1: JESD204[0] transition uninitialized -> initialized
    [ 1.645737] jesd204: /amba/spi@ff040000/adrv9009-phy@1: JESD204[2] transition uninitialized -> initialized
    [ 1.655337] jesd204: found 8 devices and 1 topologies
    [ 3.401838] axi_sysid 85000000.axi-sysid-0: [adrv9009] on [zcu102] git <0> dirty [2021-04-29 12:11:06] UTC
    [ 3.742905] zynqmp_clk_divider_set_rate() set divider failed for spi1_ref_div1, ret = -13
    [ 4.102904] ad9528 spi1.0: spi1.0 supply vcc not found, using dummy regulator
    [ 4.110080] ad9528 spi1.0: Linked as a consumer to regulator.0
    [ 4.148951] jesd204: /amba/spi@ff040000/ad9528-1@0,jesd204:0,parent=spi1.0: Using as SYSREF provider
    [ 4.158416] adrv9009 spi1.1: adrv9009_probe : enter
    [ 4.168919] ad9528 spi2.0: spi2.0 supply vcc not found, using dummy regulator
    [ 4.176080] ad9528 spi2.0: Linked as a consumer to regulator.0
    [ 4.208395] adrv9009 spi2.1: adrv9009_probe : enter
    [ 5.067723] cf_axi_dds 84a04000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9371
    [ 5.084511] axi_adxcvr 84a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A50000. Number of lanes: 4.
    [ 5.096820] axi_adxcvr 84a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTH4 at 0x84A80000. Number of lanes: 8.
    [ 5.110681] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition initialized -> probed
    [ 5.121827] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition initialized -> probed
    [ 5.132957] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition probed -> idle
    [ 5.143471] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition probed -> idle
    [ 5.153987] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition idle -> device_init
    [ 5.164938] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition idle -> device_init
    [ 5.175895] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition device_init -> link_init
    [ 5.187282] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition device_init -> link_init
    [ 5.198673] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_init -> link_supported
    [ 5.210312] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_init -> link_supported
    [ 5.222095] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_supported -> link_pre_setup
    [ 5.234187] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_supported -> link_pre_setup
    [ 5.246274] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
    [ 5.258439] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
    [ 5.270604] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
    [ 5.282857] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
    [ 5.295111] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
    [ 5.307364] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
    [ 5.319616] jesd204: /fpga-axi@0/axi-jesd204-rx-os@84ab0000,jesd204:5,parent=84ab0000.axi-jesd204-rx-os: Possible instantiation for multiple chips; HDL lanes 4, Link[2] lanes 2
    [ 5.335351] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: Possible instantiation for multiple chips; HDL lanes 8, Link[0] lanes 4
    [ 5.351665] adrv9009 spi2.1: ADIHAL_resetHw
    [ 5.672836] adrv9009 spi1.1: ADIHAL_resetHw
    [ 6.002188] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage3 -> link_setup
    [ 6.014009] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage3 -> link_setup
    [ 6.026004] adrv9009 spi2.1: adrv9009_jesd204_setup_stage1:5763 Unexpected MCS sync status (0x0)
    [ 6.034790] jesd204: /amba/spi@ff050000/adrv9009-phy-b@1,jesd204:2,parent=spi2.1: JESD204[2] got error from cb: -14
    [ 6.045224] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: Rolling back from 'link_setup', got error -14
    [ 6.056528] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_setup -> opt_setup_stage1
    [ 6.068434] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_setup -> opt_setup_stage1
    [ 6.080346] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition opt_setup_stage1 -> link_setup
    [ 6.092256] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition opt_setup_stage1 -> link_setup
    [ 6.104169] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_setup -> clk_sync_stage3
    [ 6.115987] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_setup -> clk_sync_stage3
    [ 6.127806] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
    [ 6.140059] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
    [ 6.152312] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
    [ 6.164566] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
    [ 6.176818] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
    [ 6.188986] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
    [ 6.201155] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_pre_setup -> link_supported
    [ 6.213230] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_pre_setup -> link_supported
    [ 6.225311] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_supported -> link_init
    [ 6.236955] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_supported -> link_init
    [ 6.248603] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition link_init -> device_init
    [ 6.259985] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition link_init -> device_init
    [ 6.271369] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[0] transition device_init -> idle
    [ 6.282321] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: JESD204[2] transition device_init -> idle
    [ 6.293268] jesd204: /amba/spi@ff040000/adrv9009-phy@1,jesd204:1,parent=spi1.1: FSM completed with error -14

    [repeated 2 times]

  • +1
    •  Analog Employees 
    on Apr 30, 2021 2:06 PM in reply to EHeinz689

    [ 6.026004] adrv9009 spi2.1: adrv9009_jesd204_setup_stage1:5763 Unexpected MCS sync status (0x0)

    This means that spi2.1 didn't receive an SYSREF pulse when it expected one.

    Multiple AD9528 can't be synced. 

    Ideally all clocks and SYSREFs come from a single chip.

    Add the -

    jesd204-sysref-provider;

    property to the second ad9528 - you won't get two synced chips but the boot should succeed.

    -Michael