AD9371 JESD204 Link Setup Failed

Hi,

I use AD9371 with my custom board which has Xilinx Zynq MPSoC. I initialize AD9371 with my No-OS project and I don't get any error about JESD204 Link Setup. But when I use it with Linux Application, I get an error about JESD204 Link Setup. I used the same configuration for AD9371 Eval Board with ZCU106. When I used it with Eval Board, I don't get this error. I also checked the output clocks of AD9528. I observe Sysref Pulses and Dev Clk which is 122.88 MHz. I add error log for JESD link Setup. What could be the reason for that error when I observe the clock signal correctly?

Regards,

3443.ad9371_jesd_init_error.txt
[    5.785180] cf_axi_adc 84a00000.axi-ad9371-rx-hpc: ADI AIM (10.01.b) at 0x84A00000 mapped to 0x(____ptrval____), probed ADC AD9371 as MASTER
[    5.816993] cf_axi_dds 84a04000.axi-ad9371-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9371
[    5.833367] axi_adxcvr 84a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A60000. Number of lanes: 2.
[    5.846897] axi_adxcvr 84a50000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A50000. Number of lanes: 2.
[    5.859169] axi_adxcvr 84a80000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTH4 at 0x84A80000. Number of lanes: 4.
[    5.873754] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition initialized -> probed
[    5.884719] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition initialized -> probed
[    5.895674] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition initialized -> probed
[    5.906629] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition probed -> idle
[    5.916969] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition probed -> idle
[    5.927306] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition probed -> idle
[    5.937649] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
[    5.948425] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
[    5.959197] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
[    5.969976] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
[    5.981184] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
[    5.992389] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
[    6.003608] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
[    6.015079] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
[    6.026545] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
[    6.038174] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
[    6.050088] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
[    6.061994] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
[    6.073899] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
[    6.085890] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
[    6.097876] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
[    6.109868] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.121946] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
[    6.134020] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.146099] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
[    6.158176] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
[    6.170250] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
[    6.285790] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    6.395134] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    6.401046] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
[    6.412076] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0] got error from cb: -5
[    6.423889] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
[    6.435359] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
[    6.447003] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
[    6.458643] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
[    6.470287] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
[    6.481932] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
[    6.493571] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
[    6.505215] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
[    6.517294] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
[    6.529368] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
[    6.541446] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
[    6.553524] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
[    6.565598] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
[    6.577676] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
[    6.589668] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
[    6.601655] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
[    6.613646] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
[    6.625551] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
[    6.637451] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
[    6.649356] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
[    6.660826] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
[    6.672293] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
[    6.683765] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
[    6.694974] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
[    6.706179] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
[    6.717389] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
[    6.728166] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
[    6.738937] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
[    6.749715] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
[    6.759883] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
[    6.770047] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
[    6.780216] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
[    6.790992] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
[    6.801763] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
[    6.812540] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
[    6.823750] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
[    6.834956] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
[    6.846170] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
[    6.857637] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
[    6.869104] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
[    6.880859] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
[    6.892773] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
[    6.904678] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
[    6.916589] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
[    6.928581] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
[    6.940570] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
[    6.952572] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.964646] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
[    6.976720] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.988799] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
[    7.000876] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
[    7.012949] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
[    7.128484] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    7.237845] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    7.243765] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
[    7.254800] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0] got error from cb: -5
[    7.266615] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
[    7.278082] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
[    7.289729] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
[    7.301367] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
[    7.313013] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
[    7.324657] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
[    7.336296] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
[    7.347941] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
[    7.360019] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
[    7.372093] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
[    7.384170] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
[    7.396250] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
[    7.408322] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
[    7.420402] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
[    7.432392] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
[    7.444381] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
[    7.456371] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
[    7.468277] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
[    7.480176] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
[    7.492082] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
[    7.503554] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
[    7.515028] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
[    7.526498] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
[    7.537708] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
[    7.548912] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
[    7.560122] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
[    7.570900] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
[    7.581671] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
[    7.592448] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
[    7.602617] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
[    7.612780] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
[    7.622948] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
[    7.633726] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
[    7.644498] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
[    7.655273] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
[    7.666485] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
[    7.677689] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
[    7.688905] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
[    7.700371] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
[    7.711836] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
[    7.723473] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
[    7.735384] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
[    7.747288] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
[    7.759203] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
[    7.771192] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
[    7.783179] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
[    7.795170] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
[    7.807248] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
[    7.819322] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
[    7.831404] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
[    7.843479] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
[    7.855553] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
[    7.970966] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    8.080311] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    8.086231] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
[    8.097265] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0] got error from cb: -5
[    8.109087] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
[    8.120556] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
[    8.132202] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
[    8.143842] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
[    8.155485] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
[    8.167130] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
[    8.178769] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
[    8.190413] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
[    8.202492] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
[    8.214566] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
[    8.226644] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
[    8.238723] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
[    8.250796] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
[    8.262874] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
[    8.274866] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
[    8.286853] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
[    8.298844] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
[    8.310749] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
[    8.322649] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
[    8.334553] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
[    8.346030] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
[    8.357500] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
[    8.368972] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
[    8.380180] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
[    8.391386] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
[    8.402596] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
[    8.413373] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
[    8.424146] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
[    8.434931] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> idle
[    8.445099] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> idle
[    8.455262] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> idle
[    8.465431] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition idle -> device_init
[    8.476207] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition idle -> device_init
[    8.486979] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition idle -> device_init
[    8.497756] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> link_init
[    8.508966] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> link_init
[    8.520171] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> link_init
[    8.531385] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> link_supported
[    8.542851] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> link_supported
[    8.554318] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> link_supported
[    8.565954] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_pre_setup
[    8.577864] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_pre_setup
[    8.589768] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_pre_setup
[    8.601684] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> clk_sync_stage1
[    8.613673] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> clk_sync_stage1
[    8.625659] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> clk_sync_stage1
[    8.637651] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
[    8.649730] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
[    8.661812] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
[    8.673892] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
[    8.685968] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
[    8.698042] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
[    8.813431] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    8.922776] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0
[    8.928695] axi-jesd204-tx 84a90000.axi-jesd204-tx: axi_jesd204_tx_jesd204_link_setup: Link0 enable lane clock failed (-5)
[    8.939729] jesd204: /fpga-axi@0/axi-jesd204-tx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-tx: JESD204[0] got error from cb: -5
[    8.951542] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: Rolling back from 'clk_sync_stage3', got error -5
[    8.963011] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> link_setup
[    8.974656] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> link_setup
[    8.986296] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> link_setup
[    8.997940] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_setup -> clk_sync_stage3
[    9.009584] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_setup -> clk_sync_stage3
[    9.021224] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_setup -> clk_sync_stage3
[    9.032868] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage3 -> clk_sync_stage2
[    9.044947] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage3 -> clk_sync_stage2
[    9.057021] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage3 -> clk_sync_stage2
[    9.069099] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage1
[    9.081177] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage1
[    9.093251] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage1
[    9.105329] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition clk_sync_stage1 -> link_pre_setup
[    9.117321] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition clk_sync_stage1 -> link_pre_setup
[    9.129308] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition clk_sync_stage1 -> link_pre_setup
[    9.141299] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_pre_setup -> link_supported
[    9.153204] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_pre_setup -> link_supported
[    9.165103] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_pre_setup -> link_supported
[    9.177009] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_supported -> link_init
[    9.188482] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_supported -> link_init
[    9.199955] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_supported -> link_init
[    9.211427] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition link_init -> device_init
[    9.222635] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition link_init -> device_init
[    9.233841] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition link_init -> device_init
[    9.245051] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[0] transition device_init -> idle
[    9.255827] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[1] transition device_init -> idle
[    9.266599] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: JESD204[2] transition device_init -> idle
[    9.277373] jesd204: /amba/spi@ff040000/ad9371-phy@1,jesd204:1,parent=spi0.1: FSM completed with error -5

  • 0
    •  Analog Employees 
    on Apr 15, 2021 7:35 AM

    Hi, 

    The QPLL does not seems to lock.

    1. Can you do a "cat /sys/kernel/debug/clk/clk_summary"   and   share the device tree you are using. 

    2. What reference clock are you feeding to the QPLL ? 

    3. What version of HDL are you using ? 

    Thank you

    Laszlo

  • Hi,

    My reference clock is 122.88 MHz and I observe it from input of FPGA. I use 122880000 MSPS for both tx and rx. I add clock summary ".txt" file. On clock summary, clock frequencies are shown as expected. "ad9528-1-out_1" is the reference clock for FPGA. "ad9528-1_out_12" is the device clock for AD9371. My reference design is "hdl_2019_r2".

    Thank you,

    3108.ad9371_clk_summary.txt
    root@ilgar:~# cat /sys/kernel/debug/clk/clk_summary 
                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     spi0.1-tx_sampl_clk                  1        1        0   122880000          0     0  50000
     spi0.1-obs_sampl_clk                 1        1        0   245760000          0     0  50000
     spi0.1-rx_sampl_clk                  0        0        0   122880000          0     0  50000
     ad9528-1_out3                        0        0        0       60000          0     0  50000
     ad9528-1_out12                       1        1        0  1228800000          0     0  50000
     ad9528-1_out1                        6        6        0  1228800000          0     0  50000
        axi_rx_os_clkgen                  0        0        0   122880000          0     0  50000
        axi_rx_clkgen                     0        0        0   122880000          0     0  50000
        axi_tx_clkgen                     0        0        0    61440000          0     0  50000
        tx_out_clk                        0        0        0  1228800000          0     0  50000
        tx_gt_clk                         0        0        0     2457600          0     0  50000
        rx_os_out_clk                     0        0        0  1228800000          0     0  50000
        rx_os_gt_clk                      0        0        0     4915200          0     0  50000
        rx_out_clk                        0        0        0  1228800000          0     0  50000
        rx_gt_clk                         0        0        0     4915200          0     0  50000
     ad9528-1_out13                       0        0        0       60000          0     0  50000
     dp_aclk                              0        0        0   100000000        100     0  50000
     aux_ref_clk                          0        0        0    27000000          0     0  50000
     gt_crx_ref_clk                       0        0        0   108000000          0     0  50000
     pss_alt_ref_clk                      0        0        0           0          0     0  50000
     video_clk                            0        0        0    27000000          0     0  50000
     pss_ref_clk                          2        2        2    33333333          0     0  50000
        vpll_post_src                     0        0        0    33333333          0     0  50000
        vpll_pre_src                      0        0        0    33333333          0     0  50000
           vpll_int                       0        0        0  2133333312          0     0  50000
              vpll_half                   0        0        0  1066666656          0     0  50000
                 vpll_int_mux             0        0        0  1066666656          0     0  50000
                    vpll                  0        0        0  1066666656          0     0  50000
                       dp_stc_ref_mux       0        0        0  1066666656          0     0  50000
                          dp_stc_ref_div1       0        0        0    21333334          0     0  50000
                             dp_stc_ref_div2       0        0        0      666667          0     0  50000
                                dp_stc_ref       0        0        0      666667          0     0  50000
                       dp_audio_ref_mux       0        0        0  1066666656          0     0  50000
                          dp_audio_ref_div1       0        0        0    30476191          0     0  50000
                             dp_audio_ref_div2       0        0        0    10158731          0     0  50000
                                dp_audio_ref       0        0        0    10158731          0     0  50000
                       vpll_to_lpd        0        0        0   533333328          0     0  50000
        dpll_post_src                     0        0        0    33333333          0     0  50000
        dpll_pre_src                      0        0        0    33333333          0     0  50000
           dpll_int                       0        0        0  2133333312          0     0  50000
              dpll_half                   0        0        0  1066666656          0     0  50000
                 dpll_int_mux             0        0        0  1066666656          0     0  50000
                    dpll                  0        0        0  1066666656          0     0  50000
                       pcie_ref_mux       0        0        0  1066666656          0     0  50000
                          pcie_ref_div1       0        0        0    88888888          0     0  50000
                             pcie_ref       0        0        0    88888888          0     0  50000
                       sata_ref_mux       0        0        0  1066666656          0     0  50000
                          sata_ref_div1       0        0        0    88888888          0     0  50000
                             sata_ref       0        0        0    88888888          0     0  50000
                       dpdma_ref_mux       0        0        0  1066666656          0     0  50000
                          dpdma_ref_div1       0        0        0   533333328          0     0  50000
                             dpdma_ref       0        0        0   533333328          0     0  50000
                       gdma_ref_mux       0        0        0  1066666656          0     0  50000
                          gdma_ref_div1       0        0        0   533333328          0     0  50000
                             gdma_ref       0        0        0   533333328          0     0  50000
                       dp_video_ref_mux       0        0        0  1066666656          0     0  50000
                          dp_video_ref_div1       0        0        0   106666666          0     0  50000
                             dp_video_ref_div2       0        0        0   106666666          0     0  50000
                                dp_video_ref       0        0        0   106666666          0     0  50000
                       dpll_to_lpd        0        0        0   533333328          0     0  50000
        apll_post_src                     0        0        0    33333333          0     0  50000
        apll_pre_src                      0        0        0    33333333          0     0  50000
           apll_int                       0        0        0  2666666640          0     0  50000
              apll_half                   0        0        0  1333333320          0     0  50000
                 apll_int_mux             0        0        0  1333333320          0     0  50000
                    apll                  0        0        0  1333333320          0     0  50000
                       acpu_mux           0        0        0  1333333320          0     0  50000
                          acpu            0        0        0  1333333320          0     0  50000
        rpll_post_src                     0        0        0    33333333          0     0  50000
        rpll_pre_src                      1        1        1    33333333          0     0  50000
           rpll_int                       1        1        1  2133333312          0     0  50000
              rpll_half                   1        1        1  1066666656          0     0  50000
                 rpll_int_mux             1        1        1  1066666656          0     0  50000
                    rpll                  1        1        1  1066666656          0     0  50000
                       adma_ref_mux       0        0        0  1066666656          0     0  50000
                          adma_ref_div1       0        0        0   533333328          0     0  50000
                             adma_ref       0        0        0   533333328          0     0  50000
                       spi0_ref_mux       1        1        1  1066666656          0     0  50000
                          spi0_ref_div1       1        1        1    29629630          0     0  50000
                             spi0_ref_div2       1        1        1    29629630          0     0  50000
                                spi0_ref       1        1        1    29629630          0     0  50000
                       rpll_to_fpd        0        0        0   533333328          0     0  50000
        iopll_post_src                    0        0        0    33333333          0     0  50000
        iopll_pre_src                     1        1        1    33333333          0     0  50000
           iopll_int                      1        1        1  2999999970          0     0  50000
              iopll_half                  1        1        1  1499999985          0     0  50000
                 iopll_int_mux            1        1        1  1499999985          0     0  50000
                    iopll                11       12        5  1499999985          0     0  50000
                       gem3_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem3_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem3_ref_ung       0        0        0    62500000          0     0  50000
                                gem3_ref       0        0        0    62500000          0     0  50000
                                   gem3_tx       0        0        0    62500000          0     0  50000
                       gem2_ref_ung_mux       1        1        0  1499999985          0     0  50000
                          gem2_ref_ung_div1       1        1        0   124999999          0     0  50000
                             gem2_ref_ung       1        1        0   124999999          0     0  50000
                                gem2_ref       2        2        0   124999999          0     0  50000
                                   gem2_tx       1        1        0   124999999          0     0  50000
                       gem1_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem1_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem1_ref_ung       0        0        0    62500000          0     0  50000
                                gem1_ref       0        0        0    62500000          0     0  50000
                                   gem1_tx       0        0        0    62500000          0     0  50000
                       gem0_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem0_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem0_ref_ung       0        0        0    62500000          0     0  50000
                                gem0_ref       0        0        0    62500000          0     0  50000
                                   gem0_tx       0        0        0    62500000          0     0  50000
                       pl3_ref_mux        1        1        0  1499999985          0     0  50000
                          pl3_ref_div1       1        1        0    46875000          0     0  50000
                             pl3_ref_div2       1        1        0     9375000          0     0  50000
                                pl3_ref       1        1        0     9375000          0     0  50000
                       pl2_ref_mux        1        1        0  1499999985          0     0  50000
                          pl2_ref_div1       1        1        0   299999997          0     0  50000
                             pl2_ref_div2       1        1        0   299999997          0     0  50000
                                pl2_ref       4        4        0   299999997          0     0  50000
                       pl1_ref_mux        1        1        0  1499999985          0     0  50000
                          pl1_ref_div1       1        1        0   249999998          0     0  50000
                             pl1_ref_div2       1        1        0   249999998          0     0  50000
                                pl1_ref       1        1        0   249999998          0     0  50000
                       pl0_ref_mux        1        1        0  1499999985          0     0  50000
                          pl0_ref_div1       1        1        0    99999999          0     0  50000
                             pl0_ref_div2       1        1        0    99999999          0     0  50000
                                pl0_ref      10       10        0    99999999          0     0  50000
                       ams_ref_mux        1        1        1  1499999985          0     0  50000
                          ams_ref_div1       1        1        1    50000000          0     0  50000
                             ams_ref_div2       1        1        1    50000000          0     0  50000
                                ams_ref       1        1        1    50000000          0     0  50000
                       can1_ref_mux       0        0        0  1499999985          0     0  50000
                          can1_ref_div1       0        0        0    46875000          0     0  50000
                             can1_ref_div2       0        0        0    46875000          0     0  50000
                                can1_ref       0        0        0    46875000          0     0  50000
                                   can1       0        0        0    46875000          0     0  50000
                       can0_ref_mux       0        0        0  1499999985          0     0  50000
                          can0_ref_div1       0        0        0    46875000          0     0  50000
                             can0_ref_div2       0        0        0    46875000          0     0  50000
                                can0_ref       0        0        0    46875000          0     0  50000
                                   can0       0        0        0    46875000          0     0  50000
                       i2c1_ref_mux       0        1        1  1499999985          0     0  50000
                          i2c1_ref_div1       0        1        1    99999999          0     0  50000
                             i2c1_ref_div2       0        1        1    99999999          0     0  50000
                                i2c1_ref       0        1        1    99999999          0     0  50000
                       i2c0_ref_mux       0        0        0  1499999985          0     0  50000
                          i2c0_ref_div1       0        0        0   299999997          0     0  50000
                             i2c0_ref_div2       0        0        0   299999997          0     0  50000
                                i2c0_ref       0        0        0   299999997          0     0  50000
                       nand_ref_mux       0        0        0  1499999985          0     0  50000
                          nand_ref_div1       0        0        0    46875000          0     0  50000
                             nand_ref_div2       0        0        0     9375000          0     0  50000
                                nand_ref       0        0        0     9375000          0     0  50000
                       spi1_ref_mux       0        0        0  1499999985          0     0  50000
                          spi1_ref_div1       0        0        0    62500000          0     0  50000
                             spi1_ref_div2       0        0        0    62500000          0     0  50000
                                spi1_ref       0        0        0    62500000          0     0  50000
                       uart1_ref_mux       0        0        0  1499999985          0     0  50000
                          uart1_ref_div1       0        0        0    99999999          0     0  50000
                             uart1_ref_div2       0        0        0    99999999          0     0  50000
                                uart1_ref       0        0        0    99999999          0     0  50000
                       uart0_ref_mux       1        1        1  1499999985          0     0  50000
                          uart0_ref_div1       1        1        1    99999999          0     0  50000
                             uart0_ref_div2       1        1        1    99999999          0     0  50000
                                uart0_ref       1        1        1    99999999          0     0  50000
                       sdio1_ref_mux       1        1        1  1499999985          0     0  50000
                          sdio1_ref_div1       1        1        1   299999997          0     0  50000
                             sdio1_ref_div2       1        1        1   149999999          0     0  50000
                                sdio1_ref       1        1        1   149999999          0     0  50000
                       sdio0_ref_mux       0        0        0  1499999985          0     0  50000
                          sdio0_ref_div1       0        0        0    99999999          0     0  50000
                             sdio0_ref_div2       0        0        0    99999999          0     0  50000
                                sdio0_ref       0        0        0    99999999          0     0  50000
                       qspi_ref_mux       0        0        0  1499999985          0     0  50000
                          qspi_ref_div1       0        0        0   187499999          0     0  50000
                             qspi_ref_div2       0        0        0   187499999          0     0  50000
                                qspi_ref       0        0        0   187499999          0     0  50000
                       gem_tsu_ref_mux       1        1        1  1499999985          0     0  50000
                          gem_tsu_ref_div1       1        1        1   249999998          0     0  50000
                             gem_tsu_ref_div2       1        1        1   249999998          0     0  50000
                                gem_tsu_ref       1        1        1   249999998          0     0  50000
                                   gem_tsu       1        1        0   249999998          0     0  50000
                       usb3_dual_ref_mux       0        0        0  1499999985          0     0  50000
                          usb3_dual_ref_div1       0        0        0    46875000          0     0  50000
                             usb3_dual_ref_div2       0        0        0     9375000          0     0  50000
                                usb3_dual_ref       0        0        0     9375000          0     0  50000
                       usb1_bus_ref_mux       0        0        0  1499999985          0     0  50000
                          usb1_bus_ref_div1       0        0        0   124999999          0     0  50000
                             usb1_bus_ref_div2       0        0        0   124999999          0     0  50000
                                usb1_bus_ref       0        0        0   124999999          0     0  50000
                       usb0_bus_ref_mux       0        0        0  1499999985          0     0  50000
                          usb0_bus_ref_div1       0        0        0   124999999          0     0  50000
                             usb0_bus_ref_div2       0        0        0   124999999          0     0  50000
                                usb0_bus_ref       0        0        0   124999999          0     0  50000
                       lpd_lsbus_mux       1        1        0  1499999985          0     0  50000
                          lpd_lsbus_div1       1        1        0    99999999          0     0  50000
                             lpd_lsbus       7        7        0    99999999          0     0  50000
                                lpd_wdt       0        0        0    99999999          0     0  50000
                       iopll_to_fpd       1        1        0   749999993          0     0  50000
                          topsw_lsbus_mux       1        1        0   749999993          0     0  50000
                             topsw_lsbus_div1       1        1        0    93750000          0     0  50000
                                topsw_lsbus       3        3        0    93750000          0     0  50000
                                   fpd_wdt       1        1        0    93750000          0     0  50000
                          gpu_ref_mux       0        0        0   749999993          0     0  50000
                             gpu_ref_div1       0        0        0   374999997          0     0  50000
                                gpu_ref       0        0        0   374999997          0     0  50000
                                   gpu_pp1_ref       0        0        0   374999997          0     0  50000
                                   gpu_pp0_ref       0        0        0   374999997          0     0  50000
     misc_clk_2                           2        2        0    33333333          0     0  50000
        vcu_pll                           1        1        0  2667999749          0     0  50000
           vcu_pll_half                   4        4        0  1333999874          0     0  50000
              mcu_core_dec_clk_mux        1        1        0  1333999874          0     0  50000
                 mcu_core_dec_clk_div       1        1        0   444666625          0     0  50000
                    mcu_core_dec_clk       1        1        0   444666625          0     0  50000
              mcu_core_enc_clk_mux        1        1        0  1333999874          0     0  50000
                 mcu_core_enc_clk_div       1        1        0   444666625          0     0  50000
                    mcu_core_enc_clk       1        1        0   444666625          0     0  50000
              vcu_core_dec_clk_mux        1        1        0  1333999874          0     0  50000
                 vcu_core_dec_clk_div       1        1        0   666999937          0     0  50000
                    vcu_core_dec_clk       1        1        0   666999937          0     0  50000
              vcu_core_enc_clk_mux        1        1        0  1333999874          0     0  50000
                 vcu_core_enc_clk_div       1        1        0   666999937          0     0  50000
                    vcu_core_enc_clk       1        1        0   666999937          0     0  50000
     misc_clk_1                           0        0        0   250000000          0     0  50000
     can1_mio                             0        0        0           0          0     0  50000
     can0_mio                             0        0        0           0          0     0  50000
     gem3_rx                              0        0        0           0          0     0  50000
     gem2_rx                              1        1        0           0          0     0  50000
     gem1_rx                              0        0        0           0          0     0  50000
     gem0_rx                              0        0        0           0          0     0  50000
    root@ilgar:~# 
    
    

  • 0
    •  Analog Employees 
    on Apr 28, 2021 4:55 AM in reply to serkancan

    Moved to Linux forum since this seems to be related to a Linux issue if it works on No-Os. 

    Laszlo

  • 0
    •  Analog Employees 
    on Apr 28, 2021 5:57 AM in reply to serkancan

    [ 8.813431] axi_adxcvr 84a80000.axi-adxcvr-tx: QPLL TX Error: 0

    This indicates that the QPLL is not locking. Can you share your devicetree?

    -Michael