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iio_readdev: timeout when trying to refill ADC buffer

Hi,

When I try to use the ADC buffer using iio_readdev, I got the following output:

iio_readdev -u local: -b 256 -s 1024 cf-ad9361-lpc
unable to refill buffer: Connection timed out

The timeout happens within the device_check_ready function, during the polling.

Any hint about how to debug this? Before that I also enabled the buffer to be sure, with "echo 1 > buffer/enable", but it doesn't change the result.

Here is my device-tree:

rx_dma: dma@XXX84000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xXXX84000 0x1000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			clocks = <&misc_clk_2>;
			interrupt-parent = <&ad9361_if_ic_0>;
			interrupts = <6 2>;

			adi,channels {
				#size-cells = <0>;
				#address-cells = <1>;

				dma-channel@0 {
					reg = <0>;
					adi,source-bus-width = <64>;
					adi,source-bus-type = <1>;
					adi,destination-bus-width = <64>;
					adi,destination-bus-type = <0>;
				};
			};
		};

		tx_dma: dma@XXX87000  {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0xXXX87000 0x1000>;
			#dma-cells = <1>;
			#clock-cells = <0>;
			clocks = <&misc_clk_2>;
			interrupt-parent = <&ad9361_if_ic_0>;
			interrupts = <9 2>;

			adi,channels {
				#size-cells = <0>;
				#address-cells = <1>;

				dma-channel@0 {
					reg = <0>;
					adi,source-bus-width = <64>;
					adi,source-bus-type = <0>;
					adi,destination-bus-width = <64>;
					adi,destination-bus-type = <1>;
				};
			};
		};

		cf_ad9361_adc_core_0: cf-ad9361-lpc@XXX90000 {
			compatible = "adi,axi-ad9361-6.00.a";
			reg = <0xXXX90000 0x6000>;
			dmas = <&rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&adc0_ad9361>;
		};

		cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@XXX94000 {
			compatible = "adi,axi-ad9361-dds-6.00.a";
			reg = <0xXXX94000 0x1000>;
			clocks = <&adc0_ad9361 13>;
			clock-names = "sampl_clk";
			dmas = <&tx_dma 0>;
			dma-names = "tx";
			adi,axi-dds-1-rf-channel-default-scale = <0>;
			adi,axi-dds-1-rf-channel;
		};

Thanks.



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[edited by: Neutrinoxy at 11:55 AM (GMT -5) on 9 Mar 2021]
  • Hi,

    I would verify the interrupt numbers. By the way, what FPGA carrier do you use?

    Thanks,
    Dragos

  • Hi ,

    We are using a custom board that is very similar to the zcu102. I double checked the interrupt numbers but it seems fine. When I look at the interrupts avec an iio_readdev, I see the following:

    cat /proc/interrupts
               CPU0       CPU1       CPU2       CPU3
      5:      10173       6709       7139       6687     GICv2  30 Level     arch_timer
      9:       4563          0          0          0  interrupt-controller@XXX80000   0 Edge    -edge      XXXc0000.axi_quad_spi
     10:          0          0          0          0  interrupt-controller@XXX80000   1 Edge    -edge      XXXd0000.axi_quad_spi
     11:          0          0          0          0  interrupt-controller@XXX80000   2 Edge    -edge      XXXe0000.axi_quad_spi
     14:          0          0          0          0     GICv2  67 Level     zynqmp_ipi
     15:          0          0          0          0     GICv2 175 Level     arm-pmu
     16:          0          0          0          0     GICv2 176 Level     arm-pmu
     17:          0          0          0          0     GICv2 177 Level     arm-pmu
     18:          0          0          0          0     GICv2 178 Level     arm-pmu
     19:          1          0          0          0     GICv2 144 Level     fd070000.memory-controller
     21:          0          0          0          0     GICv2  42 Level     ff960000.memory-controller
     22:          0          0          0          0     GICv2  57 Level     axi-pmon, axi-pmon
     23:          0          0          0          0     GICv2 155 Level     axi-pmon, axi-pmon
     24:        214          0          0          0     GICv2  53 Level     xuartps
     25:          1          0          0          0  interrupt-controller@XXX80000   6 Edge    -edge      XXX84000.dma
     26:          0          0          0          0  interrupt-controller@XXX80000   9 Edge    -edge      XXX87000.dma
    IPI0:      1485       3629       5235       1294       Rescheduling interrupts
    IPI1:       166        165        166         14       Function call interrupts
    IPI2:         0          0          0          0       CPU stop interrupts
    IPI3:         0          0          0          0       CPU stop (for crash dump) interrupts
    IPI4:         0          0          0          0       Timer broadcast interrupts
    IPI5:         0          0          0          0       IRQ work interrupts
    IPI6:         0          0          0          0       CPU wake-up interrupts
    Err:          0
    root@xilinx-zcu102-2019_2:~#

    The interrupt 25 corresponds to the RX dma (pin number 6 of the interrupt controller). The counter is incremented each time I execute the command.

    Do you think it still can be an issue with interrupts? Also, I don't know if it's relevant, but we have another interrupt controller between this one and the PS. So the path is : DMA -> Interrupt Controller -> Interrupt Controller -> Zynq PS (PL-PS IRQ).

    Thanks.

  • For me, the IRQ numbers specified in the devicetree look wrong.

    According to the Zynq UltraScale+ Device Technical Reference Manual:
     - for PL_PS_Group0 (PL to PS interrupt signals 0 to 7), IRQ Number (GIC) is 121:128;
     - for PL_PS_Group1 (PL to PS interrupt signals 8 to 15), IRQ Number (GIC) is 136:143.

    Normally, to obtain the value that should be specified in the devicetree, you should subtract 32 from the IRQ Number specified in the device technical reference manual.

    Can you verify again your devicetree?

    Thanks,
    Dragos