I am trying to set the sampling frequency to 300MSPS on fmcdaq2 using linux 2019_R1(vivado 2018.3) image by changing the clock settings (channel dividers) from adi-daq2.dtsi
then build the kernel. I did the following steps :
- set adi,pll2-m1-freq = <600000000>; which means out master clock is 5.
- change ADC and DAC clock channel dividers :
- "DAC_CLK_FMC" = 4.
- "DAC_CLK" = 2.
- "ADC_CLK_FMC" = 4.
- "ADC_CLK" = 2.
- enable cpll in axi_ad9144_adxcvr by adding adi,use-cpll-enable;
- set adi,sys-clk-select = <0> in axi_ad9144_adxcvr.
the settings did not work . ad9680 sp0 and ad9144 sp0 are out of range also I did the same settings before on no-OS software after emoving the FIFO and it worked do you have any advice.
settings the sampling frequency in no-OS to 300MSPS are disscussed here :