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digital tuning failing on one of 4 AD9361 chips

Hello,

    I am running into a problem with my digital RX tuning failing.  I have 4 chips on my board and 3 out of the 4 pass, but one is failing.  I checked the obvious stuff like making sure that my signal names P/Ns are correct on the schematic and I checked the constraints and that everything is hooked up in Vivado and everything looks correct.  I have attached the trace length difference.  The only thing I can think of at this point is that maybe a solder joint is bad?  I turned on the verbose and veryVerbose options from: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation?s.  I understand if you run the BIST timing analysis once it has registered you get a 15 x 15 grid showing data delay vs clock.  But, I don't understand when the driver initialize what the "0" and "1" rows mean on:

0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:o o o o o o o o o # # # # o o o 
1:o o o o o o o o o o o # # # # o 

Why only two rows?

Do the adi,rx-data-clock-delay = <0>; and adi,rx-data-delay = <9>; have any effect in the device tree if the adi,digital-interface-tune-skip-mode is not set to anything?


When I try to run the bist_timing_analysis later on the device that fails I get a kernel panic. On the other 3 devices I have no problem.

Good device on boot:

    3.404172] ad9361 spi1.0: ad9361_probe : enter (ad9361)
[    3.552550] ad9361 spi1.0: ad9361_probe : AD936x Rev 2 successfully initialized
[    3.715448] SAMPL CLK: 25000000 tuning: RX
[    3.719553]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    3.724058] 0:# # # o o o o o o o o o o o o o
[    3.728560] 1:# o o o o o o o o o o o o o o o
[    3.865632] SAMPL CLK: 40000000 tuning: RX
[    3.869734]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    3.874236] 0:# # # o o o o o o o o o o # # #
[    3.878733] 1:# o o o o o o o o o o o # # # #
[    4.018005] SAMPL CLK: 61440000 tuning: RX
[    4.022112]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.026614] 0:# # # o o o o o # # # # # # # #
[    4.031110] 1:# # o o o o o # # # # o # # # #
[    4.035652] SAMPL CLK: 61440000 tuning: RX
[    4.039756]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.044271] 0:# # # o o O o o # # # # # # # #
[    4.048775] 1:# # o o o o o # # # # o # # # #
[    4.188450] SAMPL CLK: 25000000 tuning: TX
[    4.192552]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.197054] 0:# # # # # # # # # # # # # # # #
[    4.201550] 1:# # o o o o o o o o o o o o o o
[    4.338602] SAMPL CLK: 40000000 tuning: TX
[    4.342706]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.347210] 0:# # # # # # # # # # # # # # # #
[    4.351705] 1:# # o o o o o o o o o # # # # #
[    4.491010] SAMPL CLK: 61440000 tuning: TX
[    4.495110]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.499613] 0:# # # # # # # # # # # # # # # #
[    4.504109] 1:# # o o o o # # # # # # # # # #
[    4.508647] SAMPL CLK: 61440000 tuning: TX
[    4.512747]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.517251] 0:# # # # # # # # # # # # # # # #
[    4.521747] 1:# # o o O o # # # # # # # # # #
[    4.530774] cf_axi_adc 99020000.axi_ad9361: ADI AIM (10.00.b) at 0x99020000 mapped to 0xffffff800c0c0000, probed ADC AD9361 as MASTER

Good device after boot with bist_timing_analysis:

root@prfi:/sys/kernel/debug/iio/iio:device2# echo 1 > bist_timing_analysis
root@prfi:/sys/kernel/debug/iio/iio:device2# cat bist_timing_analysis
CLK: 60000000 Hz 'o' = PASS
DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:. . o o o o o . . . . o o o o o 
1:. . . o o o o o . . . . . o o o 
2:. . . . o o o o o . . . . o o o 
3:o . . . . o o o o o . . . . o o 
4:o . . . . . o o o o o . . . . . 
5:o o o . . . . o o o o o . . . . 
6:o o o . . . . . o o o o o . . . 
7:o o o o . . . . . o o o o o . . 
8:. o o o o . . . . . o o o o o . 
9:. . o o o o . . . . . o o o o o 
a:. . . o o o o . . . . . o o o o 
b:. . . . o o o o . . . . . o o o 
c:. . . . . o o o o . . . . . o o 
d:o . . . . . o o o o . . . . . o 
e:o o . . . . . o o o o . . . . . 
f:o o o . . . . . o o o o . . . . 

Bad device:

[  626.800716] ad9361 spi1.2: ad9361_probe : enter (ad9361)
[  626.807147] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
[  626.954828] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
[  627.117251] SAMPL CLK: 25000000 tuning: RX
[  627.121357]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.125874] 0:# # # # # # # # # # # # # # # #
[  627.130371] 1:# # # # # # # # # # # # # # # #
[  627.267119] SAMPL CLK: 40000000 tuning: RX
[  627.271222]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.275739] 0:# # # # # # # # # # # # # # # #
[  627.280240] 1:# # # # # # # # # # # # # # # #
[  627.418921] SAMPL CLK: 61440000 tuning: RX
[  627.423026]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.427531] 0:# # # # # # # # # # # # # # # #
[  627.432034] 1:# # # # # # # # # # # # # # # #
[  627.436567] SAMPL CLK: 61440000 tuning: RX
[  627.440673]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.445177] 0:# # # # # # # # # # # # # # # #
[  627.449681] 1:# # # # # # # # # # # # # # # #
[  627.454195] ad9361 spi1.2: ad9361_dig_tune_delay: Tuning RX FAILED!
[  627.460997] cf_axi_adc: probe of 99060000.axi_ad9361 failed with error -5

Here are my questions:  

1.  Is there a way to tell if a particular bit isn't coming across correctly?

2.  Is there any additional debug I can turn on?

3.  How can I debug this?

4.  In Vivado I just enabled: set_property IOB TRUE [get_ports {*}], I am not sure if this will make a difference, but I am about to try.  

Hyperlynx Timing attached below:

Parents
  • An update:  

    I set the adi,digital-interface-tune-skip-mode = 2 to skip.  Then, I manually ran the bist and it passes.  One other thing that I noticed is that it says, "Master".  How is this "Master" set??  Device tree?  What does it mean.  

    root@prfi:~# echo spi1.2 > /sys/bus/spi/drivers/ad9361/bind
    [ 32.623857] ad9361 spi1.2: ad9361_probe : enter (ad9361)
    [ 32.630318] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
    [ 32.787042] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
    root@prfi:~# [ 32.818007] cf_axi_adc 99060000.axi_ad9361: ADI AIM (10.00.b) at 0x99060000 mapped to 0xffffff800c740000, probed ADC AD9361 as MASTER

    lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device4 -> ../../../devices/platform/amba/ff040000.spi/spi_master/spi1/spi1.2/iio:device4
    lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device5 -> ../../../devices/platform/amba_pl@0/99060000.axi_ad9361/iio:device5
    lrwxrwxrwx 1 root root 0 Jan 30 16:14 iio_sysfs_trigger -> ../../../devices/iio_sysfs_trigger
    root@prfi:/sys/bus/iio/devices# cd /sys/kernel/debug/iio/iio:device4
    root@prfi:/sys/kernel/debug/iio/iio:device4# ls b*
    bist_prbs bist_timing_analysis bist_tone
    root@prfi:/sys/kernel/debug/iio/iio:device4# echo 1 > bist_timing_analysis
    root@prfi:/sys/kernel/debug/iio/iio:device4# cat bist_timing_analysis
    CLK: 60000000 Hz 'o' = PASS
    DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    0:. . . o . . . . . . . . o o o .
    1:. . . . . . . o . . . . . o o o
    2:. . . . o . . o o . . . . . o o
    3:. . . . . . . o o . . . . . . o
    4:o . . . . . . o o o o . . . . .
    5:o o . . . . . o o o o . . . . .
    6:o o o . . . . . o o o o . . . .
    7:o o o o . . . . . o o o o . . .
    8:. o o o . . . . . . o o o o . .
    9:. . o o . . . . . . . o o o o .
    a:. . . o . . . . . . . . o o o o
    b:. . . . o . . o . . . . . o o o
    c:. . . . . . . o o . . . . . o o
    d:. . . . . . . o o o . . . . . o
    e:o . . . . . . o o o o . . . . .
    f:o o . . . . . . o o o o . . . .

    Should I just set the clk delay to 6 and the data delay to 5 in the device tree?

    adi,rx-data-clock-delay = <6>;
    adi,rx-data-delay = <5>;

  • Sorry, hard to see with a non-monospaced font.  I would set the data-clock-delay =<9> and the rx-data-delay = <5>

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