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The AD9361 is a high performance, highly integrated radio frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and 4G base station applications....
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digital tuning failing on one of 4 AD9361 chips



		

			

									
					    astone21480
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jan 29, 2021 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello,
    

        I am running into a problem with my digital RX tuning failing.  I have 4 chips on my board and 3 out of the 4 pass, but one is failing.  I checked the obvious stuff like making sure that my signal names P/Ns are correct on the schematic and I checked the constraints and that everything is hooked up in Vivado and everything looks correct.  I have attached the trace length difference.  The only thing I can think of at this point is that maybe a solder joint is bad?  I turned on the verbose and veryVerbose options from: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/interface_timing_validation?s.  I understand if you run the BIST timing analysis once it has registered you get a 15 x 15 grid showing data delay vs clock.  But, I don't understand when the driver initialize what the "0" and "1" rows mean on:
    

    0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:o o o o o o o o o # # # # o o o 
1:o o o o o o o o o o o # # # # o 

    Why only two rows?  

    Do the adi,rx-data-clock-delay = <0>; and adi,rx-data-delay = <9>; have any effect in the device tree if the adi,digital-interface-tune-skip-mode is not set to anything?


    When I try to run the bist_timing_analysis later on the device that fails I get a kernel panic.  On the other 3 devices I have no problem.  

    Good device on boot:

        3.404172] ad9361 spi1.0: ad9361_probe : enter (ad9361)
[    3.552550] ad9361 spi1.0: ad9361_probe : AD936x Rev 2 successfully initialized
[    3.715448] SAMPL CLK: 25000000 tuning: RX
[    3.719553]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    3.724058] 0:# # # o o o o o o o o o o o o o
[    3.728560] 1:# o o o o o o o o o o o o o o o
[    3.865632] SAMPL CLK: 40000000 tuning: RX
[    3.869734]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    3.874236] 0:# # # o o o o o o o o o o # # #
[    3.878733] 1:# o o o o o o o o o o o # # # #
[    4.018005] SAMPL CLK: 61440000 tuning: RX
[    4.022112]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.026614] 0:# # # o o o o o # # # # # # # #
[    4.031110] 1:# # o o o o o # # # # o # # # #
[    4.035652] SAMPL CLK: 61440000 tuning: RX
[    4.039756]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.044271] 0:# # # o o O o o # # # # # # # #
[    4.048775] 1:# # o o o o o # # # # o # # # #
[    4.188450] SAMPL CLK: 25000000 tuning: TX
[    4.192552]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.197054] 0:# # # # # # # # # # # # # # # #
[    4.201550] 1:# # o o o o o o o o o o o o o o
[    4.338602] SAMPL CLK: 40000000 tuning: TX
[    4.342706]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.347210] 0:# # # # # # # # # # # # # # # #
[    4.351705] 1:# # o o o o o o o o o # # # # #
[    4.491010] SAMPL CLK: 61440000 tuning: TX
[    4.495110]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.499613] 0:# # # # # # # # # # # # # # # #
[    4.504109] 1:# # o o o o # # # # # # # # # #
[    4.508647] SAMPL CLK: 61440000 tuning: TX
[    4.512747]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[    4.517251] 0:# # # # # # # # # # # # # # # #
[    4.521747] 1:# # o o O o # # # # # # # # # #
[    4.530774] cf_axi_adc 99020000.axi_ad9361: ADI AIM (10.00.b) at 0x99020000 mapped to 0xffffff800c0c0000, probed ADC AD9361 as MASTER

    

    

    Good device after boot with bist_timing_analysis:
    

    root@prfi:/sys/kernel/debug/iio/iio:device2# echo 1 > bist_timing_analysis
root@prfi:/sys/kernel/debug/iio/iio:device2# cat bist_timing_analysis
CLK: 60000000 Hz 'o' = PASS
DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:. . o o o o o . . . . o o o o o 
1:. . . o o o o o . . . . . o o o 
2:. . . . o o o o o . . . . o o o 
3:o . . . . o o o o o . . . . o o 
4:o . . . . . o o o o o . . . . . 
5:o o o . . . . o o o o o . . . . 
6:o o o . . . . . o o o o o . . . 
7:o o o o . . . . . o o o o o . . 
8:. o o o o . . . . . o o o o o . 
9:. . o o o o . . . . . o o o o o 
a:. . . o o o o . . . . . o o o o 
b:. . . . o o o o . . . . . o o o 
c:. . . . . o o o o . . . . . o o 
d:o . . . . . o o o o . . . . . o 
e:o o . . . . . o o o o . . . . . 
f:o o o . . . . . o o o o . . . . 

    

    

    Bad device:
    

    [  626.800716] ad9361 spi1.2: ad9361_probe : enter (ad9361)
[  626.807147] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
[  626.954828] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
[  627.117251] SAMPL CLK: 25000000 tuning: RX
[  627.121357]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.125874] 0:# # # # # # # # # # # # # # # #
[  627.130371] 1:# # # # # # # # # # # # # # # #
[  627.267119] SAMPL CLK: 40000000 tuning: RX
[  627.271222]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.275739] 0:# # # # # # # # # # # # # # # #
[  627.280240] 1:# # # # # # # # # # # # # # # #
[  627.418921] SAMPL CLK: 61440000 tuning: RX
[  627.423026]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.427531] 0:# # # # # # # # # # # # # # # #
[  627.432034] 1:# # # # # # # # # # # # # # # #
[  627.436567] SAMPL CLK: 61440000 tuning: RX
[  627.440673]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[  627.445177] 0:# # # # # # # # # # # # # # # #
[  627.449681] 1:# # # # # # # # # # # # # # # #
[  627.454195] ad9361 spi1.2: ad9361_dig_tune_delay: Tuning RX FAILED!
[  627.460997] cf_axi_adc: probe of 99060000.axi_ad9361 failed with error -5

    

    Here are my questions:  
    

    1.  Is there a way to tell if a particular bit isn't coming across correctly?
    

    2.  Is there any additional debug I can turn on?
    

    3.  How can I debug this?
    

    4.  In Vivado I just enabled: set_property IOB TRUE [get_ports {*}], I am not sure if this will make a difference, but I am about to try.  
    

    Hyperlynx Timing attached below:
    

     
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 hennerich
                
                                                    
                 ad9361
                
                                                    
                 Wideband Transceiver IC
                
                                                    
                 RF Integrated Transceivers
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    


	















    
	
    
	
    
					



			








	
	
	
	



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        An update:  
        

        I set the adi,digital-interface-tune-skip-mode = 2 to skip.  Then, I manually ran the bist and it passes.  One other thing that I noticed is that it says, "Master".  How is this "Master" set??  Device tree?  What does it mean.  
        

        root@prfi:~# echo spi1.2 > /sys/bus/spi/drivers/ad9361/bind
        [ 32.623857] ad9361 spi1.2: ad9361_probe : enter (ad9361)
        [ 32.630318] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
        [ 32.787042] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
        root@prfi:~# [ 32.818007] cf_axi_adc 99060000.axi_ad9361: ADI AIM (10.00.b) at 0x99060000 mapped to 0xffffff800c740000, probed ADC AD9361 as MASTER
        

        

        lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device4 -> ../../../devices/platform/amba/ff040000.spi/spi_master/spi1/spi1.2/iio:device4
        lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device5 -> ../../../devices/platform/amba_pl@0/99060000.axi_ad9361/iio:device5
        lrwxrwxrwx 1 root root 0 Jan 30 16:14 iio_sysfs_trigger -> ../../../devices/iio_sysfs_trigger
        root@prfi:/sys/bus/iio/devices# cd /sys/kernel/debug/iio/iio:device4
        root@prfi:/sys/kernel/debug/iio/iio:device4# ls b*
        bist_prbs bist_timing_analysis bist_tone
        root@prfi:/sys/kernel/debug/iio/iio:device4# echo 1 > bist_timing_analysis
        root@prfi:/sys/kernel/debug/iio/iio:device4# cat bist_timing_analysis
        CLK: 60000000 Hz 'o' = PASS
        DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
        0:. . . o . . . . . . . . o o o . 
        1:. . . . . . . o . . . . . o o o 
        2:. . . . o . . o o . . . . . o o 
        3:. . . . . . . o o . . . . . . o 
        4:o . . . . . . o o o o . . . . . 
        5:o o . . . . . o o o o . . . . . 
        6:o o o . . . . . o o o o . . . . 
        7:o o o o . . . . . o o o o . . . 
        8:. o o o . . . . . . o o o o . . 
        9:. . o o . . . . . . . o o o o . 
        a:. . . o . . . . . . . . o o o o 
        b:. . . . o . . o . . . . . o o o 
        c:. . . . . . . o o . . . . . o o 
        d:. . . . . . . o o o . . . . . o 
        e:o . . . . . . o o o o . . . . . 
        f:o o . . . . . . o o o o . . . . 
        

        Should I just set the clk delay to 6 and the data delay to 5 in the device tree?
        

        adi,rx-data-clock-delay = <6>;
         adi,rx-data-delay = <5>;
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

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          An update:  
          

          I set the adi,digital-interface-tune-skip-mode = 2 to skip.  Then, I manually ran the bist and it passes.  One other thing that I noticed is that it says, "Master".  How is this "Master" set??  Device tree?  What does it mean.  
          

          root@prfi:~# echo spi1.2 > /sys/bus/spi/drivers/ad9361/bind
          [ 32.623857] ad9361 spi1.2: ad9361_probe : enter (ad9361)
          [ 32.630318] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
          [ 32.787042] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
          root@prfi:~# [ 32.818007] cf_axi_adc 99060000.axi_ad9361: ADI AIM (10.00.b) at 0x99060000 mapped to 0xffffff800c740000, probed ADC AD9361 as MASTER
          

          

          lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device4 -> ../../../devices/platform/amba/ff040000.spi/spi_master/spi1/spi1.2/iio:device4
          lrwxrwxrwx 1 root root 0 Jan 30 16:15 iio:device5 -> ../../../devices/platform/amba_pl@0/99060000.axi_ad9361/iio:device5
          lrwxrwxrwx 1 root root 0 Jan 30 16:14 iio_sysfs_trigger -> ../../../devices/iio_sysfs_trigger
          root@prfi:/sys/bus/iio/devices# cd /sys/kernel/debug/iio/iio:device4
          root@prfi:/sys/kernel/debug/iio/iio:device4# ls b*
          bist_prbs bist_timing_analysis bist_tone
          root@prfi:/sys/kernel/debug/iio/iio:device4# echo 1 > bist_timing_analysis
          root@prfi:/sys/kernel/debug/iio/iio:device4# cat bist_timing_analysis
          CLK: 60000000 Hz 'o' = PASS
          DC0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
          0:. . . o . . . . . . . . o o o . 
          1:. . . . . . . o . . . . . o o o 
          2:. . . . o . . o o . . . . . o o 
          3:. . . . . . . o o . . . . . . o 
          4:o . . . . . . o o o o . . . . . 
          5:o o . . . . . o o o o . . . . . 
          6:o o o . . . . . o o o o . . . . 
          7:o o o o . . . . . o o o o . . . 
          8:. o o o . . . . . . o o o o . . 
          9:. . o o . . . . . . . o o o o . 
          a:. . . o . . . . . . . . o o o o 
          b:. . . . o . . o . . . . . o o o 
          c:. . . . . . . o o . . . . . o o 
          d:. . . . . . . o o o . . . . . o 
          e:o . . . . . . o o o o . . . . . 
          f:o o . . . . . . o o o o . . . . 
          

          Should I just set the clk delay to 6 and the data delay to 5 in the device tree?
          

          adi,rx-data-clock-delay = <6>;
           adi,rx-data-delay = <5>;
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
						
				
						
				
				
		
		
          
			
		
          
	
          

          

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						in reply to astone21480
					
									
            
	
            

		
		
            
					
            Sorry, hard to see with a non-monospaced font.  I would set the data-clock-delay =<9> and the rx-data-delay = <5>
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

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						in reply to astone21480
					
									
              
	
              

		
		
              
					
              The more I read...I am wondering if I am having this problem due to device tree settings and mcs_sync.  Is there a way to have 1 master and 3 slaves?  In Vivado I have wired the I_clk to the input clk of each AD9361 device.  In the device tree I only see the slavecore-reg option, but I cannot have more than 1 slavecore-reg.  Can you tell me how to identify devices as a "SLAVE"?
              

              I was looking at the code here: https://github.com/analogdevicesinc/libad9361-iio/blob/master/ad9361_multichip_sync.c and this post: https://ez.analog.com/linux-software-drivers/f/q-a/99191/ad9361-digital-tune-on-slave-device
              

              and it looks like I might need to modify this code for 4 devices and then ad9361_fmcomms5_multichip_sync with the 4 devices specified.  
              

              Any help/advice?  Any ideas on things to modify in device tree.  Device tree listed below:
              

              / {
	clocks {
		ad9361_clkin: clock@0 {
			#clock-cells = <0>;
			compatible = "adjustable-clock";
			clock-frequency = <80000000>;
			clock-accuracy = <200000>; /* 200 ppm (ppb) */
			clock-output-names = "ad9361_ext_refclk";
		};
	};
};

&spi0 {
    /* ad9361_0_L1Ant0_L1Ant1*/
	adc0_ad9361: ad9361-phy@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <0>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;


		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1570420000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};

	/* ad9361_1_L1Ant2 */
	adc1_ad9361: ad9361-phy-B@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <1>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;


		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1570420000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};

	/* ad9361_2_L2Ant0_L2Ant1 */
	adc2_ad9361: ad9361-phy-C@2 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <2>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,digital-interface-tune-skip-mode = <2>;
		adi,rx-data-clock-delay = <9>;
		adi,rx-data-delay = <5>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;

		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1222600000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};
};

&spi1 {
	/* ad9361_3_L2Ant2 */
	adc3_ad9361: ad9361-phy-D@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <0>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;

		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1222600000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};
};
              

              

              /include/ "system-conf.dtsi"
/ {
    /* reducing memory available by 0xA000 * 2 = 0x14000 */
    memory {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x3FEEC000>;
    };

    pod_dma_ctr: pod-dma-ctr@0 {
               compatible = "pod,prfi_dma";
                dmas = <&axi_dmac_0 0>;
               dma-names = "prfi_dma";
    }; 

    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/leds/common.h>

    leds {
        compatible = "gpio-leds";
        fp1_led {
            label = "fp1_led";
            gpios = <&gpio 99 GPIO_ACTIVE_LOW>;
            linux,default-trigger = "heartbeat";
        };
        fp2_led {
            label = "fp2_led";
            gpios = <&gpio 100 GPIO_ACTIVE_LOW>;
            linux,default-trigger = "heartbeat";
        };
        fp3_led {
            label = "fp2_led";
            gpios = <&gpio 101 GPIO_ACTIVE_LOW>;
            linux,default-trigger = "heartbeat";
        };
        fp4_led {
            label = "fp4_led";
            gpios = <&gpio 102 GPIO_ACTIVE_LOW>;
            linux,default-trigger = "heartbeat";
        };
        BUF245_led1 {
            label = "BUF245_led1";
            gpios = <&gpio 103 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led2 {
            label = "BUF245_led2";
            gpios = <&gpio 104 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led3 {
            label = "BUF245_led3";
            gpios = <&gpio 105 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led4 {
            label = "BUF245_led4";
            gpios = <&gpio 106 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led5 {
            label = "BUF245_led5";
            gpios = <&gpio 107 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led6 {
            label = "BUF245_led6";
            gpios = <&gpio 108 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led7 {
            label = "BUF245_led7";
            gpios = <&gpio 109 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
        BUF245_led8 {
            label = "BUF245_led8";
            gpios = <&gpio 110 GPIO_ACTIVE_HIGH>;
            linux,default-state = "on";
        };
    };

    chosen {
    bootargs = "earlycon clk_ignore_unused cpuidle.off=1";
    };


    /* these are each of the AD9361 IP blocks in Vivado DAC*/

    /*cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@99024000 {*/
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99024000 0x0 0x1000>;             */
    /*        clocks = <&adc0_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        dmas = <&axi_ad9361_dac_dma 0>;                */
    /*        dma-names = "tx";                              */
    /*        slavecore-reg = <0x99044000 0x1000>;           */
    /*    };                                                 */
    /*cf_ad9361_dac_core_1: cf-ad9361-dds-core-B@99044000 {  */
    /*        compatible = "adi,axi-ad9361x2-dds-6.00.a";    */
    /*        reg = <0x0 0x99044000 0x0 0x1000>;             */
    /*        clocks = <&adc1_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */
    /*cf_ad9361_dac_core_2: cf-ad9361-dds-core-C@99064000 {  */
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99064000 0x0 0x1000>;             */
    /*        clocks = <&adc2_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */
    /*cf_ad9361_dac_core_3: cf-ad9361-dds-core-D@99084000 {  */
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99084000 0x0 0x1000>;             */
    /*        clocks = <&adc3_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */

};     
&tsu_ext_clk {
    clock-frequency = <250000000>;
};
&gem0 {
    phy-handle = <&phy9>;
    phy9: phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x5>;
    };
};

&i2c0 {
status = "okay";
clock-frequency = <400000>;

    lm87@2e {
        compatible = "ti,lm87";
        reg = <0x2e>;
        has-in6;
        has-in7;
    };  

    ad7291@20 {
        compatible = "adi,ad7291";
        reg = <0x20>;
    };  
};    
/* PRFI DMA */
&axi_dmac_0 {
    compatible = "adi,axi-dmac-1.00.a";

    adi,channels {
        #size-cells = <0>;
        #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <128>;
            adi,source-bus-type = <1>;
            adi,destination-bus-width = <32>;
            adi,destination-bus-type = <0>;
            adi,length-width = <24>;
        };
    };
};

/* This is the ADI default RX DMA */
&axi_ad9361_adc_dma {
    compatible = "adi,axi-dmac-1.00.a";
    adi,channels {
        #size-cells = <0>;
        #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <256>;
            adi,source-bus-type = <2>;
            adi,destination-bus-width = <64>;
            adi,destination-bus-type = <0>;
        };
    };
};

/* This is the ADI default TX DMA */
&axi_ad9361_dac_dma {
    compatible = "adi,axi-dmac-1.00.a";
    adi,channels {
            #size-cells = <0>;
            #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <64>;
            adi,source-bus-type = <0>;
            adi,destination-bus-width = <256>;
            adi,destination-bus-type = <2>;
        };
    };
};
/* these are each of the AD9361 IP blocks in Vivado A2D*/
&axi_ad9361_0_L1Ant0_L1Ant1 {            
            compatible = "adi,axi-ad9361-6.00.a";
            /*dmas = <&axi_ad9361_adc_dma 0>;*/
            /*dma-names = "rx";*/
            spibus-connected = <&adc0_ad9361>;
            /*slavecore-reg = <0x99040000 0x6000>;*/
        };

&axi_ad9361_1_L1Ant2 {            
            compatible = "adi,axi-ad9361-6.00.a";
            spibus-connected = <&adc1_ad9361>;       
        };

&axi_ad9361_2_L2Ant0_L2Ant1 {            
            compatible = "adi,axi-ad9361-6.00.a";
            spibus-connected = <&adc2_ad9361>;           
        };

&axi_ad9361_3_L2Ant2 {            
            compatible = "adi,axi-ad9361-6.00.a";            
            spibus-connected = <&adc3_ad9361>;
        };



#include "ad9361_spi_and_clock.dtsi"

&adc0_ad9361 {
    reset-gpios = <&gpio 130 0>;
    sync-gpios = <&gpio 129 0>;   
    enable-gpios = <&gpio 132 0>;
};

&adc1_ad9361 {
    enable-gpios = <&gpio 135 0>;
};

&adc2_ad9361 {
    enable-gpios = <&gpio 125 0>;
};

&adc3_ad9361 {
    enable-gpios = <&gpio 124 0>;
};



              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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													0
							
			
				
									
							        
			
			
			
              •  Analog Employees  
              
            
			                            
                                                                                                                        
            
				
			
            
												
						in reply to astone21480
					
									
              
	
              

		
		
              
					
              Yes - the way the clocks are connected in our FMCOMMS5 design is that tuning can fail in case the clock are not (yet) synchronized. You can also skip the digital tuning during probe and manually trigger it after you went thought the MCS sequence for all devices.
              

              -Michael
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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													0
							
			
				
									
							        
			
			
			
              •  Analog Employees  
              
            
			                            
                                                                                                                        
            
				
			
            
												
						in reply to astone21480
					
									
              
	
              

		
		
              
					
              astone21480 said:
              noticed is that it says, "Master".  How is this "Master" set??  Device tree?  What does it mean.
              

              The master or primary is the devices which ultimately controls the SYNC GPIO. 
              
			
              

		
			
	      

		
		
	
              
	
              
		
              
			
		
              
	
              
	
              
		
						
						
				
						
				
				
		
		
              
			
		
              
	
              

              

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						in reply to mhennerich
					
									
                
	
                

		
		
                
					
                Yea, but it looks like I have two masters...  How is this set or determined?  Do I need to write my own code to sync everything like the fmcomms5 code? Or, does that code exist somewhere already,?
                
			
                

		
			
	      

		
		
	
                
	
                
		
                
			
		
                
	
                
	
                
		
						
						
				
						
				
				
		
		
                
			
		
                
	
                

                

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													0
							
			
				
									
							        
			
			
			
                •  Analog Employees  
                
            
			                            
                                                                                                                        
            
				
			
            
												
						in reply to astone21480
					
									
                
	
                

		
		
                
					
                You always need to do the MCS sync sequence from user space.
                

                There is a library function for this:
                

                https://github.com/analogdevicesinc/libad9361-iio/blob/master/ad9361_multichip_sync.c
                

                The device which has the SYNC GPIO in it's device tree node is the master, and needs to be called last.
                
			
                

		
			
	      

		
		
	
                
	
                
		
                
			
		
                
	
                
	
                
		
						
						
				
						
				
				
		
		
                
			
		
                
	
                

                

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						in reply to mhennerich
					
									
                  
	
                  

		
		
                  
					
                  Called last with? Boot process? Is it possible to bypass running the ad9361_probe on boot? Also, what's with the two rows for the digital turning vs. 15 rows?
                  
			
                  

		
			
	      

		
		
	
                  
	
                  
		
                  
			
		
                  
	
                  
	
                  
		
						
						
				
						
				
				
		
		
                  
			
		
                  
	
                  

                  

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                  •  Analog Employees  
                  
            
			                            
                                                                                                                        
            
				
			
            
												
						in reply to astone21480
					
									
                  
	
                  

		
		
                  
					
                  Please take a look at the User Guide. The MCS sequence requires that all devices need to be in a certain state before issuing the Pulses. This requires that the device that controls the SYNC pulse is the last one being called to move to the next state thus issuing the SYNC pulse while everyone is ready. 
                  

                  Well you can instantiate the driver later, but you can't just bypass probe.
                  

                  The 15 rows show good/fail across all possible data/clk delay options. The two lines only shift data or clk (Would need to check the code, too tell for sure) but at three different baseband rates, overlay them and determine the sweet spot.
                  

                  -Michael
                  
			
                  

		
			
	      

		
		
	
                  
	
                  
		
                  
			
		
                  
	
                  
	
                  
		
						
				
						
						
				
				
		
		
                  
			
		
                  
	
                  

                  

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