4 AD9361s on a single board. Need device tree help

Here is the error I am getting on boot:

[    2.510247] ad9361 spi1.0: ad9361_probe : enter (ad9361-2x)
[    2.514010] ad9361 spi1.1: ad9361_probe : enter (ad9361-2x)
[    2.519514] ad9361 spi1.2: ad9361_probe : enter (ad9361)
[    2.524792] ad9361 spi2.0: ad9361_probe : enter (ad9361)
[    2.535282] Unable to handle kernel NULL pointer dereference at virtual address 00000000
[    2.537731] Mem abort info:
[    2.540499]   Exception class = DABT (current EL), IL = 32 bits
[    2.546383]   SET = 0, FnV = 0
[    2.549407]   EA = 0, S1PTW = 0
[    2.552518] Data abort info:
[    2.555381]   ISV = 0, ISS = 0x00000005
[    2.559179]   CM = 0, WnR = 0
[    2.562124] user pgtable: 4k pages, 39-bit VAs, pgd = ffffffc02e373000
[    2.568609] [0000000000000000] *pgd=0000000000000000, *pud=0000000000000000
[    2.575532] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[    2.581055] Modules linked in:
[    2.584086] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 4.14.0 #1
[    2.589964] Hardware name: xlnx,zynqmp (DT)
[    2.594117] task: ffffffc02e850d80 task.stack: ffffff8008038000
[    2.600004] PC is at cf_axi_dds_probe+0x7c/0x9a0
[    2.604584] LR is at cf_axi_dds_probe+0x70/0x9a0
[    2.609168] pc : [<ffffff800881feac>] lr : [<ffffff800881fea0>] pstate: 80000145
[    2.616520] sp : ffffff800803bbe0
[    2.619807] x29: ffffff800803bbf0 x28: ffffffc03fee0cc0
[    2.625083] x27: ffffff8008c91000 x26: ffffffc02e155c10
[    2.630360] x25: ffffffc02e155c00 x24: ffffff8008c91fe8
[    2.635636] x23: 0000000000000000 x22: ffffffc007432000
[    2.640913] x21: ffffff800902fa90 x20: ffffffc02e155c10
[    2.646189] x19: ffffffc007432500 x18: 0000000000000001
[    2.651466] x17: 0000000000000000 x16: 0000000000000008
[    2.656742] x15: ffffffffffffffff x14: ffffffc0074c760c
[    2.662019] x13: ffffffc0074c760b x12: 0000000000000028
[    2.667295] x11: 0000000000000001 x10: 0101010101010101
[    2.672572] x9 : ffffff800803bba0 x8 : 7f7f7f7f7f7f7f7f
[    2.677848] x7 : ffffff800803bba0 x6 : ffffffc0074c760a
[    2.683125] x5 : 0000000000000000 x4 : 0000000000000000
[    2.688401] x3 : 0000000000000032 x2 : 0000000000000000
[    2.693678] x1 : 0000000000000200 x0 : ffffffc02e155c10
[    2.698955] Process swapper/0 (pid: 1, stack limit = 0xffffff8008038000)
[    2.705615] Call trace:
[    2.708038] Exception stack(0xffffff800803baa0 to 0xffffff800803bbe0)
[    2.714440] baa0: ffffffc02e155c10 0000000000000200 0000000000000000 0000000000000032
[    2.722225] bac0: 0000000000000000 0000000000000000 ffffffc0074c760a ffffff800803bba0
[    2.730010] bae0: 7f7f7f7f7f7f7f7f ffffff800803bba0 0101010101010101 0000000000000001
[    2.737795] bb00: 0000000000000028 ffffffc0074c760b ffffffc0074c760c ffffffffffffffff
[    2.745580] bb20: 0000000000000008 0000000000000000 0000000000000001 ffffffc007432500
[    2.753365] bb40: ffffffc02e155c10 ffffff800902fa90 ffffffc007432000 0000000000000000
[    2.761150] bb60: ffffff8008c91fe8 ffffffc02e155c00 ffffffc02e155c10 ffffff8008c91000
[    2.768935] bb80: ffffffc03fee0cc0 ffffff800803bbf0 ffffff800881fea0 ffffff800803bbe0
[    2.776720] bba0: ffffff800881feac 0000000080000145 00000000fffffffe ffffffc02e155c10
[    2.784505] bbc0: ffffffffffffffff ffffff800902fab8 ffffff800803bbf0 ffffff800881feac
[    2.792290] [<ffffff800881feac>] cf_axi_dds_probe+0x7c/0x9a0
[    2.797915] [<ffffff800857e2d8>] platform_drv_probe+0x58/0xb8
[    2.803622] [<ffffff800857c6d4>] driver_probe_device+0x22c/0x2d8
[    2.809590] [<ffffff800857c83c>] __driver_attach+0xbc/0xc0
[    2.815040] [<ffffff800857a814>] bus_for_each_dev+0x4c/0x98
[    2.820575] [<ffffff800857bfd0>] driver_attach+0x20/0x28
[    2.825852] [<ffffff800857bb20>] bus_add_driver+0x1b8/0x228
[    2.831389] [<ffffff800857d1d8>] driver_register+0x60/0xf8
[    2.836838] [<ffffff800857e228>] __platform_driver_register+0x40/0x48
[    2.843240] [<ffffff8008f5e3a0>] cf_axi_dds_driver_init+0x18/0x20
[    2.849295] [<ffffff8008083980>] do_one_initcall+0x38/0x128
[    2.854830] [<ffffff8008f30ccc>] kernel_init_freeable+0x138/0x1d8
[    2.860886] [<ffffff8008ab41b8>] kernel_init+0x10/0x100
[    2.866075] [<ffffff8008084c10>] ret_from_fork+0x10/0x18
[    2.871352] Code: 97f5774f aa0003f7 911402d3 aa1a03e0 (a94006e2)
[    2.877410] ---[ end trace 0026aaaea3a413a4 ]---
[    2.882014] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b

You also don't need the TPL HDL core?

I guess you do. Try without DMA, I thought there is also a SYNTHESIS option.

Then forget about the ad9361-x2 stuff. And assign each TRX it's own RX & TX TPL with all required dt properties.

-Michael 

Sorry, not sure what you mean by "TPL".  What is that acronym refer to?

mhennerich said:

TPL HDL core?

TPL stands for Transport Layer - the AXI_AD9361 IP core ...

https://wiki.analog.com/resources/fpga/docs/axi_ad9361

Hi mhennerich,

    I had some hardware problems on my custom board that I have since tracked down and remedied.  Now, I am seeing 1 of the 4 AD9361s successfully initialize, but not all 4.  What is interesting is that it runs the ad9361_probe twice in the boot sequence.  The first time all 4 boards are attempted to be initialized, but it runs into a problem with the reset (is there a timer built in to give it enough time to reset??). 

line 9395:  if (IS_ERR(phy->pdata->reset_gpio))

The second time only the first AD9361 fully initializes.  Some notes.  My design uses 1 reset line for all 4 chips.  If this is a major problem, I can alter this going forward.  

I am hitting a wall here.  My next step was to hook up the debugger.  Any suggestions on what/how to change device tree?  

Log of bootup messages that are pertinent:  

[    1.371716] ad9361 spi1.0: ad9361_probe : enter (ad9361)
[    1.372657] Error line 9395
[    1.372741] ad9361 spi1.1: ad9361_probe : enter (ad9361)
[    1.373743] ad9361 spi1.1: ad9361_reset: by SPI, this may cause unpredicted behavior!
[    1.373797] Error line 9446 PRODUCT ID doesn't match 0xFF
[    1.373814] ad9361 spi1.1: ad9361_probe : Unsupported PRODUCT_ID 0xFF
[    1.373898] ad9361 spi1.2: ad9361_probe : enter (ad9361)
[    1.374895] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
[    1.374946] Error line 9446 PRODUCT ID doesn't match 0xFF
[    1.374962] ad9361 spi1.2: ad9361_probe : Unsupported PRODUCT_ID 0xFF
[    1.375046] ad9361 spi2.0: ad9361_probe : enter (ad9361)
[    1.376035] ad9361 spi2.0: ad9361_reset: by SPI, this may cause unpredicted behavior!
[    1.376086] Error line 9446 PRODUCT ID doesn't match 0xFF
[    1.376102] ad9361 spi2.0: ad9361_probe : Unsupported PRODUCT_ID 0xFF

...

[    3.311085] ad9361 spi1.0: ad9361_probe : enter (ad9361)
[    3.460268] ad9361 spi1.0: ad9361_probe : AD936x Rev 2 successfully initialized
[    4.297600] cf_axi_adc 99020000.axi_ad9361: ADI AIM (10.00.b) at 0x99020000 mapped to 0xffffff800bd20000, probed ADC AD                                                                   9361 as MASTER
[    4.311676] rtc_zynqmp ffa60000.rtc: setting system clock to 2021-01-20 22:58:38 UTC (1611183518)

Here is my updated device tree files:

/include/ "system-conf.dtsi"
/ {
    /* reducing memory available by 0xA000 * 2 = 0x14000 */
    memory {
        device_type = "memory";
        reg = <0x0 0x0 0x0 0x3FEEC000>;
    };

    pod_dma_ctr: pod-dma-ctr@0 {
               compatible = "pod,prfi_dma";
                dmas = <&axi_dmac_0 0>;
               dma-names = "prfi_dma";
    }; 

    chosen {
    bootargs = "earlycon clk_ignore_unused cpuidle.off=1";
    };


    /* these are each of the AD9361 IP blocks in Vivado DAC*/

    /*cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@99024000 {*/
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99024000 0x0 0x1000>;             */
    /*        clocks = <&adc0_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        dmas = <&axi_ad9361_dac_dma 0>;                */
    /*        dma-names = "tx";                              */
    /*        slavecore-reg = <0x99044000 0x1000>;           */
    /*    };                                                 */
    /*cf_ad9361_dac_core_1: cf-ad9361-dds-core-B@99044000 {  */
    /*        compatible = "adi,axi-ad9361x2-dds-6.00.a";    */
    /*        reg = <0x0 0x99044000 0x0 0x1000>;             */
    /*        clocks = <&adc1_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */
    /*cf_ad9361_dac_core_2: cf-ad9361-dds-core-C@99064000 {  */
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99064000 0x0 0x1000>;             */
    /*        clocks = <&adc2_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */
    /*cf_ad9361_dac_core_3: cf-ad9361-dds-core-D@99084000 {  */
    /*        compatible = "adi,axi-ad9361-dds-6.00.a";      */
    /*        reg = <0x0 0x99084000 0x0 0x1000>;             */
    /*        clocks = <&adc3_ad9361 13>;                    */
    /*        clock-names = "sampl_clk";                     */
    /*        mastercore-reg = <0x99024000 0x1000>;          */
    /*    };                                                 */

};     
&tsu_ext_clk {
    clock-frequency = <250000000>;
};
&gem0 {
    phy-handle = <&phy9>;
    phy9: phy@9 {
        reg = <0x9>;
        xlnx,phy-type = <0x5>;
    };
};

&i2c0 {
status = "okay";
clock-frequency = <400000>;

    lm87@2e {
        compatible = "ti,lm87";
        reg = <0x2e>;
        has-in6;
        has-in7;
    };  

    ad7291@20 {
        compatible = "adi,ad7291";
        reg = <0x20>;
    };  
};    
/* PRFI DMA */
&axi_dmac_0 {
    compatible = "adi,axi-dmac-1.00.a";

    adi,channels {
        #size-cells = <0>;
        #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <128>;
            adi,source-bus-type = <1>;
            adi,destination-bus-width = <32>;
            adi,destination-bus-type = <0>;
            adi,length-width = <24>;
        };
    };
};

/* This is the ADI default RX DMA */
&axi_ad9361_adc_dma {
    compatible = "adi,axi-dmac-1.00.a";
    adi,channels {
        #size-cells = <0>;
        #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <256>;
            adi,source-bus-type = <2>;
            adi,destination-bus-width = <64>;
            adi,destination-bus-type = <0>;
        };
    };
};

/* This is the ADI default TX DMA */
&axi_ad9361_dac_dma {
    compatible = "adi,axi-dmac-1.00.a";
    adi,channels {
            #size-cells = <0>;
            #address-cells = <1>;

        dma-channel@0 {
            reg = <0>;
            adi,source-bus-width = <64>;
            adi,source-bus-type = <0>;
            adi,destination-bus-width = <256>;
            adi,destination-bus-type = <2>;
        };
    };
};
/* these are each of the AD9361 IP blocks in Vivado A2D*/
&axi_ad9361_0_L1Ant0_L1Ant1 {            
            compatible = "adi,axi-ad9361-6.00.a";
            /*dmas = <&axi_ad9361_adc_dma 0>;*/
            /*dma-names = "rx";*/
            spibus-connected = <&adc0_ad9361>;
            /*slavecore-reg = <0x99040000 0x6000>;*/
        };

&axi_ad9361_1_L1Ant2 {            
            compatible = "adi,axi-ad9361-6.00.a";
            spibus-connected = <&adc1_ad9361>;       
        };

&axi_ad9361_2_L2Ant0_L2Ant1 {            
            compatible = "adi,axi-ad9361-6.00.a";
            spibus-connected = <&adc2_ad9361>;           
        };

&axi_ad9361_3_L2Ant2 {            
            compatible = "adi,axi-ad9361-6.00.a";            
            spibus-connected = <&adc3_ad9361>;
        };



#include "ad9361_spi_and_clock.dtsi"

&adc0_ad9361 {
    reset-gpios = <&gpio 130 0>;
    sync-gpios = <&gpio 129 0>;   
    enable-gpios = <&gpio 132 0>;
};

&adc1_ad9361 {
    enable-gpios = <&gpio 135 0>;
};

&adc2_ad9361 {
    enable-gpios = <&gpio 125 0>;
};

&adc3_ad9361 {
    enable-gpios = <&gpio 124 0>;
};

/ {
	clocks {
		ad9361_clkin: clock@0 {
			#clock-cells = <0>;
			compatible = "adjustable-clock";
			clock-frequency = <80000000>;
			clock-accuracy = <200000>; /* 200 ppm (ppb) */
			clock-output-names = "ad9361_ext_refclk";
		};
	};
};

&spi0 {
    /* ad9361_0_L1Ant0_L1Ant1*/
	adc0_ad9361: ad9361-phy@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <0>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;


		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1570420000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};

	/* ad9361_1_L1Ant2 */
	adc1_ad9361: ad9361-phy-B@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <1>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;


		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1570420000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};

	/* ad9361_2_L2Ant0_L2Ant1 */
	adc2_ad9361: ad9361-phy-C@2 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <2>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;

		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1222600000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};
};

&spi1 {
	/* ad9361_3_L2Ant2 */
	adc3_ad9361: ad9361-phy-D@0 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "adi,ad9361";

		/* SPI Setup */
		reg = <0>;
		spi-cpha;
		spi-max-frequency = <10000000>;

		/* Clocks */
		clocks = <&ad9361_clkin>;
		clock-names = "ad9361_ext_refclk";
		clock-output-names = "rx_sampl_clk", "tx_sampl_clk";


		//adi,debug-mode-enable;
		/* Digital Interface Control */

		adi,pp-tx-swap-enable;
		adi,pp-rx-swap-enable;
		adi,rx-frame-pulse-mode-enable;
		adi,lvds-mode-enable;
		adi,lvds-bias-mV = <150>;
		adi,lvds-rx-onchip-termination-enable;

		adi,rx-data-clock-delay = <0>;
		adi,rx-data-delay = <9>;
		adi,tx-fb-clock-delay = <4>;
		adi,tx-data-delay = <0>;

		//adi,fdd-rx-rate-2tx-enable;

		//adi,dcxo-coarse-and-fine-tune = <8 5920>;
		adi,xo-disable-use-ext-refclk-enable;

		/* Mode Setup */

		adi,2rx-2tx-mode-enable;
		//adi,split-gain-table-mode-enable;

		/* ENSM Mode */
		//adi,frequency-division-duplex-mode-enable = <0>;
		//adi,ensm-enable-pin-pulse-mode-enable;
		//adi,ensm-enable-txnrx-control-enable;

		adi,rx1-rx2-phase-inversion-enable;

		/* adi,rx-rf-port-input-select:
		 * 0 = (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced
		 * 1 = (RX1B_N &  RX1B_P) and (RX2B_N & RX2B_P) enabled; balanced
		 * 2 = (RX1C_N &  RX1C_P) and (RX2C_N & RX2C_P) enabled; balanced
		 *
		 * 3 = RX1A_N and RX2A_N enabled; unbalanced
		 * 4 = RX1A_P and RX2A_P enabled; unbalanced
		 * 5 = RX1B_N and RX2B_N enabled; unbalanced
		 * 6 = RX1B_P and RX2B_P enabled; unbalanced
		 * 7 = RX1C_N and RX2C_N enabled; unbalanced
		 * 8 = RX1C_P and RX2C_P enabled; unbalanced
		 */

		adi,rx-rf-port-input-select = <0>; /* (RX1A_N &  RX1A_P) and (RX2A_N & RX2A_P) enabled; balanced */

		/* adi,tx-rf-port-input-select:
		 * 0	TX1A, TX2A
		 * 1	TX1B, TX2B
		 */

		adi,tx-rf-port-input-select = <0>; /* TX1A, TX2A */
		//adi,update-tx-gain-in-alert-enable;
		adi,tx-attenuation-mdB = <10000>;
		adi,tx-lo-powerdown-managed-enable;

		adi,rf-rx-bandwidth-hz = <22000000>;
		adi,rf-tx-bandwidth-hz = <18000000>;
		adi,rx-synthesizer-frequency-hz = /bits/ 64 <1222600000>;
		adi,tx-synthesizer-frequency-hz = /bits/ 64 <2400000000>;

		/*				BBPLL     ADC        R2CLK     R1CLK    CLKRF    RSAMPL  */
		adi,rx-path-clock-frequencies = <960000000 480000000 240000000 120000000 60000000 60000000>;
		/*				BBPLL     DAC        T2CLK     T1CLK    CLKTF    TSAMPL  */
		adi,tx-path-clock-frequencies = <960000000 240000000 120000000 60000000 60000000 60000000>;

		/* Gain Control */

		/* adi,gc-rx[1|2]-mode:
		 * 0 = RF_GAIN_MGC
		 * 1 = RF_GAIN_FASTATTACK_AGC
		 * 2 = RF_GAIN_SLOWATTACK_AGC
		 * 3 = RF_GAIN_HYBRID_AGC
		 */

		adi,gc-rx1-mode = <0>;
		adi,gc-rx2-mode = <0>;
		adi,gc-adc-ovr-sample-size = <4>; /* sum 4 samples */
		adi,gc-adc-small-overload-thresh = <47>; /* sum of squares */
		adi,gc-adc-large-overload-thresh = <58>; /* sum of squares */
		adi,gc-lmt-overload-high-thresh = <800>; /* mV */
		adi,gc-lmt-overload-low-thresh = <704>; /* mV */
		adi,gc-dec-pow-measurement-duration = <8192>; /* 0..524288 Samples */
		adi,gc-low-power-thresh = <24>; /* 0..-64 dBFS vals are set pos */
		//adi,gc-dig-gain-enable;
		//adi,gc-max-dig-gain = <15>;

		/* Manual Gain Control Setup */

		//adi,mgc-rx1-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		//adi,mgc-rx2-ctrl-inp-enable; /* uncomment to use ctrl inputs */
		adi,mgc-inc-gain-step = <2>;
		adi,mgc-dec-gain-step = <2>;

		/* adi,mgc-split-table-ctrl-inp-gain-mode:
		 * (relevant if adi,split-gain-table-mode-enable is set)
		 * 0 = AGC determine this
		 * 1 = only in LPF
		 * 2 = only in LMT
		 */

		adi,mgc-split-table-ctrl-inp-gain-mode = <0>;

		/* Automatic Gain Control Setup */

		adi,agc-attack-delay-extra-margin-us= <1>; /* us */
		adi,agc-outer-thresh-high = <5>; /* -dBFS */
		adi,agc-outer-thresh-high-dec-steps = <2>; /* 0..15 */
		adi,agc-inner-thresh-high = <10>; /* -dBFS */
		adi,agc-inner-thresh-high-dec-steps = <1>; /* 0..7 */
		adi,agc-inner-thresh-low = <12>; /* -dBFS */
		adi,agc-inner-thresh-low-inc-steps = <1>; /* 0..7 */
		adi,agc-outer-thresh-low = <18>; /* -dBFS */
		adi,agc-outer-thresh-low-inc-steps = <2>; /* 0..15 */

		adi,agc-adc-small-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-exceed-counter = <10>; /* 0..15 */
		adi,agc-adc-large-overload-inc-steps = <2>; /* 0..15 */
		//adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable;
		adi,agc-lmt-overload-large-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-small-exceed-counter = <10>; /* 0..15 */
		adi,agc-lmt-overload-large-inc-steps = <2>; /* 0..7 */
		//adi,agc-dig-saturation-exceed-counter = <3>; /* 0..15 */
		//adi,agc-dig-gain-step-size = <4>; /* 1..8 */

		//adi,agc-sync-for-gain-counter-enable;
		adi,agc-gain-update-interval-us = <1000>;  /* 1ms */
		//adi,agc-immed-gain-change-if-large-adc-overload-enable;
		//adi,agc-immed-gain-change-if-large-lmt-overload-enable;

		/* Fast AGC */

		adi,fagc-dec-pow-measurement-duration = <64>; /* 64 Samples */
		//adi,fagc-allow-agc-gain-increase-enable;
		adi,fagc-lp-thresh-increment-steps = <1>;
		adi,fagc-lp-thresh-increment-time = <5>;

		adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <8>;
		adi,fagc-final-overrange-count = <3>;
		//adi,fagc-gain-increase-after-gain-lock-enable;
		adi,fagc-gain-index-type-after-exit-rx-mode = <0>;
		adi,fagc-lmt-final-settling-steps = <1>;
		adi,fagc-lock-level = <10>;
		adi,fagc-lock-level-gain-increase-upper-limit = <5>;
		adi,fagc-lock-level-lmt-gain-increase-enable;

		adi,fagc-lpf-final-settling-steps = <1>;
		adi,fagc-optimized-gain-offset = <5>;
		adi,fagc-power-measurement-duration-in-state5 = <64>;
		adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <10>;
		adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
		adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0>;
		adi,fagc-rst-gla-large-adc-overload-enable;
		adi,fagc-rst-gla-large-lmt-overload-enable;
		adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <10>;
		adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
		adi,fagc-state-wait-time-ns = <260>;
		adi,fagc-use-last-lock-level-for-set-gain-enable;

		/* RSSI */

		/* adi,rssi-restart-mode:
		 * 0 = AGC_IN_FAST_ATTACK_MODE_LOCKS_THE_GAIN,
		 * 1 = EN_AGC_PIN_IS_PULLED_HIGH,
		 * 2 = ENTERS_RX_MODE,
		 * 3 = GAIN_CHANGE_OCCURS,
		 * 4 = SPI_WRITE_TO_REGISTER,
		 * 5 = GAIN_CHANGE_OCCURS_OR_EN_AGC_PIN_PULLED_HIGH,
		 */
		adi,rssi-restart-mode = <3>;
		//adi,rssi-unit-is-rx-samples-enable;
		adi,rssi-delay = <1>; /* 1us */
		adi,rssi-wait = <1>; /* 1us */
		adi,rssi-duration = <1000>; /* 1ms */

		/* Control Outputs */
		adi,ctrl-outs-index = <0>;
		adi,ctrl-outs-enable-mask = <0xFF>;

		/* AuxADC Temp Sense Control */

		adi,temp-sense-measurement-interval-ms = <1000>;
		adi,temp-sense-offset-signed = <0xCE>;
		adi,temp-sense-periodic-measurement-enable;

		/* AuxDAC Control */

		adi,aux-dac-manual-mode-enable;

		adi,aux-dac1-default-value-mV = <0>;
		//adi,aux-dac1-active-in-rx-enable;
		//adi,aux-dac1-active-in-tx-enable;
		//adi,aux-dac1-active-in-alert-enable;
		adi,aux-dac1-rx-delay-us = <0>;
		adi,aux-dac1-tx-delay-us = <0>;

		adi,aux-dac2-default-value-mV = <0>;
		//adi,aux-dac2-active-in-rx-enable;
		//adi,aux-dac2-active-in-tx-enable;
		//adi,aux-dac2-active-in-alert-enable;
		adi,aux-dac2-rx-delay-us = <0>;
		adi,aux-dac2-tx-delay-us = <0>;
	};
};

I would definitely spend each transceiver it's own RESET. Otherwise you run into all kinds of sequencing issues. The AD936x requires a RESET pulse. Otherwise the SPI can be corrupted.

What may happen in your case right now is that the RESET GPIO is not yet configured when the first devices fails to probe.

You can try to re-instantiate the failed devices (spi2.0, spi1.1, etc. )by:

#echo spi2.0 > /sys/bus/spi/drivers/ad9361/bind

You may also check:
# cat /sys/kernel/debug/gpio

You can try to assign the RESET GPIO to the first device you see on your kernel message being probed.

Regarding kernel debugging - Use printk()

pr_err("%s:%d: Some var %d\n", __func__, __LINE_, ret);

-Michael 

I would definitely spend each transceiver it's own RESET. Otherwise you run into all kinds of sequencing issues. The AD936x requires a RESET pulse. Otherwise the SPI can be corrupted.

What may happen in your case right now is that the RESET GPIO is not yet configured when the first devices fails to probe.

You can try to re-instantiate the failed devices (spi2.0, spi1.1, etc. )by:

#echo spi2.0 > /sys/bus/spi/drivers/ad9361/bind

You may also check:
# cat /sys/kernel/debug/gpio

You can try to assign the RESET GPIO to the first device you see on your kernel message being probed.

Regarding kernel debugging - Use printk()

pr_err("%s:%d: Some var %d\n", __func__, __LINE_, ret);

-Michael 

On the second time it initializes does it only try the spi0.0? Is there a way to get the reset gpio configured before it runs the probe?

You could use a gpio-hog to drive the RESET inactive.

But I would assign the RESET GPIO to the first ad9361 SPI device that probes on your system. 

Yea, that's what I did.

Looks like it kind-of worked.  I have more questions.  

1.  Why does this not work during boot?  Seems like the reset stuff is fine?  Do I need to change the order things are booted in?  

2.  Why am I seeing "probed ADC AD9361 as SLAVE".  What does the SLAVE mean in this case?  SLAVE to what or whom?  Is there something that specifies SLAVE or MASTER in the devicetree?

3.  Why on spi1.2 am I seeing the ad9361_dig_tune_delay failed?  The others are fine, but this one isn't?  I length matched all of the digital lines on my board and I modified the HDL to not have the delay blocks in there anymore since I carefully length matched.  

root@prfi:~# echo spi1.1 > /sys/bus/spi/drivers/ad9361/bind
[63187.426976] ad9361 spi1.1: ad9361_probe : enter (ad9361)
[63187.433414] ad9361 spi1.1: ad9361_reset: by SPI, this may cause unpredicted behavior!
[63187.582017] ad9361 spi1.1: ad9361_probe : AD936x Rev 2 successfully initialized
root@prfi:~# [63187.872366] cf_axi_adc 99040000.axi_ad9361: ADI AIM (10.00.b) at 0x99040000 mapped to 0xfff fff800c630000, probed ADC AD9361 as SLAVE

root@prfi:~# echo spi1.2 > /sys/bus/spi/drivers/ad9361/bind
[63204.014926] ad9361 spi1.2: ad9361_probe : enter (ad9361)
[63204.021358] ad9361 spi1.2: ad9361_reset: by SPI, this may cause unpredicted behavior!
[63204.168778] ad9361 spi1.2: ad9361_probe : AD936x Rev 2 successfully initialized
root@prfi:~# [63204.601871] SAMPL CLK: 61440000 tuning: RX
[63204.605986] 0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
[63204.610488] 0:# # # # # # # # # # # # # # # #
[63204.614990] 1:# # # # # # # # # # # # # # # #
[63204.619491] ad9361 spi1.2: ad9361_dig_tune_delay: Tuning RX FAILED!
[63204.626426] cf_axi_adc: probe of 99060000.axi_ad9361 failed with error -5

root@prfi:~# echo spi2.0 > /sys/bus/spi/drivers/ad9361/bind
[63249.282933] ad9361 spi2.0: ad9361_probe : enter (ad9361)
[63249.289366] ad9361 spi2.0: ad9361_reset: by SPI, this may cause unpredicted behavior!
[63249.438944] ad9361 spi2.0: ad9361_probe : AD936x Rev 2 successfully initialized
root@prfi:~# [63249.728722] cf_axi_adc 99080000.axi_ad9361: ADI AIM (10.00.b) at 0x99080000 mapped to 0xffffff800c670000, probed ADC AD9361 as SLAVE