adrv9009-zu11eg-adrv2crr SFP ethernet clock

Hi,

I am trying to add ethernet to PL side of SOM system with carrier board. Both 10G or 1G Xilinx ethernet subsystems need 125MHz or 156.25MHz differential clock from FPGA pins. However, I am not sure where to get these clocks from. There are clocks in the carrier board like SFP_REFCLK, ETH_REFCLK1. SFP_REFCLK is generated from HMC7044. In the reference design of this system, HMC7044 pll2 output frequency is set as 2949.12MHz which can be divided by even numbers in the range 0-4096 to output a clock at the SFP_REFCLK as shown in https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts . However, with this configuration, we cannot obtain 156.25MHz or 125MHz with any division. I could not find information regarding ETH_REFCLK1 which is the output of ad9545. I could not find dt-binding about this chip so that I can get my desired clock rate. Is it possible that this ETH_REFCLK1 in the carrier board provides 125 MHz default frequency?

Wrapping up everything, how can I get this 125MHz or 156.25MHz clock while using adrv9009-zu11eg reference design provided by ADI?

Thanks in advance,

Sermed

  • 0
    •  Analog Employees 
    on Jan 13, 2021 12:11 PM in reply to Sermed

    Hi Sermed,

    Yes, the correct configuration for adrv2crr-fmc (looking at the schematics) is to set the output driver mode to DRIVER_MODE_SINGLE_DIV_DIF, sink 15 mA current:

    output-clk@AD9545_Q1A {
      reg = <AD9545_Q1A>;
      adi,output-mode = <DRIVER_MODE_DUAL_DIV_DIF>;
      adi,current-source-microamp = <15000>;
    }

  • Couple of dt configurations I tried, but failed:

    1)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <0>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1B {
                      reg = <AD9545_Q1B>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

    2)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
                };
    
    			/* 4A */
    
    		};

    3)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

  • 0
    •  Analog Employees 
    on Jan 18, 2021 8:51 AM

    Hey,

    Is this board a RevA?

    RevA may need a bit more soldering to connect a ref clock for SFP's ethernet.

  • 0
    •  Analog Employees 
    on Jan 18, 2021 8:57 AM in reply to ADIApproved

    In any case, SFP on Talise is not yet working/supported.

    It requires a special HDL IP from Xilinx to work.

    When we tried this [at around release 2019_R1], we tried it with some Xilinx IPs.

    The IP core from Xilinx wasn't working very well.

    The Xilinx driver was also having some issues accessing memory.

    We used the AD9545 chip to provide the ref-clk for the IP core.

    At the time, we did not have a Linux driver in place for AD9545.
    We tried this on a Xilinx ZCU102 and the Talise SOM 9009 (ZU11EG)

    So, we may try this again, but it requires a bit more work to get it up and running properly.

    Until then, the main stance is that this is not yet supported.

    Apologies for the inconvenience.

    Thanks

    Alex

  • Hi,

    Board is RevB.

    Actually we already use ips of Xilinx. We successfully integrated 1G Xilinx ip to adrv9009 reference design in zcu102. In Zcu102, we get the necessary 156.25MHz clock from Si570 chip on the board.  In this ADI SOM board, the only thing problematic is that we should get the clock from ad9545 and we could not achieve it yet. 

    So, you say that we cannot get the necessary clock from the onboard chip ad9545 using the driver you added?

    Thanks,

    Sermed