I am trying to add ethernet to PL side of SOM system with carrier board. Both 10G or 1G Xilinx ethernet subsystems need 125MHz or 156.25MHz differential clock from FPGA pins. However, I am not sure where to get these clocks from. There are clocks in the carrier board like SFP_REFCLK, ETH_REFCLK1. SFP_REFCLK is generated from HMC7044. In the reference design of this system, HMC7044 pll2 output frequency is set as 2949.12MHz which can be divided by even numbers in the range 0-4096 to output a clock at the SFP_REFCLK as shown in https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts . However, with this configuration, we cannot obtain 156.25MHz or 125MHz with any division. I could not find information regarding ETH_REFCLK1 which is the output of ad9545. I could not find dt-binding about this chip so that I can get my desired clock rate. Is it possible that this ETH_REFCLK1 in the carrier board provides 125 MHz default frequency?
Wrapping up everything, how can I get this 125MHz or 156.25MHz clock while using adrv9009-zu11eg reference design provided by ADI?
Thanks in advance,