adrv9009-zu11eg-adrv2crr SFP ethernet clock

Hi,

I am trying to add ethernet to PL side of SOM system with carrier board. Both 10G or 1G Xilinx ethernet subsystems need 125MHz or 156.25MHz differential clock from FPGA pins. However, I am not sure where to get these clocks from. There are clocks in the carrier board like SFP_REFCLK, ETH_REFCLK1. SFP_REFCLK is generated from HMC7044. In the reference design of this system, HMC7044 pll2 output frequency is set as 2949.12MHz which can be divided by even numbers in the range 0-4096 to output a clock at the SFP_REFCLK as shown in https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts . However, with this configuration, we cannot obtain 156.25MHz or 125MHz with any division. I could not find information regarding ETH_REFCLK1 which is the output of ad9545. I could not find dt-binding about this chip so that I can get my desired clock rate. Is it possible that this ETH_REFCLK1 in the carrier board provides 125 MHz default frequency?

Wrapping up everything, how can I get this 125MHz or 156.25MHz clock while using adrv9009-zu11eg reference design provided by ADI?

Thanks in advance,

Sermed

Parents
  • 0
    •  Analog Employees 
    on Dec 29, 2020 10:00 AM

    Hi Sermed,

    We have a Linux driver for ad9545 done. It is used to generate the above frequencies on this board. We will test the SFP and come back with an answer.

    Thanks,

    Alexandru

  • Hi,

    I have seen that you added ad9545 driver to the linux-master branch. Looking at the schematics of the adrv2crr board, I added the below device tree to system-user.dtsi in petalinux. However, I could not obtain any clock from the ETH_REFCLK1 pin. What is wrong or missing in this device tree part?

    /include/ "system-conf.dtsi"
    / {
    };
    
    
    /*
     * I2C1
     */
    #include <dt-bindings/clock/ad9545.h>
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    	pinctrl-names = "gpio";
    	pinctrl-0 = <&pinctrl_i2c1_gpio>;
    	scl-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
    	sda-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
    
    	i2c-mux@70 { /* u19 */
    		compatible = "nxp,pca9548"; /* TCA9548 */
    		#address-cells = <1>;
    		#size-cells = <0>;
    		reg = <0x70>;
    
    		i2c@0 { /* Audio ADAU1761 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    
    			adau1761: adau1761@3b {
    				compatible = "adi,adau1761";
    				reg = <0x3b>;
    
    				clocks = <&audio_clock>;
    				clock-names = "mclk";
    
    				#sound-dai-cells = <0>;
    			};
    
    		};
    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                ad9545_clock: ad9545@4A {
                        compatible = "adi,ad9545";
                        reg = <0x4A>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        adi,ref-crystal;
                        adi,ref-frequency-hz = <49152000>;
                        #clock-cells = <2>;
                        clock-output-names = "OUT1B-P", "OUT1B-N";
                        ad9545_apll1: pll-clk@1 {
                            reg = <1>;
                            adi,pll-source = <4>;
                            adi,pll-loop-bandwidth-hz = <200>;
                        };
                        aux_nco0: aux-nco-clk@0 {
                        	reg = <0>;
                        	adi,freq-lock-threshold-ps = <100000>;
                        	adi,phase-lock-threshold-ps = <100000>;
                        };
                        output-clk@8 {
                            reg = <8>;
                            adi,init-freq-hz = <156250000>;
                            adi,init-phase = <0>;
                            adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                            adi,current-source-microamp = <15000>;
                        };
                        output-clk@9 {
                            reg = <9>;
                            adi,init-freq-hz = <156250000>;
                            adi,init-phase = <180>;
                            adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                            adi,current-source-microamp = <15000>;
                        };
                };
        };
    
    			/* 4A */
    
    		};
    		i2c@2 { /* PTN5150 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <2>;
    
    			/* 1D */
    
    		};
    		i2c@3 { /* QSFP */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <3>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    		i2c@4 { /* SFP+ */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <4>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    
    		};
    		i2c@5 { /* FMC HPC */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <5>;
    
    // 			ad7291@2f {
    // 				compatible = "adi,ad7291";
    // 				reg = <0x2f>;
    // 			};
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    	};
    	
    

    Thanks,

    Sermed

  • Hi,

    Here is the output of clk_summary:

                                     enable  prepare  protect                      y
       clock                          count    count    count        rate   accurace
    --------------------------------------------------------------------------------
     spi1.1-tx_sampl_clk                  0        0        0   245760000          0
     spi1.1-obs_sampl_clk                 0        0        0   245760000          0
     spi1.1-rx_sampl_clk                  0        0        0   245760000          0
     spi1.0-tx_sampl_clk                  1        1        0   245760000          0
     spi1.0-obs_sampl_clk                 1        1        0   245760000          0
     spi1.0-rx_sampl_clk                  0        0        0   245760000          0
     spi2.1-tx_sampl_clk                  0        0        0   245760000          0
     spi2.1-obs_sampl_clk                 0        0        0   245760000          0
     spi2.1-rx_sampl_clk                  0        0        0   245760000          0
     spi2.0-tx_sampl_clk                  0        0        0   245760000          0
     spi2.0-obs_sampl_clk                 0        0        0   245760000          0
     spi2.0-rx_sampl_clk                  0        0        0   245760000          0
     hmc7044_e_out11_REFCLK_SFP           0        0        0   122880000          0
     hmc7044_e_out6_SYNC_OUT2             0        0        0      768000          0
     hmc7044_e_out5_SYNC_OUT1             0        0        0      768000          0
     hmc7044_e_out2_REFCLK_OUT2           0        0        0    30720000          0
     hmc7044_e_out0_REFCLK_OUT0           0        0        0    30720000          0
     hmc7044_c_out11_REFCLK_SFP           0        0        0   122880000          0
     hmc7044_c_out10_REFCLK_QSFP          0        0        0    30720000          0
     hmc7044_c_out9_REFCLK_OUT4           5        5        0    30720000          0
        hmc7044_fmc_out9_FPGA_SYSREF_RX_CD       0        0        0      768000   0
        hmc7044_fmc_out8_FPGA_SYSREF_TX_OBS_CD       0        0        0      768000
        hmc7044_fmc_out7_CORE_CLK_RX_CD       0        0        0   245760000      0
        hmc7044_fmc_out6_CORE_CLK_TX_OBS_CD       0        0        0   122880000  0
        hmc7044_fmc_out5_JESD_REFCLK_RX_CD       2        2        0   245760000   0
        hmc7044_fmc_out4_JESD_REFCLK_TX_OBS_CD       4        4        0   245760000
        hmc7044_fmc_out3_DEV_SYSREF_D       0        0        0     3840000        0
        hmc7044_fmc_out2_DEV_REFCLK_D       1        1        0   245760000        0
        hmc7044_fmc_out1_DEV_SYSREF_C       0        0        0     3840000        0
        hmc7044_fmc_out0_DEV_REFCLK_C       1        1        0   245760000        0
     hmc7044_c_out8_REFCLK_OUT3           0        0        0    30720000          0
     hmc7044_c_out6_SYNC_OUT2             0        0        0     3840000          0
     hmc7044_c_out5_SYNC_OUT1             0        0        0     3840000          0
     hmc7044_c_out2_REFCLK_OUT2           7        7        2    30720000          0
        hmc7044_out9_FPGA_SYSREF_RX_AB       0        0        0     3840000       0
        hmc7044_out8_FPGA_SYSREF_TX_OBS_AB       0        0        0     3840000   0
        hmc7044_out7_CORE_CLK_RX_AB       1        1        0   245760000          0
        hmc7044_out6_CORE_CLK_TX_OBS_AB       2        2        0   122880000      0
        hmc7044_out5_JESD_REFCLK_RX_AB       2        2        1   245760000       0
           rx_out_clk                     0        0        0   245760000          0
           rx_gt_clk                      1        1        1     9830400          0
        hmc7044_out4_JESD_REFCLK_TX_OBS_AB       4        4        2   245760000   0
           tx_out_clk                     0        0        0   245760000          0
           tx_gt_clk                      1        1        1     4915200          0
           rx_os_out_clk                  0        0        0   245760000          0
           rx_os_gt_clk                   1        1        1     4915200          0
        hmc7044_out3_DEV_SYSREF_B         0        0        0     3840000          0
        hmc7044_out2_DEV_REFCLK_B         1        1        0   245760000          0
        hmc7044_out1_DEV_SYSREF_A         0        0        0     3840000          0
        hmc7044_out0_DEV_REFCLK_A         1        1        0   245760000          0
     hmc7044_c_out0_REFCLK_OUT0           0        0        0    30720000          0
     audio_clock                          1        1        0    12288000          0
     dp_aclk                              1        1        0   100000000        100
     aux_ref_clk                          0        0        0    27000000          0
     gt_crx_ref_clk                       0        0        0   108000000          0
     pss_alt_ref_clk                      0        0        0           0          0
     video_clk                            0        0        0    27000000          0
     pss_ref_clk                          3        3        3    33333333          0
        vpll_post_src                     0        0        0    33333333          0
        vpll_pre_src                      0        0        0    33333333          0
           vpll_int                       0        0        0  2999999970          0
              vpll_half                   0        0        0  1499999985          0
                 vpll_int_mux             0        0        0  1499999985          0
                    vpll                  0        0        0  1499999985          0
                       dp_video_ref_mux       0        0        0  1499999985      0
                          dp_video_ref_div1       0        0        0   299999997  0
                             dp_video_ref_div2       0        0        0   299999990
                                dp_video_ref       0        0        0   299999997 0
                       vpll_to_lpd        0        0        0   499999995          0
        dpll_post_src                     0        0        0    33333333          0
        dpll_pre_src                      1        1        1    33333333          0
           dpll_int                       1        1        1  2399999976          0
              dpll_half                   1        1        1  1199999988          0
                 dpll_int_mux             1        1        1  1199999988          0
                    dpll                  1        1        1  1199999988          0
                       gpu_ref_mux        0        0        0  1199999988          0
                          gpu_ref_div1       0        0        0   599999994       0
                             gpu_ref       0        0        0   599999994         0
                                gpu_pp1_ref       0        0        0   599999994  0
                                gpu_pp0_ref       0        0        0   599999994  0
                       pcie_ref_mux       0        0        0  1199999988          0
                          pcie_ref_div1       0        0        0    99999999      0
                             pcie_ref       0        0        0    99999999        0
                       sata_ref_mux       0        0        0  1199999988          0
                          sata_ref_div1       0        0        0    99999999      0
                             sata_ref       0        0        0    99999999        0
                       dpdma_ref_mux       1        1        1  1199999988         0
                          dpdma_ref_div1       1        1        1   599999994     0
                             dpdma_ref       1        1        1   599999994       0
                       gdma_ref_mux       0        0        0  1199999988          0
                          gdma_ref_div1       0        0        0   599999994      0
                             gdma_ref       0        0        0   599999994        0
                       dp_stc_ref_mux       0        0        0  1199999988        0
                          dp_stc_ref_div1       0        0        0    26666667    0
                             dp_stc_ref_div2       0        0        0    26666667 0
                                dp_stc_ref       0        0        0    26666667   0
                       dp_audio_ref_mux       0        0        0  1199999988      0
                          dp_audio_ref_div1       0        0        0    22641510  0
                             dp_audio_ref_div2       0        0        0    22641510
                                dp_audio_ref       0        0        0    22641510 0
                       dpll_to_lpd        0        0        0   399999996          0
        apll_post_src                     0        0        0    33333333          0
        apll_pre_src                      0        0        0    33333333          0
           apll_int                       0        0        0  2666666640          0
              apll_half                   0        0        0  1333333320          0
                 apll_int_mux             0        0        0  1333333320          0
                    apll                  0        0        0  1333333320          0
                       acpu_mux           0        0        0  1333333320          0
                          acpu            0        0        0  1333333320          0
        rpll_post_src                     0        0        0    33333333          0
        rpll_pre_src                      1        1        1    33333333          0
           rpll_int                       1        1        1  1999999980          0
              rpll_half                   1        1        1   999999990          0
                 rpll_int_mux             1        1        1   999999990          0
                    rpll                  1        1        1   999999990          0
                       adma_ref_mux       0        0        0   999999990          0
                          adma_ref_div1       0        0        0   499999995      0
                             adma_ref       0        0        0   499999995        0
                       spi1_ref_mux       0        0        0   999999990          0
                          spi1_ref_div1       0        0        0   199999998      0
                             spi1_ref_div2       0        0        0   199999998   0
                                spi1_ref       0        0        0   199999998     0
                       spi0_ref_mux       0        0        0   999999990          0
                          spi0_ref_div1       0        0        0    99999999      0
                             spi0_ref_div2       0        0        0    99999999   0
                                spi0_ref       0        0        0    99999999     0
                       sdio1_ref_mux       1        1        1   999999990         0
                          sdio1_ref_div1       1        1        1   199999998     0
                             sdio1_ref_div2       1        1        1   199999998  0
                                sdio1_ref       1        1        1   199999998    0
                       rpll_to_fpd        0        0        0   499999995          0
        iopll_post_src                    0        0        0    33333333          0
        iopll_pre_src                     1        1        1    33333333          0
           iopll_int                      1        1        1  2999999970          0
              iopll_half                  1        1        1  1499999985          0
                 iopll_int_mux            1        1        1  1499999985          0
                    iopll                13       15        8  1499999985          0
                       gem3_ref_ung_mux       1        1        0  1499999985      0
                          gem3_ref_ung_div1       1        1        0  1499999985  0
                             gem3_ref_ung       1        1        0   124999999    0
                                gem3_ref       2        2        0   124999999     0
                                   gem3_tx       1        1        0   124999999   0
                       gem2_ref_ung_mux       0        0        0  1499999985      0
                          gem2_ref_ung_div1       0        0        0    62500000  0
                             gem2_ref_ung       0        0        0    62500000    0
                                gem2_ref       0        0        0    62500000     0
                                   gem2_tx       0        0        0    62500000   0
                       gem1_ref_ung_mux       0        0        0  1499999985      0
                          gem1_ref_ung_div1       0        0        0    62500000  0
                             gem1_ref_ung       0        0        0    62500000    0
                                gem1_ref       0        0        0    62500000     0
                                   gem1_tx       0        0        0    62500000   0
                       gem0_ref_ung_mux       0        0        0  1499999985      0
                          gem0_ref_ung_div1       0        0        0   124999999  0
                             gem0_ref_ung       0        0        0   124999999    0
                       pl3_ref_mux        1        1        0  1499999985          0
                          pl3_ref_div1       1        1        0    46875000       0
                             pl3_ref_div2       1        1        0     9375000    0
                                pl3_ref       1        1        0     9375000      0
                       pl2_ref_mux        1        1        0  1499999985          0
                          pl2_ref_div1       1        1        0    36585366       0
                             pl2_ref_div2       1        1        0    12195122    0
                                pl2_ref       7        7        0    12195122      0
                       pl1_ref_mux        1        1        0  1499999985          0
                          pl1_ref_div1       1        1        0    50000000       0
                             pl1_ref_div2       1        1        0    50000000    0
                                pl1_ref       1        1        0    50000000      0
                       pl0_ref_mux        1        1        0  1499999985          0
                          pl0_ref_div1       1        1        0    99999999       0
                             pl0_ref_div2       1        1        0    99999999    0
                                pl0_ref       4        4        0    99999999      0
                       ams_ref_mux        1        1        1  1499999985          0
                          ams_ref_div1       1        1        1    50000000       0
                             ams_ref_div2       1        1        1    50000000    0
                                ams_ref       1        1        1    50000000      0
                       can1_ref_mux       0        0        0  1499999985          0
                          can1_ref_div1       0        0        0    46875000      0
                             can1_ref_div2       0        0        0    46875000   0
                                can1_ref       0        0        0    46875000     0
                                   can1       0        0        0    46875000      0
                       can0_ref_mux       0        0        0  1499999985          0
                          can0_ref_div1       0        0        0    46875000      0
                             can0_ref_div2       0        0        0    46875000   0
                                can0_ref       0        0        0    46875000     0
                                   can0       0        0        0    46875000      0
                       i2c1_ref_mux       1        1        1  1499999985          0
                          i2c1_ref_div1       1        1        1    99999999      0
                             i2c1_ref_div2       1        1        1    99999999   0
                                i2c1_ref       1        1        1    99999999     0
                       i2c0_ref_mux       0        1        1  1499999985          0
                          i2c0_ref_div1       0        1        1    99999999      0
                             i2c0_ref_div2       0        1        1    99999999   0
                                i2c0_ref       0        1        1    99999999     0
                       nand_ref_mux       0        0        0  1499999985          0
                          nand_ref_div1       0        0        0    46875000      0
                             nand_ref_div2       0        0        0     9375000   0
                                nand_ref       0        0        0     9375000     0
                       uart1_ref_mux       1        1        1  1499999985         0
                          uart1_ref_div1       1        1        1    99999999     0
                             uart1_ref_div2       1        1        1    99999999  0
                                uart1_ref       1        1        1    99999999    0
                       uart0_ref_mux       0        0        0  1499999985         0
                          uart0_ref_div1       0        0        0    62500000     0
                             uart0_ref_div2       0        0        0    62500000  0
                                uart0_ref       0        0        0    62500000    0
                       sdio0_ref_mux       0        0        0  1499999985         0
                          sdio0_ref_div1       0        0        0    99999999     0
                             sdio0_ref_div2       0        0        0    99999999  0
                                sdio0_ref       0        0        0    99999999    0
                       qspi_ref_mux       0        1        1  1499999985          0
                          qspi_ref_div1       0        1        1   299999997      0
                             qspi_ref_div2       0        1        1   299999997   0
                                qspi_ref       0        1        1   299999997     0
                       gem_tsu_ref_mux       1        1        1  1499999985       0
                          gem_tsu_ref_div1       1        1        1   249999998   0
                             gem_tsu_ref_div2       1        1        1   2499999980
                                gem_tsu_ref       1        1        1   249999998  0
                                   gem_tsu       2        2        0   249999998   0
                       usb3_dual_ref_mux       1        1        1  1499999985     0
                          usb3_dual_ref_div1       1        1        1    60000000 0
                             usb3_dual_ref_div2       1        1        1    2000000
                                usb3_dual_ref       1        1        1    200000000
                       usb1_bus_ref_mux       0        0        0  1499999985      0
                          usb1_bus_ref_div1       0        0        0   124999999  0
                             usb1_bus_ref_div2       0        0        0   124999990
                                usb1_bus_ref       0        0        0   124999999 0
                       usb0_bus_ref_mux       1        1        1  1499999985      0
                          usb0_bus_ref_div1       1        1        1   249999998  0
                             usb0_bus_ref_div2       1        1        1   249999990
                                usb0_bus_ref       1        1        1   249999998 0
                       lpd_lsbus_mux       1        1        0  1499999985         0
                          lpd_lsbus_div1       1        1        0    99999999     0
                             lpd_lsbus       7        8        0    99999999       0
                                lpd_wdt       0        0        0    99999999      0
                       iopll_to_fpd       1        1        0   499999995          0
                          topsw_lsbus_mux       1        1        0   499999995    0
                             topsw_lsbus_div1       1        1        0    999999990
                                topsw_lsbus       3        3        0    99999999  0
                                   fpd_wdt       1        1        0    99999999   0
     PLL1                                 1        1        0           0          0
        Q1BB-div                          0        0        0           0          0
        Q1B-div                           0        0        0           0          0
     gem0_ref                             2        2        0           0          0
        gem0_tx                           1        1        0           0          0
     can1_mio                             0        0        0           0          0
     can0_mio                             0        0        0           0          0
     gem3_rx                              1        1        0           0          0
     gem2_rx                              0        0        0           0          0
     gem1_rx                              0        0        0           0          0
     gem0_rx                              1        1        0           0          0

    Here is the system-user.dtsi :

    /include/ "system-conf.dtsi"
    / {
    };
    
    
    /*
     * I2C1
     */
    #include <dt-bindings/clock/ad9545.h>
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    	pinctrl-names = "gpio";
    	pinctrl-0 = <&pinctrl_i2c1_gpio>;
    	scl-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
    	sda-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
    
    	i2c-mux@70 { /* u19 */
    		compatible = "nxp,pca9548"; /* TCA9548 */
    		#address-cells = <1>;
    		#size-cells = <0>;
    		reg = <0x70>;
    
    		i2c@0 { /* Audio ADAU1761 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    
    			adau1761: adau1761@3b {
    				compatible = "adi,adau1761";
    				reg = <0x3b>;
    
    				clocks = <&audio_clock>;
    				clock-names = "mclk";
    
    				#sound-dai-cells = <0>;
    			};
    
    		};
    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1B {
                      reg = <AD9545_Q1B>;
                      adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
                };
        };
    
    			/* 4A */
    
    		};
    		i2c@2 { /* PTN5150 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <2>;
    
    			/* 1D */
    
    		};
    		i2c@3 { /* QSFP */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <3>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    		i2c@4 { /* SFP+ */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <4>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    
    		};
    		i2c@5 { /* FMC HPC */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <5>;
    
    // 			ad7291@2f {
    // 				compatible = "adi,ad7291";
    // 				reg = <0x2f>;
    // 			};
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    	};
    	
    Here is the related part of the overall dts compiled by Petalinux (could not paste it all as it'is too long):

    i2c@ff030000 {
    			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
    			status = "okay";
    			interrupt-parent = <0x4>;
    			interrupts = <0x0 0x12 0x4>;
    			reg = <0x0 0xff030000 0x0 0x1000>;
    			#address-cells = <0x1>;
    			#size-cells = <0x0>;
    			power-domains = <0xc 0x26>;
    			clocks = <0x3 0x3e>;
    			clock-frequency = <0x61a80>;
    			pinctrl-names = "gpio";
    			pinctrl-0 = <0x16>;
    			scl-gpios = <0x12 0x20 0x0>;
    			sda-gpios = <0x12 0x21 0x0>;
    
    			i2c-mux@70 {
    				compatible = "nxp,pca9548";
    				#address-cells = <0x1>;
    				#size-cells = <0x0>;
    				reg = <0x70>;
    
    				i2c@0 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x0>;
    
    					adau1761@3b {
    						compatible = "adi,adau1761";
    						reg = <0x3b>;
    						clocks = <0x17>;
    						clock-names = "mclk";
    						#sound-dai-cells = <0x0>;
    						phandle = <0x3d>;
    					};
    				};
    
    				i2c@1 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x1>;
    
    					ad9545@4A {
    						compatible = "adi,ad9545";
    						reg = <0x4a>;
    						#address-cells = <0x1>;
    						#size-cells = <0x0>;
    						adi,ref-crystal;
    						adi,ref-frequency-hz = <0x2ee0000>;
    						#clock-cells = <0x2>;
    						assigned-clocks = <0x18 0x2 0x0 0x18 0x1 0x1 0x18 0x0 0x6 0x18 0x0 0x8>;
    						assigned-clock-rates = <0x2710 0x6fc23ac0 0x9502f90 0x9502f90>;
    						assigned-clock-phases = <0x0 0x0 0x0 0xb4>;
    						phandle = <0x18>;
    
    						aux-nco-clk@0 {
    							reg = <0x0>;
    							adi,freq-lock-threshold-ps = <0xf42400>;
    							adi,phase-lock-threshold-ps = <0xf42400>;
    						};
    
    						pll-clk@1 {
    							reg = <0x1>;
    							adi,pll-source = <0x4>;
    							adi,pll-loop-bandwidth-hz = <0xc8>;
    						};
    
    						output-clk@6 {
    							reg = <0x6>;
    							adi,output-mode = <0x2>;
    							adi,current-source-microamp = <0x3a98>;
    						};
    
    						output-clk@8 {
    							reg = <0x8>;
    							adi,output-mode = <0x2>;
    							adi,current-source-microamp = <0x3a98>;
    						};
    					};
    				};
    
    				i2c@2 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x2>;
    				};
    
    				i2c@3 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x3>;
    
    					eeprom@50 {
    						compatible = "at24,24c02";
    						reg = <0x50>;
    					};
    				};
    
    				i2c@4 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x4>;
    
    					eeprom@50 {
    						compatible = "at24,24c02";
    						reg = <0x50>;
    					};
    				};
    
    				i2c@5 {
    					#address-cells = <0x1>;
    					#size-cells = <0x0>;
    					reg = <0x5>;
    
    					eeprom@50 {
    						compatible = "at24,24c02";
    						reg = <0x50>;
    					};
    				};
    			};

  • 0
    •  Analog Employees 
    on Jan 13, 2021 10:24 AM in reply to Sermed

    Hi Sermed,

    The device tree looks good. The problem is that the auxiliary NCO clock is not registering in the common clock framework.

    I fixed this here: https://github.com/analogdevicesinc/linux/pull/1371/files

    As a bypass, just to check if this is the problem, you could try changing the aux-nco-clk@AD9545_NCO0 to:

                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;

                        adi,nco-freq-hz = <10000>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                   }

    Thanks,

    Alexandru Tachici

  • Hi,

    Actually this made a change in the clock summary output:

                                     enable  prepare  protect                                duty
       clock                          count    count    count        rate   accuracy phase  cycle
    ---------------------------------------------------------------------------------------------
     spi1.1-tx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi1.1-obs_sampl_clk                 0        0        0   245760000          0     0  50000
     spi1.1-rx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi1.0-tx_sampl_clk                  1        1        0   245760000          0     0  50000
     spi1.0-obs_sampl_clk                 1        1        0   245760000          0     0  50000
     spi1.0-rx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi2.1-tx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi2.1-obs_sampl_clk                 0        0        0   245760000          0     0  50000
     spi2.1-rx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi2.0-tx_sampl_clk                  0        0        0   245760000          0     0  50000
     spi2.0-obs_sampl_clk                 0        0        0   245760000          0     0  50000
     spi2.0-rx_sampl_clk                  0        0        0   245760000          0     0  50000
     AUX_NCO0                             0        0        0       10000          0     0  50000
        PLL1                              0        0        0  1875000000          0     0  50000
           Q1B-div                        0        0        0   156250000          0     0  50000
           Q1A-div                        0        0        0   156250000          0     0  50000
     hmc7044_e_out11_REFCLK_SFP           0        0        0   122880000          0     0  50000
     hmc7044_e_out6_SYNC_OUT2             0        0        0      768000          0     0  50000
     hmc7044_e_out5_SYNC_OUT1             0        0        0      768000          0     0  50000
     hmc7044_e_out2_REFCLK_OUT2           0        0        0    30720000          0     0  50000
     hmc7044_e_out0_REFCLK_OUT0           0        0        0    30720000          0     0  50000
     hmc7044_c_out11_REFCLK_SFP           0        0        0   122880000          0     0  50000
     hmc7044_c_out10_REFCLK_QSFP          0        0        0    30720000          0     0  50000
     hmc7044_c_out9_REFCLK_OUT4           5        5        0    30720000          0     0  50000
        hmc7044_fmc_out9_FPGA_SYSREF_RX_CD       0        0        0      768000          0     0  50000
        hmc7044_fmc_out8_FPGA_SYSREF_TX_OBS_CD       0        0        0      768000          0     0  50000
        hmc7044_fmc_out7_CORE_CLK_RX_CD       0        0        0   245760000          0     0  50000
        hmc7044_fmc_out6_CORE_CLK_TX_OBS_CD       0        0        0   122880000          0     0  50000
        hmc7044_fmc_out5_JESD_REFCLK_RX_CD       2        2        0   245760000          0     0  50000
        hmc7044_fmc_out4_JESD_REFCLK_TX_OBS_CD       4        4        0   245760000          0     0  50000
        hmc7044_fmc_out3_DEV_SYSREF_D       0        0        0     3840000          0     0  50000
        hmc7044_fmc_out2_DEV_REFCLK_D       1        1        0   245760000          0     0  50000
        hmc7044_fmc_out1_DEV_SYSREF_C       0        0        0     3840000          0     0  50000
        hmc7044_fmc_out0_DEV_REFCLK_C       1        1        0   245760000          0     0  50000
     hmc7044_c_out8_REFCLK_OUT3           0        0        0    30720000          0     0  50000
     hmc7044_c_out6_SYNC_OUT2             0        0        0     3840000          0     0  50000
     hmc7044_c_out5_SYNC_OUT1             0        0        0     3840000          0     0  50000
     hmc7044_c_out2_REFCLK_OUT2           7        7        2    30720000          0     0  50000
        hmc7044_out9_FPGA_SYSREF_RX_AB       0        0        0     3840000          0     0  50000
        hmc7044_out8_FPGA_SYSREF_TX_OBS_AB       0        0        0     3840000          0     0  50000
        hmc7044_out7_CORE_CLK_RX_AB       1        1        0   245760000          0     0  50000
        hmc7044_out6_CORE_CLK_TX_OBS_AB       2        2        0   122880000          0     0  50000
        hmc7044_out5_JESD_REFCLK_RX_AB       2        2        1   245760000          0     0  50000
           rx_out_clk                     0        0        0   245760000          0     0  50000
           rx_gt_clk                      1        1        1     9830400          0     0  50000
        hmc7044_out4_JESD_REFCLK_TX_OBS_AB       4        4        2   245760000          0     0  50000
           tx_out_clk                     0        0        0   245760000          0     0  50000
           tx_gt_clk                      1        1        1     4915200          0     0  50000
           rx_os_out_clk                  0        0        0   245760000          0     0  50000
           rx_os_gt_clk                   1        1        1     4915200          0     0  50000
        hmc7044_out3_DEV_SYSREF_B         0        0        0     3840000          0     0  50000
        hmc7044_out2_DEV_REFCLK_B         1        1        0   245760000          0     0  50000
        hmc7044_out1_DEV_SYSREF_A         0        0        0     3840000          0     0  50000
        hmc7044_out0_DEV_REFCLK_A         1        1        0   245760000          0     0  50000
     hmc7044_c_out0_REFCLK_OUT0           0        0        0    30720000          0     0  50000
     audio_clock                          1        1        0    12288000          0     0  50000
     dp_aclk                              1        1        0   100000000        100     0  50000
     aux_ref_clk                          0        0        0    27000000          0     0  50000
     gt_crx_ref_clk                       0        0        0   108000000          0     0  50000
     pss_alt_ref_clk                      0        0        0           0          0     0  50000
     video_clk                            0        0        0    27000000          0     0  50000
     pss_ref_clk                          3        3        3    33333333          0     0  50000
        vpll_post_src                     0        0        0    33333333          0     0  50000
        vpll_pre_src                      0        0        0    33333333          0     0  50000
           vpll_int                       0        0        0  2999999970          0     0  50000
              vpll_half                   0        0        0  1499999985          0     0  50000
                 vpll_int_mux             0        0        0  1499999985          0     0  50000
                    vpll                  0        0        0  1499999985          0     0  50000
                       dp_video_ref_mux       0        0        0  1499999985          0     0  50000
                          dp_video_ref_div1       0        0        0   299999997          0     0  50000
                             dp_video_ref_div2       0        0        0   299999997          0     0  50000
                                dp_video_ref       0        0        0   299999997          0     0  50000
                       vpll_to_lpd        0        0        0   499999995          0     0  50000
        dpll_post_src                     0        0        0    33333333          0     0  50000
        dpll_pre_src                      1        1        1    33333333          0     0  50000
           dpll_int                       1        1        1  2399999976          0     0  50000
              dpll_half                   1        1        1  1199999988          0     0  50000
                 dpll_int_mux             1        1        1  1199999988          0     0  50000
                    dpll                  1        1        1  1199999988          0     0  50000
                       gpu_ref_mux        0        0        0  1199999988          0     0  50000
                          gpu_ref_div1       0        0        0   599999994          0     0  50000
                             gpu_ref       0        0        0   599999994          0     0  50000
                                gpu_pp1_ref       0        0        0   599999994          0     0  50000
                                gpu_pp0_ref       0        0        0   599999994          0     0  50000
                       pcie_ref_mux       0        0        0  1199999988          0     0  50000
                          pcie_ref_div1       0        0        0    99999999          0     0  50000
                             pcie_ref       0        0        0    99999999          0     0  50000
                       sata_ref_mux       0        0        0  1199999988          0     0  50000
                          sata_ref_div1       0        0        0    99999999          0     0  50000
                             sata_ref       0        0        0    99999999          0     0  50000
                       dpdma_ref_mux       1        1        1  1199999988          0     0  50000
                          dpdma_ref_div1       1        1        1   599999994          0     0  50000
                             dpdma_ref       1        1        1   599999994          0     0  50000
                       gdma_ref_mux       0        0        0  1199999988          0     0  50000
                          gdma_ref_div1       0        0        0   599999994          0     0  50000
                             gdma_ref       0        0        0   599999994          0     0  50000
                       dp_stc_ref_mux       0        0        0  1199999988          0     0  50000
                          dp_stc_ref_div1       0        0        0    26666667          0     0  50000
                             dp_stc_ref_div2       0        0        0    26666667          0     0  50000
                                dp_stc_ref       0        0        0    26666667          0     0  50000
                       dp_audio_ref_mux       0        0        0  1199999988          0     0  50000
                          dp_audio_ref_div1       0        0        0    22641510          0     0  50000
                             dp_audio_ref_div2       0        0        0    22641510          0     0  50000
                                dp_audio_ref       0        0        0    22641510          0     0  50000
                       dpll_to_lpd        0        0        0   399999996          0     0  50000
        apll_post_src                     0        0        0    33333333          0     0  50000
        apll_pre_src                      0        0        0    33333333          0     0  50000
           apll_int                       0        0        0  2666666640          0     0  50000
              apll_half                   0        0        0  1333333320          0     0  50000
                 apll_int_mux             0        0        0  1333333320          0     0  50000
                    apll                  0        0        0  1333333320          0     0  50000
                       acpu_mux           0        0        0  1333333320          0     0  50000
                          acpu            0        0        0  1333333320          0     0  50000
        rpll_post_src                     0        0        0    33333333          0     0  50000
        rpll_pre_src                      1        1        1    33333333          0     0  50000
           rpll_int                       1        1        1  1999999980          0     0  50000
              rpll_half                   1        1        1   999999990          0     0  50000
                 rpll_int_mux             1        1        1   999999990          0     0  50000
                    rpll                  1        1        1   999999990          0     0  50000
                       adma_ref_mux       0        0        0   999999990          0     0  50000
                          adma_ref_div1       0        0        0   499999995          0     0  50000
                             adma_ref       0        0        0   499999995          0     0  50000
                       spi1_ref_mux       0        0        0   999999990          0     0  50000
                          spi1_ref_div1       0        0        0   199999998          0     0  50000
                             spi1_ref_div2       0        0        0   199999998          0     0  50000
                                spi1_ref       0        0        0   199999998          0     0  50000
                       spi0_ref_mux       0        0        0   999999990          0     0  50000
                          spi0_ref_div1       0        0        0    99999999          0     0  50000
                             spi0_ref_div2       0        0        0    99999999          0     0  50000
                                spi0_ref       0        0        0    99999999          0     0  50000
                       sdio1_ref_mux       1        1        1   999999990          0     0  50000
                          sdio1_ref_div1       1        1        1   199999998          0     0  50000
                             sdio1_ref_div2       1        1        1   199999998          0     0  50000
                                sdio1_ref       1        1        1   199999998          0     0  50000
                       rpll_to_fpd        0        0        0   499999995          0     0  50000
        iopll_post_src                    0        0        0    33333333          0     0  50000
        iopll_pre_src                     1        1        1    33333333          0     0  50000
           iopll_int                      1        1        1  2999999970          0     0  50000
              iopll_half                  1        1        1  1499999985          0     0  50000
                 iopll_int_mux            1        1        1  1499999985          0     0  50000
                    iopll                13       15        8  1499999985          0     0  50000
                       gem3_ref_ung_mux       1        1        0  1499999985          0     0  50000
                          gem3_ref_ung_div1       1        1        0  1499999985          0     0  50000
                             gem3_ref_ung       1        1        0   124999999          0     0  50000
                                gem3_ref       2        2        0   124999999          0     0  50000
                                   gem3_tx       1        1        0   124999999          0     0  50000
                       gem2_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem2_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem2_ref_ung       0        0        0    62500000          0     0  50000
                                gem2_ref       0        0        0    62500000          0     0  50000
                                   gem2_tx       0        0        0    62500000          0     0  50000
                       gem1_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem1_ref_ung_div1       0        0        0    62500000          0     0  50000
                             gem1_ref_ung       0        0        0    62500000          0     0  50000
                                gem1_ref       0        0        0    62500000          0     0  50000
                                   gem1_tx       0        0        0    62500000          0     0  50000
                       gem0_ref_ung_mux       0        0        0  1499999985          0     0  50000
                          gem0_ref_ung_div1       0        0        0   124999999          0     0  50000
                             gem0_ref_ung       0        0        0   124999999          0     0  50000
                       pl3_ref_mux        1        1        0  1499999985          0     0  50000
                          pl3_ref_div1       1        1        0    46875000          0     0  50000
                             pl3_ref_div2       1        1        0     9375000          0     0  50000
                                pl3_ref       1        1        0     9375000          0     0  50000
                       pl2_ref_mux        1        1        0  1499999985          0     0  50000
                          pl2_ref_div1       1        1        0    36585366          0     0  50000
                             pl2_ref_div2       1        1        0    12195122          0     0  50000
                                pl2_ref       7        7        0    12195122          0     0  50000
                       pl1_ref_mux        1        1        0  1499999985          0     0  50000
                          pl1_ref_div1       1        1        0    50000000          0     0  50000
                             pl1_ref_div2       1        1        0    50000000          0     0  50000
                                pl1_ref       1        1        0    50000000          0     0  50000
                       pl0_ref_mux        1        1        0  1499999985          0     0  50000
                          pl0_ref_div1       1        1        0    99999999          0     0  50000
                             pl0_ref_div2       1        1        0    99999999          0     0  50000
                                pl0_ref       4        4        0    99999999          0     0  50000
                       ams_ref_mux        1        1        1  1499999985          0     0  50000
                          ams_ref_div1       1        1        1    50000000          0     0  50000
                             ams_ref_div2       1        1        1    50000000          0     0  50000
                                ams_ref       1        1        1    50000000          0     0  50000
                       can1_ref_mux       0        0        0  1499999985          0     0  50000
                          can1_ref_div1       0        0        0    46875000          0     0  50000
                             can1_ref_div2       0        0        0    46875000          0     0  50000
                                can1_ref       0        0        0    46875000          0     0  50000
                                   can1       0        0        0    46875000          0     0  50000
                       can0_ref_mux       0        0        0  1499999985          0     0  50000
                          can0_ref_div1       0        0        0    46875000          0     0  50000
                             can0_ref_div2       0        0        0    46875000          0     0  50000
                                can0_ref       0        0        0    46875000          0     0  50000
                                   can0       0        0        0    46875000          0     0  50000
                       i2c1_ref_mux       1        1        1  1499999985          0     0  50000
                          i2c1_ref_div1       1        1        1    99999999          0     0  50000
                             i2c1_ref_div2       1        1        1    99999999          0     0  50000
                                i2c1_ref       1        1        1    99999999          0     0  50000
                       i2c0_ref_mux       0        1        1  1499999985          0     0  50000
                          i2c0_ref_div1       0        1        1    99999999          0     0  50000
                             i2c0_ref_div2       0        1        1    99999999          0     0  50000
                                i2c0_ref       0        1        1    99999999          0     0  50000
                       nand_ref_mux       0        0        0  1499999985          0     0  50000
                          nand_ref_div1       0        0        0    46875000          0     0  50000
                             nand_ref_div2       0        0        0     9375000          0     0  50000
                                nand_ref       0        0        0     9375000          0     0  50000
                       uart1_ref_mux       1        1        1  1499999985          0     0  50000
                          uart1_ref_div1       1        1        1    99999999          0     0  50000
                             uart1_ref_div2       1        1        1    99999999          0     0  50000
                                uart1_ref       1        1        1    99999999          0     0  50000
                       uart0_ref_mux       0        0        0  1499999985          0     0  50000
                          uart0_ref_div1       0        0        0    62500000          0     0  50000
                             uart0_ref_div2       0        0        0    62500000          0     0  50000
                                uart0_ref       0        0        0    62500000          0     0  50000
                       sdio0_ref_mux       0        0        0  1499999985          0     0  50000
                          sdio0_ref_div1       0        0        0    99999999          0     0  50000
                             sdio0_ref_div2       0        0        0    99999999          0     0  50000
                                sdio0_ref       0        0        0    99999999          0     0  50000
                       qspi_ref_mux       0        1        1  1499999985          0     0  50000
                          qspi_ref_div1       0        1        1   299999997          0     0  50000
                             qspi_ref_div2       0        1        1   299999997          0     0  50000
                                qspi_ref       0        1        1   299999997          0     0  50000
                       gem_tsu_ref_mux       1        1        1  1499999985          0     0  50000
                          gem_tsu_ref_div1       1        1        1   249999998          0     0  50000
                             gem_tsu_ref_div2       1        1        1   249999998          0     0  50000
                                gem_tsu_ref       1        1        1   249999998          0     0  50000
                                   gem_tsu       2        2        0   249999998          0     0  50000
                       usb3_dual_ref_mux       1        1        1  1499999985          0     0  50000
                          usb3_dual_ref_div1       1        1        1    60000000          0     0  50000
                             usb3_dual_ref_div2       1        1        1    20000000          0     0  50000
                                usb3_dual_ref       1        1        1    20000000          0     0  50000
                       usb1_bus_ref_mux       0        0        0  1499999985          0     0  50000
                          usb1_bus_ref_div1       0        0        0   124999999          0     0  50000
                             usb1_bus_ref_div2       0        0        0   124999999          0     0  50000
                                usb1_bus_ref       0        0        0   124999999          0     0  50000
                       usb0_bus_ref_mux       1        1        1  1499999985          0     0  50000
                          usb0_bus_ref_div1       1        1        1   249999998          0     0  50000
                             usb0_bus_ref_div2       1        1        1   249999998          0     0  50000
                                usb0_bus_ref       1        1        1   249999998          0     0  50000
                       lpd_lsbus_mux       1        1        0  1499999985          0     0  50000
                          lpd_lsbus_div1       1        1        0    99999999          0     0  50000
                             lpd_lsbus       7        8        0    99999999          0     0  50000
                                lpd_wdt       0        0        0    99999999          0     0  50000
                       iopll_to_fpd       1        1        0   499999995          0     0  50000
                          topsw_lsbus_mux       1        1        0   499999995          0     0  50000
                             topsw_lsbus_div1       1        1        0    99999999          0     0  50000
                                topsw_lsbus       3        3        0    99999999          0     0  50000
                                   fpd_wdt       1        1        0    99999999          0     0  50000
     gem0_ref                             2        2        0           0          0     0  50000
        gem0_tx                           1        1        0           0          0     0  50000
     can1_mio                             0        0        0           0          0     0  50000
     can0_mio                             0        0        0           0          0     0  50000
     gem3_rx                              1        1        0           0          0     0  50000
     gem2_rx                              0        0        0           0          0     0  50000
     gem1_rx                              0        0        0           0          0     0  50000
     gem0_rx                              1        1        0           0          0     0  50000
    
    

    However, 1G core still does not output any clock. Is it possible that we did not set the output clocks to be differential in the device-tree? We set output to DRIVER_MODE_DUAL_DIV. Could changing this to DRIVER_MODE_SINGLE_DIV_DIFF help? 

    If this is the case, should we add AD9545_Q1AA as output clock to the system. 

  • 0
    •  Analog Employees 
    on Jan 13, 2021 12:11 PM in reply to Sermed

    Hi Sermed,

    Yes, the correct configuration for adrv2crr-fmc (looking at the schematics) is to set the output driver mode to DRIVER_MODE_SINGLE_DIV_DIF, sink 15 mA current:

    output-clk@AD9545_Q1A {
      reg = <AD9545_Q1A>;
      adi,output-mode = <DRIVER_MODE_DUAL_DIV_DIF>;
      adi,current-source-microamp = <15000>;
    }

  • Couple of dt configurations I tried, but failed:

    1)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <0>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1B {
                      reg = <AD9545_Q1B>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

    2)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
                };
    
    			/* 4A */
    
    		};

    3)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

Reply
  • Couple of dt configurations I tried, but failed:

    1)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <0>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1B {
                      reg = <AD9545_Q1B>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

    2)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                      adi,current-source-microamp = <15000>;
                    };
                };
    
    			/* 4A */
    
    		};

    3)

    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <1>; 
    
                ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
    
                    #address-cells = <1>;
                    #size-cells = <0>;
    
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
    
                    #clock-cells = <2>;
    
                    assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                      <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                      <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                    assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                    assigned-clock-phases = <0>, <0>, <0>, <180>;
    
                    aux-nco-clk@AD9545_NCO0 {
                        reg = <AD9545_NCO0>;
                        adi,freq-lock-threshold-ps = <16000000>;
                        adi,phase-lock-threshold-ps = <16000000>;
                    };
    
                    ad9545_apll1: pll-clk@AD9545_PLL1 {
                      reg = <AD9545_PLL1>;
                      adi,pll-source = <4>;
                      adi,pll-loop-bandwidth-hz = <200>;
                    };
    
                    output-clk@AD9545_Q1A {
                      reg = <AD9545_Q1A>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                    output-clk@AD9545_Q1AA {
                      reg = <AD9545_Q1AA>;
                      adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                      adi,current-source-microamp = <15000>;
                    };
    
                };
    
    			/* 4A */
    
    		};

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