adrv9009-zu11eg-adrv2crr SFP ethernet clock

Sermed

on Dec 28, 2020

Hi,

I am trying to add ethernet to PL side of SOM system with carrier board. Both 10G or 1G Xilinx ethernet subsystems need 125MHz or 156.25MHz differential clock from FPGA pins. However, I am not sure where to get these clocks from. There are clocks in the carrier board like SFP_REFCLK, ETH_REFCLK1. SFP_REFCLK is generated from HMC7044. In the reference design of this system, HMC7044 pll2 output frequency is set as 2949.12MHz which can be divided by even numbers in the range 0-4096 to output a clock at the SFP_REFCLK as shown in https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts . However, with this configuration, we cannot obtain 156.25MHz or 125MHz with any division. I could not find information regarding ETH_REFCLK1 which is the output of ad9545. I could not find dt-binding about this chip so that I can get my desired clock rate. Is it possible that this ETH_REFCLK1 in the carrier board provides 125 MHz default frequency?

Wrapping up everything, how can I get this 125MHz or 156.25MHz clock while using adrv9009-zu11eg reference design provided by ADI?

Thanks in advance,

Sermed

Tags: Clock Generation Devices Clock Generation and Distribution hmc7044 sfp ad9545 clock and timing Clock Synchronization ADRV9009-ZU11EG adrv2CRR Show More

Parents

0 ADIApproved

on Dec 29, 2020 5:00 AM
Hi Sermed,

We have a Linux driver for ad9545 done. It is used to generate the above frequencies on this board. We will test the SFP and come back with an answer.

Thanks,

Alexandru
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 Sermed

on Jan 7, 2021 9:24 AM in reply to ADIApproved

Hi,

I have seen that you added ad9545 driver to the linux-master branch. Looking at the schematics of the adrv2crr board, I added the below device tree to system-user.dtsi in petalinux. However, I could not obtain any clock from the ETH_REFCLK1 pin. What is wrong or missing in this device tree part?

/include/ "system-conf.dtsi"
/ {
};


/*
 * I2C1
 */
#include <dt-bindings/clock/ad9545.h>

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "gpio";
	pinctrl-0 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;

	i2c-mux@70 { /* u19 */
		compatible = "nxp,pca9548"; /* TCA9548 */
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 { /* Audio ADAU1761 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			adau1761: adau1761@3b {
				compatible = "adi,adau1761";
				reg = <0x3b>;

				clocks = <&audio_clock>;
				clock-names = "mclk";

				#sound-dai-cells = <0>;
			};

		};
		i2c@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            ad9545_clock: ad9545@4A {
                    compatible = "adi,ad9545";
                    reg = <0x4A>;
                    #address-cells = <1>;
                    #size-cells = <0>;
                    adi,ref-crystal;
                    adi,ref-frequency-hz = <49152000>;
                    #clock-cells = <2>;
                    clock-output-names = "OUT1B-P", "OUT1B-N";
                    ad9545_apll1: pll-clk@1 {
                        reg = <1>;
                        adi,pll-source = <4>;
                        adi,pll-loop-bandwidth-hz = <200>;
                    };
                    aux_nco0: aux-nco-clk@0 {
                    	reg = <0>;
                    	adi,freq-lock-threshold-ps = <100000>;
                    	adi,phase-lock-threshold-ps = <100000>;
                    };
                    output-clk@8 {
                        reg = <8>;
                        adi,init-freq-hz = <156250000>;
                        adi,init-phase = <0>;
                        adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                        adi,current-source-microamp = <15000>;
                    };
                    output-clk@9 {
                        reg = <9>;
                        adi,init-freq-hz = <156250000>;
                        adi,init-phase = <180>;
                        adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                        adi,current-source-microamp = <15000>;
                    };
            };
    };

			/* 4A */

		};
		i2c@2 { /* PTN5150 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			/* 1D */

		};
		i2c@3 { /* QSFP */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};
		};
		i2c@4 { /* SFP+ */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};

		};
		i2c@5 { /* FMC HPC */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

// 			ad7291@2f {
// 				compatible = "adi,ad7291";
// 				reg = <0x2f>;
// 			};

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};
		};
	};

Thanks,

Sermed

0 ADIApproved

on Jan 11, 2021 4:36 AM in reply to Sermed
Hi Sermed,

Can you replace the ad9545 node with this one:

ad9545_clock: ad9545@4A {
   compatible = "adi,ad9545";
   reg = <0x4A>;

   #address-cells = <1>;
   #size-cells = <0>;

   adi,ref-crystal;
   adi,ref-frequency-hz = <49152000>;

   #clock-cells = <2>;
   assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
              <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
              <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
              <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
   assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
   assigned-clock-phases = <0>, <0>, <0>, <180>;

   aux-nco-clk@AD9545_NCO0 {
       reg = <AD9545_NCO0>;
       adi,freq-lock-threshold-ps = <16000000>;
       adi,phase-lock-threshold-ps = <16000000>;
   };

   ad9545_apll1: pll-clk@AD9545_PLL1 {
      reg = <AD9545_PLL1>;
      adi,pll-source = <4>;
      adi,pll-loop-bandwidth-hz = <200>;
   };

   output-clk@AD9545_Q1A {
      reg = <AD9545_Q1A>;
      adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
      adi,current-source-microamp = <15000>;
   };

   output-clk@AD9545_Q1B {
      reg = <AD9545_Q1B>;
      adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
      adi,current-source-microamp = <15000>;
   };
};

Thanks,

Alexandru Tachici
Cancel
Up +1 Down

Reply

Verify Answer

Reject Answer

Cancel
0 Sermed
on Jan 12, 2021 8:13 AM in reply to ADIApproved
Hi,

I have tried what you suggested. I fixed couple of my mistakes but still could not obtain the clock. Not sure if I'm making a mistake. I changed the fpga pin from ETH_REFCLK1 to ETH_REFCLK2 as SFP is in the corresponding transceiver quad. In this device tree, both OUT1A and OUT1B is programmed as 156.25MHz, so there should not be a problem. Did you have a chance to try this?
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

Reply

0 Sermed
on Jan 12, 2021 8:13 AM in reply to ADIApproved
Hi,

I have tried what you suggested. I fixed couple of my mistakes but still could not obtain the clock. Not sure if I'm making a mistake. I changed the fpga pin from ETH_REFCLK1 to ETH_REFCLK2 as SFP is in the corresponding transceiver quad. In this device tree, both OUT1A and OUT1B is programmed as 156.25MHz, so there should not be a problem. Did you have a chance to try this?
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

Children

0 ADIApproved

on Jan 12, 2021 10:27 AM in reply to Sermed
Hi Sermed,

I have updated today the driver in the Linux main branch: https://github.com/analogdevicesinc/linux/pull/1372. Please try running the latest Linux image and if nothing works run a "dmesg" and paste ithe output here. I have tested this on the eval-board and there should be no problem. I will try a test on the same board as yours too.
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 Sermed

on Jan 13, 2021 1:19 AM in reply to ADIApproved

Hi,

Result is the same. Here is the dmesg output:

[    0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
[    0.000000] Linux version 4.19.0-xilinx-v2019.2 (oe-user@oe-host) (gcc version 8.2.0 (GCC)) #1 SMP Thu Jan 7 08:17:49 UTC 2021
[    0.000000] Machine model: Analog Devices ADRV9009-ZU11EG Rev.B
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff010000 (options '115200n8')
[    0.000000] bootconsole [cdns0] enabled
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] cma: Reserved 256 MiB at 0x0000000070000000
[    0.000000] On node 0 totalpages: 1048576
[    0.000000]   DMA32 zone: 7168 pages used for memmap
[    0.000000]   DMA32 zone: 0 pages reserved
[    0.000000]   DMA32 zone: 524288 pages, LIFO batch:63
[    0.000000]   Normal zone: 7168 pages used for memmap
[    0.000000]   Normal zone: 524288 pages, LIFO batch:63
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] psci: SMC Calling Convention v1.1
[    0.000000] random: get_random_bytes called from start_kernel+0x94/0x3f8 with crng_init=0
[    0.000000] percpu: Embedded 23 pages/cpu @(____ptrval____) s53656 r8192 d32360 u94208
[    0.000000] pcpu-alloc: s53656 r8192 d32360 u94208 alloc=23*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for ARM erratum 845719
[    0.000000] Speculative Store Bypass Disable mitigation not required
[    0.000000] CPU features: detected: Kernel page table isolation (KPTI)
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1034240
[    0.000000] Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] software IO TLB: mapped [mem 0x6bfff000-0x6ffff000] (64MB)
[    0.000000] Memory: 3772148K/4194304K available (12924K kernel code, 1548K rwdata, 13520K rodata, 896K init, 335K bss, 160012K reserved, 26214)
[    0.000000] rcu: Hierarchical RCU implementation.
[    0.000000] rcu:     RCU event tracing is enabled.
[    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] arch_timer: cp15 timer(s) running at 33.33MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x7b0074340, max_idle_ns: 440795202884 ns
[    0.000003] sched_clock: 56 bits at 33MHz, resolution 30ns, wraps every 2199023255543ns
[    0.008231] Console: colour dummy device 80x25
[    0.012390] Calibrating delay loop (skipped), value calculated using timer frequency.. 66.66 BogoMIPS (lpj=133332)
[    0.022667] pid_max: default: 32768 minimum: 301
[    0.027349] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.033921] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.041621] ASID allocator initialised with 32768 entries
[    0.046413] rcu: Hierarchical SRCU implementation.
[    0.051420] EFI services will not be available.
[    0.055725] smp: Bringing up secondary CPUs ...
[    0.060368] Detected VIPT I-cache on CPU1
[    0.060395] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
[    0.060672] Detected VIPT I-cache on CPU2
[    0.060689] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
[    0.060946] Detected VIPT I-cache on CPU3
[    0.060963] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
[    0.061002] smp: Brought up 1 node, 4 CPUs
[    0.095586] SMP: Total of 4 processors activated.
[    0.100259] CPU features: detected: 32-bit EL0 Support
[    0.106582] CPU: All CPU(s) started at EL2
[    0.109437] alternatives: patching kernel code
[    0.114681] devtmpfs: initialized
[    0.125468] Registered cp15_barrier emulation handler
[    0.125518] Registered setend emulation handler
[    0.129479] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.139071] futex hash table entries: 1024 (order: 4, 65536 bytes)
[    0.150139] xor: measuring software checksum speed
[    0.189266]    8regs     :  2639.000 MB/sec
[    0.229293]    8regs_prefetch:  2280.000 MB/sec
[    0.269318]    32regs    :  3027.000 MB/sec
[    0.309345]    32regs_prefetch:  2565.000 MB/sec
[    0.309385] xor: using function: 32regs (3027.000 MB/sec)
[    0.313687] pinctrl core: initialized pinctrl subsystem
[    0.319418] NET: Registered protocol family 16
[    0.323558] audit: initializing netlink subsys (disabled)
[    0.328743] audit: type=2000 audit(0.272:1): state=initialized audit_enabled=0 res=1
[    0.336365] cpuidle: using governor menu
[    0.340379] vdso: 2 pages (1 code @ (____ptrval____), 1 data @ (____ptrval____))
[    0.347593] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.354944] DMA: preallocated 256 KiB pool for atomic allocations
[    0.372300] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.439031] raid6: int64x1  gen()   494 MB/s
[    0.507065] raid6: int64x1  xor()   501 MB/s
[    0.575093] raid6: int64x2  gen()   756 MB/s
[    0.643155] raid6: int64x2  xor()   666 MB/s
[    0.711187] raid6: int64x4  gen()  1089 MB/s
[    0.779225] raid6: int64x4  xor()   819 MB/s
[    0.847266] raid6: int64x8  gen()  1291 MB/s
[    0.915291] raid6: int64x8  xor()   843 MB/s
[    0.983372] raid6: neonx1   gen()   816 MB/s
[    1.051385] raid6: neonx1   xor()   979 MB/s
[    1.119417] raid6: neonx2   gen()  1252 MB/s
[    1.187465] raid6: neonx2   xor()  1297 MB/s
[    1.255515] raid6: neonx4   gen()  1640 MB/s
[    1.323543] raid6: neonx4   xor()  1569 MB/s
[    1.391610] raid6: neonx8   gen()  1711 MB/s
[    1.459638] raid6: neonx8   xor()  1613 MB/s
[    1.459675] raid6: using algorithm neonx8 gen() 1711 MB/s
[    1.463631] raid6: .... xor() 1613 MB/s, rmw enabled
[    1.468562] raid6: using neon recovery algorithm
[    1.474059] SCSI subsystem initialized
[    1.476898] libata version 3.00 loaded.
[    1.477031] usbcore: registered new interface driver usbfs
[    1.482358] usbcore: registered new interface driver hub
[    1.487631] usbcore: registered new device driver usb
[    1.492784] media: Linux media interface: v0.10
[    1.497129] videodev: Linux video capture interface: v2.00
[    1.502602] pps_core: LinuxPPS API ver. 1 registered
[    1.507489] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.516582] PTP clock support registered
[    1.520478] EDAC MC: Ver: 3.0.0
[    1.523929] zynqmp-ipi-mbox mailbox@ff990400: Probed ZynqMP IPI Mailbox driver.
[    1.531401] jesd204: created con: id=0, topo=0, link=0, /fpga-axi@0/axi-jesd204-tx@84a30000 <-> /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000
[    1.543049] jesd204: created con: id=1, topo=0, link=0, /fpga-axi@0/axi-adxcvr-tx@84a20000 <-> /fpga-axi@0/axi-jesd204-tx@84a30000
[    1.554725] jesd204: created con: id=2, topo=0, link=0, /amba/spi@ff040000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-tx@84a20000
[    1.565796] jesd204: created con: id=3, topo=0, link=2, /fpga-axi@0/axi-adxcvr-rx-os@84a60000 <-> /fpga-axi@0/axi-jesd204-rx@84a70000
[    1.577735] jesd204: created con: id=4, topo=0, link=2, /amba/spi@ff040000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-rx-os@84a60000
[    1.589064] jesd204: created con: id=5, topo=0, link=1, /fpga-axi@0/axi-adxcvr-rx@84a40000 <-> /fpga-axi@0/axi-jesd204-rx@84a50000
[    1.600742] jesd204: created con: id=6, topo=0, link=1, /amba/spi@ff040000/hmc7044@0 <-> /fpga-axi@0/axi-adxcvr-rx@84a40000
[    1.611818] jesd204: created con: id=7, topo=0, link=1, /amba/spi@ff040000/hmc7044-car@3 <-> /amba/spi@ff050000/hmc7044-fmc@2
[    1.623059] jesd204: created con: id=8, topo=0, link=2, /amba/spi@ff040000/hmc7044-car@3 <-> /amba/spi@ff050000/hmc7044-fmc@2
[    1.634305] jesd204: created con: id=9, topo=0, link=0, /amba/spi@ff040000/hmc7044-car@3 <-> /amba/spi@ff050000/hmc7044-fmc@2
[    1.645564] jesd204: created con: id=10, topo=0, link=1, /fpga-axi@0/axi-jesd204-rx@84a50000 <-> /amba/spi@ff050000/adrv9009-phy-d@1
[    1.657408] jesd204: created con: id=11, topo=0, link=2, /fpga-axi@0/axi-jesd204-rx@84a70000 <-> /amba/spi@ff050000/adrv9009-phy-d@1
[    1.669258] jesd204: created con: id=12, topo=0, link=0, /fpga-axi@0/axi-adrv9009-tx-hpc@84a04000 <-> /amba/spi@ff050000/adrv9009-phy-d@1
[    1.681578] jesd204: created con: id=13, topo=0, link=1, /amba/spi@ff050000/adrv9009-phy-d@1 <-> /amba/spi@ff050000/adrv9009-phy-c@0
[    1.693406] jesd204: created con: id=14, topo=0, link=2, /amba/spi@ff050000/adrv9009-phy-d@1 <-> /amba/spi@ff050000/adrv9009-phy-c@0
[    1.705263] jesd204: created con: id=15, topo=0, link=0, /amba/spi@ff050000/adrv9009-phy-d@1 <-> /amba/spi@ff050000/adrv9009-phy-c@0
[    1.717091] jesd204: created con: id=16, topo=0, link=1, /amba/spi@ff050000/hmc7044-fmc@2 <-> /amba/spi@ff040000/hmc7044@0
[    1.728075] jesd204: created con: id=17, topo=0, link=2, /amba/spi@ff050000/hmc7044-fmc@2 <-> /amba/spi@ff040000/hmc7044@0
[    1.739058] jesd204: created con: id=18, topo=0, link=0, /amba/spi@ff050000/hmc7044-fmc@2 <-> /amba/spi@ff040000/hmc7044@0
[    1.750085] jesd204: created con: id=19, topo=0, link=1, /amba/spi@ff050000/adrv9009-phy-c@0 <-> /amba/spi@ff040000/adrv9009-phy-b@0
[    1.761916] jesd204: created con: id=20, topo=0, link=2, /amba/spi@ff050000/adrv9009-phy-c@0 <-> /amba/spi@ff040000/adrv9009-phy-b@0
[    1.773771] jesd204: created con: id=21, topo=0, link=0, /amba/spi@ff050000/adrv9009-phy-c@0 <-> /amba/spi@ff040000/adrv9009-phy-b@0
[    1.785638] jesd204: created con: id=22, topo=0, link=1, /amba/spi@ff040000/adrv9009-phy-b@0 <-> /amba/spi@ff040000/adrv9009-phy@0
[    1.797292] jesd204: created con: id=23, topo=0, link=2, /amba/spi@ff040000/adrv9009-phy-b@0 <-> /amba/spi@ff040000/adrv9009-phy@0
[    1.808979] jesd204: created con: id=24, topo=0, link=0, /amba/spi@ff040000/adrv9009-phy-b@0 <-> /amba/spi@ff040000/adrv9009-phy@0
[    1.820687] jesd204: /amba/spi@ff040000/adrv9009-phy@0: JESD204[0] transition uninitialized -> initialized
[    1.830225] jesd204: /amba/spi@ff040000/adrv9009-phy@0: JESD204[1] transition uninitialized -> initialized
[    1.839825] jesd204: /amba/spi@ff040000/adrv9009-phy@0: JESD204[2] transition uninitialized -> initialized
[    1.849426] jesd204: found 14 devices and 1 topologies
[    1.854562] FPGA manager framework
[    1.858055] Advanced Linux Sound Architecture Driver Initialized.
[    1.864228] Bluetooth: Core ver 2.22
[    1.867521] NET: Registered protocol family 31
[    1.871918] Bluetooth: HCI device and connection manager initialized
[    1.878234] Bluetooth: HCI socket layer initialized
[    1.883076] Bluetooth: L2CAP socket layer initialized
[    1.888103] Bluetooth: SCO socket layer initialized
[    1.893304] clocksource: Switched to clocksource arch_sys_counter
[    1.899066] VFS: Disk quotas dquot_6.6.0
[    1.902920] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.913556] NET: Registered protocol family 2
[    1.914352] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes)
[    1.921867] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
[    1.929190] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[    1.935926] TCP: Hash tables configured (established 32768 bind 32768)
[    1.942125] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[    1.948101] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[    1.954582] NET: Registered protocol family 1
[    1.958966] RPC: Registered named UNIX socket transport module.
[    1.964650] RPC: Registered udp transport module.
[    1.969317] RPC: Registered tcp transport module.
[    1.973989] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.980612] PCI: CLS 0 bytes, default 64
[    1.981004] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    1.987619] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    1.995936] Initialise system trusted keyrings
[    1.999646] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[    2.006618] NFS: Registering the id_resolver key type
[    2.011024] Key type id_resolver registered
[    2.015163] Key type id_legacy registered
[    2.019146] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    2.025812] jffs2: version 2.2. (NAND) (SUMMARY)  �© 2001-2006 Red Hat, Inc.
[    3.006113] NET: Registered protocol family 38
[    3.059218] Key type asymmetric registered
[    3.059256] Asymmetric key parser 'x509' registered
[    3.062551] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
[    3.069879] io scheduler noop registered
[    3.073769] io scheduler deadline registered
[    3.078022] io scheduler cfq registered (default)
[    3.082679] io scheduler mq-deadline registered
[    3.087176] io scheduler kyber registered
[    3.116453] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    3.120119] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    3.127325] brd: module loaded
[    3.130825] loop: module loaded
[    3.131025] Registered mathworks_ip class
[    3.134057] mtdoops: mtd device (mtddev=name/number) must be supplied
[    3.141078] libphy: Fixed MDIO Bus: probed
[    3.144961] tun: Universal TUN/TAP device driver, 1.6
[    3.148932] CAN device driver interface
[    3.153466] usbcore: registered new interface driver asix
[    3.158027] usbcore: registered new interface driver ax88179_178a
[    3.164072] usbcore: registered new interface driver cdc_ether
[    3.169866] usbcore: registered new interface driver net1080
[    3.175490] usbcore: registered new interface driver cdc_subset
[    3.181371] usbcore: registered new interface driver zaurus
[    3.186920] usbcore: registered new interface driver cdc_ncm
[    3.193095] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[    3.198998] ehci-pci: EHCI PCI platform driver
[    3.203629] usbcore: registered new interface driver uas
[    3.208714] usbcore: registered new interface driver usb-storage
[    3.214709] usbcore: registered new interface driver usbserial_generic
[    3.221159] usbserial: USB Serial support registered for generic
[    3.227129] usbcore: registered new interface driver ftdi_sio
[    3.232834] usbserial: USB Serial support registered for FTDI USB Serial Device
[    3.240103] usbcore: registered new interface driver upd78f0730
[    3.245984] usbserial: USB Serial support registered for upd78f0730
[    3.253198] i2c /dev entries driver
[    3.257379] usbcore: registered new interface driver uvcvideo
[    3.261365] USB Video Class driver (1.1.1)
[    3.265904] axi_fan_control_driver 80000000.axi-fan-control: clk_get failed with -517
[    3.273932] Bluetooth: HCI UART driver ver 2.3
[    3.277633] Bluetooth: HCI UART protocol H4 registered
[    3.282729] Bluetooth: HCI UART protocol BCSP registered
[    3.288024] Bluetooth: HCI UART protocol LL registered
[    3.293109] Bluetooth: HCI UART protocol ATH3K registered
[    3.298488] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    3.304740] Bluetooth: HCI UART protocol Intel registered
[    3.310080] Bluetooth: HCI UART protocol QCA registered
[    3.315290] usbcore: registered new interface driver bcm203x
[    3.320903] usbcore: registered new interface driver bpa10x
[    3.326436] usbcore: registered new interface driver bfusb
[    3.331886] usbcore: registered new interface driver btusb
[    3.337312] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    3.342976] usbcore: registered new interface driver ath3k
[    3.348677] EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (INTERRUPT)
[    3.358581] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
[    3.371151] sdhci: Secure Digital Host Controller Interface driver
[    3.376670] sdhci: Copyright(c) Pierre Ossman
[    3.380993] sdhci-pltfm: SDHCI platform and OF driver helper
[    3.386958] ledtrig-cpu: registered to indicate activity on CPUs
[    3.392627] zynqmp_firmware_probe Platform Management API v1.1
[    3.398384] zynqmp_firmware_probe Trustzone version v1.0
[    3.406199] zynqmp-pinctrl firmware:zynqmp-firmware:pinctrl: zynqmp pinctrl initialized
[    3.433042] zynqmp_clk_mux_get_parent() getparent failed for clock: lpd_wdt, ret = -22
[    3.435747] alg: No test for xilinx-zynqmp-aes (zynqmp-aes)
[    3.440967] zynqmp_aes zynqmp_aes: AES Successfully Registered
               
[    3.448378] alg: No test for xilinx-keccak-384 (zynqmp-keccak-384)
[    3.454547] alg: No test for xilinx-zynqmp-rsa (zynqmp-rsa)
[    3.460064] usbcore: registered new interface driver usbhid
[    3.465415] usbhid: USB HID core driver
[    3.476368] axi_sysid 85000000.axi-sysid-0: AXI System ID core version (1.00.a) found
[    3.478742] axi_sysid 85000000.axi-sysid-0: [fmcomms8] on [adrv9009zu11eg] git <c0de649e2e656bd91b5da59523beaae7d04d0bfd> clean [2020-12-21 12C
[    3.492529] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    3.499083] usbcore: registered new interface driver snd-usb-audio
[    3.506571] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    3.512631] Initializing XFRM netlink socket
[    3.516593] NET: Registered protocol family 10
[    3.521307] Segment Routing with IPv6
[    3.524640] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    3.530775] NET: Registered protocol family 17
[    3.534871] NET: Registered protocol family 15
[    3.539286] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need thi.
[    3.552355] can: controller area network core (rev 20170425 abi 9)
[    3.558335] NET: Registered protocol family 29
[    3.562724] can: raw protocol (rev 20170425)
[    3.566954] can: broadcast manager protocol (rev 20170425 t)
[    3.572578] can: netlink gateway (rev 20170425) max_hops=1
[    3.578089] Bluetooth: RFCOMM TTY layer initialized
[    3.582875] Bluetooth: RFCOMM socket layer initialized
[    3.587989] Bluetooth: RFCOMM ver 1.11
[    3.591698] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    3.596969] Bluetooth: BNEP filters: protocol multicast
[    3.602161] Bluetooth: BNEP socket layer initialized
[    3.607089] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    3.612973] Bluetooth: HIDP socket layer initialized
[    3.618004] 9pnet: Installing 9P2000 support
[    3.622149] NET: Registered protocol family 36
[    3.626565] Key type dns_resolver registered
[    3.631201] registered taskstats version 1
[    3.634860] Loading compiled-in X.509 certificates
[    3.639908] Btrfs loaded, crc32c=crc32c-generic
[    3.650020] ff010000.serial: ttyPS0 at MMIO 0xff010000 (irq = 24, base_baud = 6249999) is a xuartps
[    3.659331] console [ttyPS0] enabled
[    3.662929] bootconsole [cdns0] disabled
[    3.671237] GPIO line 13 (ulpi-phy-reset) hogged as output/high
[    3.680418] of-fpga-region fpga-full: FPGA Region probed
[    3.687213] xilinx-dpdma fd4c0000.dma: Xilinx DPDMA engine is probed
[    3.693905] xilinx-psgtr fd400000.zynqmp_phy: Lane:3 type:8 protocol:4 pll_locked:yes
[    3.703278] xilinx-dp-snd-codec fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0: Failed to get required clock freq
[    3.713391] xilinx-dp-snd-codec: probe of fd4a0000.zynqmp-display:zynqmp_dp_snd_codec0 failed with error -22
[    3.723460] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm0: Xilinx DisplayPort Sound PCM probed
[    3.731509] xilinx-dp-snd-pcm zynqmp_dp_snd_pcm1: Xilinx DisplayPort Sound PCM probed
[    3.739557] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[    3.749624] OF: graph: no port node found in /amba/zynqmp-display@fd4a0000
[    3.756715] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[    3.763323] [drm] No driver support for vblank timestamp query.
[    3.769289] xlnx-drm xlnx-drm.0: bound fd4a0000.zynqmp-display (ops 0xffffff8008de4cd8)
[    4.857316] [drm] Cannot find any crtc or sizes
[    4.862067] [drm] Initialized xlnx 1.0.0 20130509 for fd4a0000.zynqmp-display on minor 0
[    4.870165] zynqmp-display fd4a0000.zynqmp-display: ZynqMP DisplayPort Subsystem driver probed
[    4.879587] adrv9009 spi1.0: adrv9009_probe : enter
[    4.885348] adrv9009 spi1.1: adrv9009_probe : enter
[    4.938988] jesd204: /amba/spi@ff040000/hmc7044-car@3,jesd204:3,parent=spi1.3: Using as SYSREF provider
[    4.997454] adrv9009 spi2.0: adrv9009_probe : enter
[    5.002866] adrv9009 spi2.1: adrv9009_probe : enter
[    5.029570] random: fast init done
[    5.059873] m25p80 spi0.0: SPI-NOR-UniqueID 104000fe98960005100022007602444e4e
[    5.068738] m25p80 spi0.0: n25q512a (131072 Kbytes)
[    5.073624] 4 fixed-partitions partitions found on MTD device spi0.0
[    5.079967] Creating 4 MTD partitions on "spi0.0":
[    5.084752] 0x000000000000-0x000002000000 : "qspi-fsbl-uboot"
[    5.090913] 0x000002000000-0x000002020000 : "qspi-uboot-env"
[    5.096931] 0x000002020000-0x000002100000 : "qspi-nvmfs"
[    5.102589] 0x000002100000-0x000007f00000 : "qspi-linux"
[    5.108665] macb ff0b0000.ethernet: Not enabling partial store and forward
[    5.116043] libphy: MACB_mii_bus: probed
[    5.151187] macb ff0e0000.ethernet: Not enabling partial store and forward
[    5.158536] libphy: MACB_mii_bus: probed
[    5.233744] Marvell 88E1510 ff0e0000.ethernet-ffffffff:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:)
[    5.247649] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 13 (00:0a:35:00:22:01)
[    5.257800] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    5.264305] xilinx-axipmon fd0b0000.perf-monitor: Probed Xilinx APM
[    5.270768] xilinx-axipmon fd490000.perf-monitor: Probed Xilinx APM
[    5.277221] xilinx-axipmon ffa10000.perf-monitor: Probed Xilinx APM
[    5.285171] dwc3 fe200000.dwc3: Failed to get clk 'ref': -2
[    5.291038] xilinx-psgtr fd400000.zynqmp_phy: Lane:1 type:0 protocol:3 pll_locked:yes
[    5.301124] OF: graph: no port node found in /amba/zynqmp_phy@fd400000/lane1
[    5.416818] at24 0-002c: 2048 byte 24c16 EEPROM, writable, 1 bytes/write
[    5.423576] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 15
[    5.430926] i2c i2c-1: Added multiplexed i2c bus 3
[    5.969319] [drm] Cannot find any crtc or sizes
[    5.989776] ad9545 4-004a: PLL1 unlocked.
[    5.993832] i2c i2c-1: Added multiplexed i2c bus 4
[    5.998782] i2c i2c-1: Added multiplexed i2c bus 5
[    6.030128] i2c i2c-1: Added multiplexed i2c bus 6
[    6.035395] at24 7-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
[    6.042046] i2c i2c-1: Added multiplexed i2c bus 7
[    6.074709] i2c i2c-1: Added multiplexed i2c bus 8
[    6.079639] i2c i2c-1: Added multiplexed i2c bus 9
[    6.084571] i2c i2c-1: Added multiplexed i2c bus 10
[    6.089441] pca954x 1-0070: registered 8 multiplexed busses for I2C switch pca9548
[    6.097026] i2c i2c-1: of_i2c: modalias failure on /amba/i2c@ff030000/i2c@2
[    6.103977] i2c i2c-1: Failed to create I2C device for /amba/i2c@ff030000/i2c@2
[    6.111277] i2c i2c-1: of_i2c: modalias failure on /amba/i2c@ff030000/i2c@3
[    6.118228] i2c i2c-1: Failed to create I2C device for /amba/i2c@ff030000/i2c@3
[    6.125529] i2c i2c-1: of_i2c: modalias failure on /amba/i2c@ff030000/i2c@4
[    6.132481] i2c i2c-1: Failed to create I2C device for /amba/i2c@ff030000/i2c@4
[    6.139782] i2c i2c-1: of_i2c: modalias failure on /amba/i2c@ff030000/i2c@5
[    6.146733] i2c i2c-1: Failed to create I2C device for /amba/i2c@ff030000/i2c@5
[    6.154055] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 16
[    6.160304] axi_fan_control_driver 80000000.axi-fan-control: Failed to initialize device
[    6.168452] axi_fan_control_driver: probe of 80000000.axi-fan-control failed with error -22
[    6.177201] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer with timeout 60s
[    6.184695] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1333333 KHz
[    6.192089] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP for freq 1333333320 (-34)
[    6.200821] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 1199999 KHz
[    6.209350] cpu cpu0: dev_pm_opp_set_rate: failed to find current OPP for freq 1333333320 (-34)
[    6.249308] mmc0: SDHCI controller on ff170000.mmc [ff170000.mmc] using ADMA 64-bit
[    6.266257] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[    6.276425] adrv9009 spi1.0: adrv9009_probe : enter
[    6.282010] adrv9009 spi1.1: adrv9009_probe : enter
[    6.335104] adrv9009 spi2.0: adrv9009_probe : enter
[    6.344682] adrv9009 spi2.1: adrv9009_probe : enter
[    6.354493] macb ff0b0000.ethernet: Not enabling partial store and forward
[    6.361882] libphy: MACB_mii_bus: probed
[    6.390086] mmc0: Problem switching card into high-speed mode!
[    6.396021] mmc0: new SDXC card at address 0001
[    6.401013] mmcblk0: mmc0:0001 SD 58.3 GiB 
[    6.406736]  mmcblk0: p1 p2 p3
[    6.449721] Marvell 88E1510 ff0e0000.ethernet-ffffffff:01: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:)
[    6.463625] macb ff0b0000.ethernet eth1: Cadence GEM rev 0x50070106 at 0xff0b0000 irq 12 (d6:ac:09:5a:17:b8)
[    6.476353] axi_adxcvr 84a40000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A40000. Number of lanes: 8.
[    6.489691] axi_adxcvr 84a60000.axi-adxcvr-rx-os: AXI-ADXCVR-RX (17.01.a) using CPLL on GTH4 at 0x84A60000. Number of lanes: 8.
[    6.502138] axi_adxcvr 84a20000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using QPLL on GTH4 at 0x84A20000. Number of lanes: 16.
[    6.515753] asoc-simple-card talise_sound: adau-hifi <-> 82000000.axi-i2s-adi mapping ok
[    6.527191] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[    6.537374] adrv9009 spi1.0: adrv9009_probe : enter
[    6.547256] adrv9009 spi1.1: adrv9009_probe : enter
[    6.578178] cf_axi_adc 84a00000.axi-adrv9009-rx-hpc: ADI AIM (10.01.b) at 0x84A00000 mapped to 0x(____ptrval____), probed ADC ADRV9009-X4 as MR
[    6.614851] cf_axi_dds 84a04000.axi-adrv9009-tx-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____),4
[    6.629698] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition initialized -> probed
[    6.640825] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition initialized -> probed
[    6.651942] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition initialized -> probed
[    6.663114] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition probed -> idle
[    6.673625] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition probed -> idle
[    6.684136] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition probed -> idle
[    6.694702] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition idle -> device_init
[    6.705647] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition idle -> device_init
[    6.716591] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition idle -> device_init
[    6.727593] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition device_init -> link_init
[    6.738977] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition device_init -> link_init
[    6.750357] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition device_init -> link_init
[    6.761794] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_init -> link_supported
[    6.773438] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_init -> link_supported
[    6.785077] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_init -> link_supported
[    6.797372] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_supported -> link_pre_setup
[    6.809454] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_supported -> link_pre_setup
[    6.821525] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_supported -> link_pre_setup
[    6.869370] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_pre_setup -> clk_sync_stage1
[    6.881534] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_pre_setup -> clk_sync_stage1
[    6.893701] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_pre_setup -> clk_sync_stage1
[    6.917362] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage1 -> clk_sync_stage2
[    6.929613] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage1 -> clk_sync_stage2
[    6.941866] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition clk_sync_stage1 -> clk_sync_stage2
[    6.954840] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage2 -> clk_sync_stage3
[    6.967094] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage2 -> clk_sync_stage3
[    6.979347] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition clk_sync_stage2 -> clk_sync_stage3
[    6.991600] jesd204: /fpga-axi@0/axi-jesd204-rx@84a50000,jesd204:8,parent=84a50000.axi-jesd204-rx: Possible instantiation for multiple chips; 2
[    7.006809] jesd204: /fpga-axi@0/axi-jesd204-rx@84a70000,jesd204:10,parent=84a70000.axi-jesd204-rx: Possible instantiation for multiple chips;2
[    7.022218] jesd204: /fpga-axi@0/axi-jesd204-tx@84a30000,jesd204:12,parent=84a30000.axi-jesd204-tx: Possible instantiation for multiple chips;4
[    7.038803] adrv9009 spi2.1: ADIHAL_resetHw
[    7.378899] adrv9009 spi2.0: ADIHAL_resetHw
[    7.782159] adrv9009 spi1.1: ADIHAL_resetHw
[    8.110793] adrv9009 spi1.0: ADIHAL_resetHw
[    8.509339] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clk_sync_stage3 -> link_setup
[    8.521159] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clk_sync_stage3 -> link_setup
[    8.532971] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition clk_sync_stage3 -> link_setup
[    8.546187] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_setup -> opt_setup_stage1
[    8.558093] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_setup -> opt_setup_stage1
[    8.570000] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_setup -> opt_setup_stage1
[    8.657296] random: crng init done
[   16.825636] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage1 -> opt_setup_stage2
[   16.838062] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage1 -> opt_setup_stage2
[   16.850492] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition opt_setup_stage1 -> opt_setup_stage2
[   16.864413] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage2 -> opt_setup_stage3
[   16.876836] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage2 -> opt_setup_stage3
[   16.889266] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition opt_setup_stage2 -> opt_setup_stage3
[   16.904221] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage3 -> opt_setup_stage4
[   16.916645] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage3 -> opt_setup_stage4
[   16.929073] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition opt_setup_stage3 -> opt_setup_stage4
[   21.946901] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage4 -> opt_setup_stage5
[   21.959334] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage4 -> opt_setup_stage5
[   21.971759] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition opt_setup_stage4 -> opt_setup_stage5
[   21.991738] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition opt_setup_stage5 -> clocks_enable
[   22.003903] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition opt_setup_stage5 -> clocks_enable
[   22.016070] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition opt_setup_stage5 -> clocks_enable
[   22.029149] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition clocks_enable -> link_enable
[   22.040880] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition clocks_enable -> link_enable
[   22.052613] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition clocks_enable -> link_enable
[   22.101230] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_enable -> link_running
[   22.112873] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_enable -> link_running
[   22.124519] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_enable -> link_running
[   22.238084] adrv9009 spi2.1: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
[   22.260734] adrv9009 spi2.0: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
[   22.283389] adrv9009 spi1.1: adrv9009_info: adrv9009 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
[   22.306134] adrv9009 spi1.0: adrv9009_info: adrv9009-x4 Rev 192, Firmware 6.0.2 API version: 3.6.0.5 successfully initialized via jesd204-fsm
[   22.318818] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[0] transition link_running -> opt_post_running_stage
[   22.331418] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[1] transition link_running -> opt_post_running_stage
[   22.344014] jesd204: /amba/spi@ff040000/adrv9009-phy@0,jesd204:0,parent=spi1.0: JESD204[2] transition link_running -> opt_post_running_stage
[   22.357201] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[   22.367427] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[   22.379986] input: gpio_keys as /devices/platform/gpio_keys/input/input0
[   22.386935] hctosys: unable to open rtc device (rtc0)
[   22.391981] of_cfs_init
[   22.394441] of_cfs_init: OK
[   22.397427] cfg80211: Loading compiled-in X.509 certificates for regulatory database
[   22.405539] xilinx-dp-snd-card fd4a0000.zynqmp-display:zynqmp_dp_snd_card: ASoC: CPU DAI (null) not registered
[   22.523306] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
[   22.530588] ALSA device list:
[   22.533549]   #0: ADRV9009 ZU11EG ADAU1761
[   22.537914] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
[   22.546523] cfg80211: failed to load regulatory.db
[   22.574823] EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
[   22.582923] VFS: Mounted root (ext4 filesystem) on device 179:2.
[   22.590164] devtmpfs: mounted
[   22.593285] Freeing unused kernel memory: 896K
[   22.609326] Run /sbin/init as init process
[   23.655992] systemd[1]: System time before build time, advancing clock.
[   23.717457] systemd[1]: systemd 237 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT)
[   23.738975] systemd[1]: Detected architecture arm64.
[   23.774397] systemd[1]: Set hostname to <arm>.
[   24.409865] systemd[1]: File /lib/systemd/system/systemd-udevd.service:35 configures an IP firewall (IPAddressDeny=any), but the local system .
[   24.426671] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
[   24.552912] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
[   24.577383] systemd[1]: Reached target Remote File Systems.
[   24.593601] systemd[1]: Created slice User and Session Slice.
[   24.609424] systemd[1]: Reached target Swap.
[   24.625446] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
[   25.235132] systemd-journald[2410]: Received request to flush runtime journal from PID 1
[   25.331867] systemd-journald[2410]: File /var/log/journal/ccbd08173b4dcb8907efc0975a6df325/system.journal corrupted or uncleanly shut down, re.
[   28.687110] pps pps0: new PPS source ptp0
[   28.687122] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[   28.687242] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[   28.710529] pps pps1: new PPS source ptp1
[   28.710542] macb ff0b0000.ethernet: gem-ptp-timer ptp clock registered.
[   28.710666] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready
[   31.829900] macb ff0e0000.ethernet eth0: link up (1000/Full)
[   31.829919] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready

0 ADIApproved

on Jan 13, 2021 4:16 AM in reply to Sermed
Hi Sermed,

Can you please run this cmd and paste the output here:

cat /sys/kernel/debug/clk/clk_summary

This should show the assigned frequencies to the auxiliary NCO1, PLL1 and the two outputs.

Can you also paste the new device tree here?

Thanks,

Alexandru
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 Sermed

on Jan 13, 2021 4:59 AM in reply to ADIApproved

Hi,

Here is the output of clk_summary:

 clock ----------------------------------- spi1.1-tx_sampl_clk spi1.1-obs_sampl_clk spi1.1-rx_sampl_clk spi1.0-tx_sampl_clk spi1.0-obs_sampl_clk spi1.0-rx_sampl_clk spi2.1-tx_sampl_clk spi2.1-obs_sampl_clk spi2.1-rx_sampl_clk spi2.0-tx_sampl_clk spi2.0-obs_sampl_clk spi2.0-rx_sampl_clk hmc7044_e_out11_REFCLK_SFP hmc7044_e_out6_SYNC_OUT2 hmc7044_e_out5_SYNC_OUT1 hmc7044_e_out2_REFCLK_OUT2 hmc7044_e_out0_REFCLK_OUT0 hmc7044_c_out11_REFCLK_SFP hmc7044_c_out10_REFCLK_QSFP hmc7044_c_out9_REFCLK_OUT4 hmc7044_fmc_out9_FPGA_SYSREF_RX_CD hmc7044_fmc_out8_FPGA_SYSREF_TX_OBS_CD hmc7044_fmc_out7_CORE_CLK_RX_CD hmc7044_fmc_out6_CORE_CLK_TX_OBS_CD hmc7044_fmc_out5_JESD_REFCLK_RX_CD hmc7044_fmc_out4_JESD_REFCLK_TX_OBS_CD hmc7044_fmc_out3_DEV_SYSREF_D       0 hmc7044_fmc_out2_DEV_REFCLK_D       1 hmc7044_fmc_out1_DEV_SYSREF_C       0 hmc7044_fmc_out0_DEV_REFCLK_C       1 hmc7044_c_out8_REFCLK_OUT3 hmc7044_c_out6_SYNC_OUT2 hmc7044_c_out5_SYNC_OUT1 hmc7044_c_out2_REFCLK_OUT2 hmc7044_out9_FPGA_SYSREF_RX_AB hmc7044_out8_FPGA_SYSREF_TX_OBS_AB hmc7044_out7_CORE_CLK_RX_AB       1 hmc7044_out6_CORE_CLK_TX_OBS_AB hmc7044_out5_JESD_REFCLK_RX_AB rx_out_clk rx_gt_clk hmc7044_out4_JESD_REFCLK_TX_OBS_AB tx_out_clk tx_gt_clk rx_os_out_clk rx_os_gt_clk hmc7044_out3_DEV_SYSREF_B hmc7044_out2_DEV_REFCLK_B hmc7044_out1_DEV_SYSREF_A hmc7044_out0_DEV_REFCLK_A hmc7044_c_out0_REFCLK_OUT0 audio_clock dp_aclk aux_ref_clk gt_crx_ref_clk pss_alt_ref_clk video_clk pss_ref_clk vpll_post_src vpll_pre_src vpll_int vpll_half vpll_int_mux vpll dp_video_ref_mux dp_video_ref_div1 dp_video_ref_div2 dp_video_ref vpll_to_lpd dpll_post_src dpll_pre_src dpll_int dpll_half dpll_int_mux dpll gpu_ref_mux gpu_ref_div1 gpu_ref       0 gpu_pp1_ref gpu_pp0_ref pcie_ref_mux       0 pcie_ref_div1 pcie_ref       0 sata_ref_mux       0 sata_ref_div1 sata_ref       0 dpdma_ref_mux       1 dpdma_ref_div1 dpdma_ref gdma_ref_mux       0 gdma_ref_div1 gdma_ref       0 dp_stc_ref_mux       0 dp_stc_ref_div1 dp_stc_ref_div2 dp_stc_ref dp_audio_ref_mux dp_audio_ref_div1 dp_audio_ref_div2 dp_audio_ref dpll_to_lpd apll_post_src apll_pre_src apll_int apll_half apll_int_mux apll acpu_mux acpu rpll_post_src rpll_pre_src rpll_int rpll_half rpll_int_mux rpll adma_ref_mux       0 adma_ref_div1 adma_ref       0 spi1_ref_mux       0 spi1_ref_div1 spi1_ref_div2 spi1_ref spi0_ref_mux       0 spi0_ref_div1 spi0_ref_div2 spi0_ref sdio1_ref_mux       1 sdio1_ref_div1 sdio1_ref_div2 sdio1_ref rpll_to_fpd iopll_post_src iopll_pre_src iopll_int iopll_half iopll_int_mux iopll gem3_ref_ung_mux gem3_ref_ung_div1 gem3_ref_ung gem3_ref gem3_tx gem2_ref_ung_mux gem2_ref_ung_div1 gem2_ref_ung gem2_ref gem2_tx gem1_ref_ung_mux gem1_ref_ung_div1 gem1_ref_ung gem1_ref gem1_tx gem0_ref_ung_mux gem0_ref_ung_div1 gem0_ref_ung pl3_ref_mux pl3_ref_div1 pl3_ref_div2 pl3_ref pl2_ref_mux pl2_ref_div1 pl2_ref_div2 pl2_ref pl1_ref_mux pl1_ref_div1 pl1_ref_div2 pl1_ref pl0_ref_mux pl0_ref_div1 pl0_ref_div2 pl0_ref ams_ref_mux ams_ref_div1 ams_ref_div2 ams_ref can1_ref_mux       0 can1_ref_div1 can1_ref_div2 can1_ref can1 can0_ref_mux       0 can0_ref_div1 can0_ref_div2 can0_ref can0 i2c1_ref_mux       1 i2c1_ref_div1 i2c1_ref_div2 i2c1_ref i2c0_ref_mux       0 i2c0_ref_div1 i2c0_ref_div2 i2c0_ref nand_ref_mux       0 nand_ref_div1 nand_ref_div2 nand_ref uart1_ref_mux       1 uart1_ref_div1 uart1_ref_div2 uart1_ref uart0_ref_mux       0 uart0_ref_div1 uart0_ref_div2 uart0_ref sdio0_ref_mux       0 sdio0_ref_div1 sdio0_ref_div2 sdio0_ref qspi_ref_mux       0 qspi_ref_div1 qspi_ref_div2 qspi_ref gem_tsu_ref_mux gem_tsu_ref_div1 gem_tsu_ref_div2 gem_tsu_ref gem_tsu usb3_dual_ref_mux usb3_dual_ref_div1 usb3_dual_ref_div2 usb3_dual_ref usb1_bus_ref_mux usb1_bus_ref_div1 usb1_bus_ref_div2 usb1_bus_ref usb0_bus_ref_mux usb0_bus_ref_div1 usb0_bus_ref_div2 usb0_bus_ref lpd_lsbus_mux       1 lpd_lsbus_div1 lpd_lsbus lpd_wdt iopll_to_fpd       1 topsw_lsbus_mux topsw_lsbus_div1 topsw_lsbus fpd_wdt PLL1 Q1BB-div Q1B-div gem0_ref gem0_tx can1_mio can0_mio gem3_rx gem2_rx gem1_rx gem0_rx

enable  prepare  protect                      y count    count    count        rate   accurace --------------------------------------------- 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 1        1        0   245760000          0 1        1        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   245760000          0 0        0        0   122880000          0 0        0        0      768000          0 0        0        0      768000          0 0        0        0    30720000          0 0        0        0    30720000          0 0        0        0   122880000          0 0        0        0    30720000          0 5        5        0    30720000          0 0        0        0      768000   0 0        0        0      768000 0        0        0   245760000      0 0        0        0   122880000  0 2        2        0   245760000   0 4        4        0   245760000 0        0     3840000        0 1        0   245760000        0 0        0     3840000        0 1        0   245760000        0 0        0        0    30720000          0 0        0        0     3840000          0 0        0        0     3840000          0 7        7        2    30720000          0 0        0        0     3840000       0 0        0        0     3840000   0 1        0   245760000          0 2        2        0   122880000      0 2        2        1   245760000       0 0        0        0   245760000          0 1        1        1     9830400          0 4        4        2   245760000   0 0        0        0   245760000          0 1        1        1     4915200          0 0        0        0   245760000          0 1        1        1     4915200          0 0        0        0     3840000          0 1        1        0   245760000          0 0        0        0     3840000          0 1        1        0   245760000          0 0        0        0    30720000          0 1        1        0    12288000          0 1        1        0   100000000        100 0        0        0    27000000          0 0        0        0   108000000          0 0        0        0           0          0 0        0        0    27000000          0 3        3        3    33333333          0 0        0        0    33333333          0 0        0        0    33333333          0 0        0        0  2999999970          0 0        0        0  1499999985          0 0        0        0  1499999985          0 0        0        0  1499999985          0 0        0        0  1499999985      0 0        0        0   299999997  0 0        0        0   299999990 0        0        0   299999997 0 0        0        0   499999995          0 0        0        0    33333333          0 1        1        1    33333333          0 1        1        1  2399999976          0 1        1        1  1199999988          0 1        1        1  1199999988          0 1        1        1  1199999988          0 0        0        0  1199999988          0 0        0        0   599999994       0 0        0   599999994         0 0        0        0   599999994  0 0        0        0   599999994  0 0        0  1199999988          0 0        0        0    99999999      0 0        0    99999999        0 0        0  1199999988          0 0        0        0    99999999      0 0        0    99999999        0 1        1  1199999988         0 1        1        1   599999994     0 1        1        1   599999994       0 0        0  1199999988          0 0        0        0   599999994      0 0        0   599999994        0 0        0  1199999988        0 0        0        0    26666667    0 0        0        0    26666667 0 0        0        0    26666667   0 0        0        0  1199999988      0 0        0        0    22641510  0 0        0        0    22641510 0        0        0    22641510 0 0        0        0   399999996          0 0        0        0    33333333          0 0        0        0    33333333          0 0        0        0  2666666640          0 0        0        0  1333333320          0 0        0        0  1333333320          0 0        0        0  1333333320          0 0        0        0  1333333320          0 0        0        0  1333333320          0 0        0        0    33333333          0 1        1        1    33333333          0 1        1        1  1999999980          0 1        1        1   999999990          0 1        1        1   999999990          0 1        1        1   999999990          0 0        0   999999990          0 0        0        0   499999995      0 0        0   499999995        0 0        0   999999990          0 0        0        0   199999998      0 0        0        0   199999998   0 0        0        0   199999998     0 0        0   999999990          0 0        0        0    99999999      0 0        0        0    99999999   0 0        0        0    99999999     0 1        1   999999990         0 1        1        1   199999998     0 1        1        1   199999998  0 1        1        1   199999998    0 0        0        0   499999995          0 0        0        0    33333333          0 1        1        1    33333333          0 1        1        1  2999999970          0 1        1        1  1499999985          0 1        1        1  1499999985          0 13       15        8  1499999985          0 1        1        0  1499999985      0 1        1        0  1499999985  0 1        1        0   124999999    0 2        2        0   124999999     0 1        1        0   124999999   0 0        0        0  1499999985      0 0        0        0    62500000  0 0        0        0    62500000    0 0        0        0    62500000     0 0        0        0    62500000   0 0        0        0  1499999985      0 0        0        0    62500000  0 0        0        0    62500000    0 0        0        0    62500000     0 0        0        0    62500000   0 0        0        0  1499999985      0 0        0        0   124999999  0 0        0        0   124999999    0 1        1        0  1499999985          0 1        1        0    46875000       0 1        1        0     9375000    0 1        1        0     9375000      0 1        1        0  1499999985          0 1        1        0    36585366       0 1        1        0    12195122    0 7        7        0    12195122      0 1        1        0  1499999985          0 1        1        0    50000000       0 1        1        0    50000000    0 1        1        0    50000000      0 1        1        0  1499999985          0 1        1        0    99999999       0 1        1        0    99999999    0 4        4        0    99999999      0 1        1        1  1499999985          0 1        1        1    50000000       0 1        1        1    50000000    0 1        1        1    50000000      0 0        0  1499999985          0 0        0        0    46875000      0 0        0        0    46875000   0 0        0        0    46875000     0 0        0        0    46875000      0 0        0  1499999985          0 0        0        0    46875000      0 0        0        0    46875000   0 0        0        0    46875000     0 0        0        0    46875000      0 1        1  1499999985          0 1        1        1    99999999      0 1        1        1    99999999   0 1        1        1    99999999     0 1        1  1499999985          0 0        1        1    99999999      0 0        1        1    99999999   0 0        1        1    99999999     0 0        0  1499999985          0 0        0        0    46875000      0 0        0        0     9375000   0 0        0        0     9375000     0 1        1  1499999985         0 1        1        1    99999999     0 1        1        1    99999999  0 1        1        1    99999999    0 0        0  1499999985         0 0        0        0    62500000     0 0        0        0    62500000  0 0        0        0    62500000    0 0        0  1499999985         0 0        0        0    99999999     0 0        0        0    99999999  0 0        0        0    99999999    0 1        1  1499999985          0 0        1        1   299999997      0 0        1        1   299999997   0 0        1        1   299999997     0 1        1        1  1499999985       0 1        1        1   249999998   0 1        1        1   2499999980 1        1        1   249999998  0 2        2        0   249999998   0 1        1        1  1499999985     0 1        1        1    60000000 0 1        1        1    2000000 1        1        1    200000000 0        0        0  1499999985      0 0        0        0   124999999  0 0        0        0   124999990 0        0        0   124999999 0 1        1        1  1499999985      0 1        1        1   249999998  0 1        1        1   249999990 1        1        1   249999998 0 1        0  1499999985         0 1        1        0    99999999     0 7        8        0    99999999       0 0        0        0    99999999      0 1        0   499999995          0 1        1        0   499999995    0 1        1        0    999999990 3        3        0    99999999  0 1        1        0    99999999   0 1        1        0           0          0 0        0        0           0          0 0        0        0           0          0 2        2        0           0          0 1        1        0           0          0 0        0        0           0          0 0        0        0           0          0 1        1        0           0          0 0        0        0           0          0 0        0        0           0          0 1        1        0           0          0

Here is the system-user.dtsi :

/include/ "system-conf.dtsi"
/ {
};


/*
 * I2C1
 */
#include <dt-bindings/clock/ad9545.h>

&i2c1 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "gpio";
	pinctrl-0 = <&pinctrl_i2c1_gpio>;
	scl-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
	sda-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;

	i2c-mux@70 { /* u19 */
		compatible = "nxp,pca9548"; /* TCA9548 */
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x70>;

		i2c@0 { /* Audio ADAU1761 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			adau1761: adau1761@3b {
				compatible = "adi,adau1761";
				reg = <0x3b>;

				clocks = <&audio_clock>;
				clock-names = "mclk";

				#sound-dai-cells = <0>;
			};

		};
		i2c@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>; 

            ad9545_clock: ad9545@4A {
                compatible = "adi,ad9545";
                reg = <0x4A>;

                #address-cells = <1>;
                #size-cells = <0>;

                adi,ref-crystal;
                adi,ref-frequency-hz = <49152000>;

                #clock-cells = <2>;
                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                assigned-clock-phases = <0>, <0>, <0>, <180>;

                aux-nco-clk@AD9545_NCO0 {
                    reg = <AD9545_NCO0>;
                    adi,freq-lock-threshold-ps = <16000000>;
                    adi,phase-lock-threshold-ps = <16000000>;
                };

                ad9545_apll1: pll-clk@AD9545_PLL1 {
                  reg = <AD9545_PLL1>;
                  adi,pll-source = <4>;
                  adi,pll-loop-bandwidth-hz = <200>;
                };

                output-clk@AD9545_Q1A {
                  reg = <AD9545_Q1A>;
                  adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
                  adi,current-source-microamp = <15000>;
                };

                output-clk@AD9545_Q1B {
                  reg = <AD9545_Q1B>;
                  adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
                  adi,current-source-microamp = <15000>;
                };
            };
    };

			/* 4A */

		};
		i2c@2 { /* PTN5150 */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;

			/* 1D */

		};
		i2c@3 { /* QSFP */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};
		};
		i2c@4 { /* SFP+ */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};

		};
		i2c@5 { /* FMC HPC */
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <5>;

// 			ad7291@2f {
// 				compatible = "adi,ad7291";
// 				reg = <0x2f>;
// 			};

			eeprom@50 {
				compatible = "at24,24c02";
				reg = <0x50>;
			};
		};
	};

Here is the related part of the overall dts compiled by Petalinux (could not paste it all as it'is too long):

i2c@ff030000 {
			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
			status = "okay";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x12 0x4>;
			reg = <0x0 0xff030000 0x0 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			power-domains = <0xc 0x26>;
			clocks = <0x3 0x3e>;
			clock-frequency = <0x61a80>;
			pinctrl-names = "gpio";
			pinctrl-0 = <0x16>;
			scl-gpios = <0x12 0x20 0x0>;
			sda-gpios = <0x12 0x21 0x0>;

			i2c-mux@70 {
				compatible = "nxp,pca9548";
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				reg = <0x70>;

				i2c@0 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x0>;

					adau1761@3b {
						compatible = "adi,adau1761";
						reg = <0x3b>;
						clocks = <0x17>;
						clock-names = "mclk";
						#sound-dai-cells = <0x0>;
						phandle = <0x3d>;
					};
				};

				i2c@1 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x1>;

					ad9545@4A {
						compatible = "adi,ad9545";
						reg = <0x4a>;
						#address-cells = <0x1>;
						#size-cells = <0x0>;
						adi,ref-crystal;
						adi,ref-frequency-hz = <0x2ee0000>;
						#clock-cells = <0x2>;
						assigned-clocks = <0x18 0x2 0x0 0x18 0x1 0x1 0x18 0x0 0x6 0x18 0x0 0x8>;
						assigned-clock-rates = <0x2710 0x6fc23ac0 0x9502f90 0x9502f90>;
						assigned-clock-phases = <0x0 0x0 0x0 0xb4>;
						phandle = <0x18>;

						aux-nco-clk@0 {
							reg = <0x0>;
							adi,freq-lock-threshold-ps = <0xf42400>;
							adi,phase-lock-threshold-ps = <0xf42400>;
						};

						pll-clk@1 {
							reg = <0x1>;
							adi,pll-source = <0x4>;
							adi,pll-loop-bandwidth-hz = <0xc8>;
						};

						output-clk@6 {
							reg = <0x6>;
							adi,output-mode = <0x2>;
							adi,current-source-microamp = <0x3a98>;
						};

						output-clk@8 {
							reg = <0x8>;
							adi,output-mode = <0x2>;
							adi,current-source-microamp = <0x3a98>;
						};
					};
				};

				i2c@2 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x2>;
				};

				i2c@3 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x3>;

					eeprom@50 {
						compatible = "at24,24c02";
						reg = <0x50>;
					};
				};

				i2c@4 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x4>;

					eeprom@50 {
						compatible = "at24,24c02";
						reg = <0x50>;
					};
				};

				i2c@5 {
					#address-cells = <0x1>;
					#size-cells = <0x0>;
					reg = <0x5>;

					eeprom@50 {
						compatible = "at24,24c02";
						reg = <0x50>;
					};
				};
			};

0 ADIApproved

on Jan 13, 2021 5:24 AM in reply to Sermed
Hi Sermed,

The device tree looks good. The problem is that the auxiliary NCO clock is not registering in the common clock framework.

I fixed this here: https://github.com/analogdevicesinc/linux/pull/1371/files

As a bypass, just to check if this is the problem, you could try changing the aux-nco-clk@AD9545_NCO0 to:

                aux-nco-clk@AD9545_NCO0 {
                    reg = <AD9545_NCO0>;

                    adi,nco-freq-hz = <10000>;
                    adi,freq-lock-threshold-ps = <16000000>;
                    adi,phase-lock-threshold-ps = <16000000>;
               }

Thanks,

Alexandru Tachici
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 Sermed

on Jan 13, 2021 6:45 AM in reply to ADIApproved

Hi,

Actually this made a change in the clock summary output:

                                 enable  prepare  protect                                duty
   clock                          count    count    count        rate   accuracy phase  cycle
---------------------------------------------------------------------------------------------
 spi1.1-tx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi1.1-obs_sampl_clk                 0        0        0   245760000          0     0  50000
 spi1.1-rx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi1.0-tx_sampl_clk                  1        1        0   245760000          0     0  50000
 spi1.0-obs_sampl_clk                 1        1        0   245760000          0     0  50000
 spi1.0-rx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi2.1-tx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi2.1-obs_sampl_clk                 0        0        0   245760000          0     0  50000
 spi2.1-rx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi2.0-tx_sampl_clk                  0        0        0   245760000          0     0  50000
 spi2.0-obs_sampl_clk                 0        0        0   245760000          0     0  50000
 spi2.0-rx_sampl_clk                  0        0        0   245760000          0     0  50000
 AUX_NCO0                             0        0        0       10000          0     0  50000
    PLL1                              0        0        0  1875000000          0     0  50000
       Q1B-div                        0        0        0   156250000          0     0  50000
       Q1A-div                        0        0        0   156250000          0     0  50000
 hmc7044_e_out11_REFCLK_SFP           0        0        0   122880000          0     0  50000
 hmc7044_e_out6_SYNC_OUT2             0        0        0      768000          0     0  50000
 hmc7044_e_out5_SYNC_OUT1             0        0        0      768000          0     0  50000
 hmc7044_e_out2_REFCLK_OUT2           0        0        0    30720000          0     0  50000
 hmc7044_e_out0_REFCLK_OUT0           0        0        0    30720000          0     0  50000
 hmc7044_c_out11_REFCLK_SFP           0        0        0   122880000          0     0  50000
 hmc7044_c_out10_REFCLK_QSFP          0        0        0    30720000          0     0  50000
 hmc7044_c_out9_REFCLK_OUT4           5        5        0    30720000          0     0  50000
    hmc7044_fmc_out9_FPGA_SYSREF_RX_CD       0        0        0      768000          0     0  50000
    hmc7044_fmc_out8_FPGA_SYSREF_TX_OBS_CD       0        0        0      768000          0     0  50000
    hmc7044_fmc_out7_CORE_CLK_RX_CD       0        0        0   245760000          0     0  50000
    hmc7044_fmc_out6_CORE_CLK_TX_OBS_CD       0        0        0   122880000          0     0  50000
    hmc7044_fmc_out5_JESD_REFCLK_RX_CD       2        2        0   245760000          0     0  50000
    hmc7044_fmc_out4_JESD_REFCLK_TX_OBS_CD       4        4        0   245760000          0     0  50000
    hmc7044_fmc_out3_DEV_SYSREF_D       0        0        0     3840000          0     0  50000
    hmc7044_fmc_out2_DEV_REFCLK_D       1        1        0   245760000          0     0  50000
    hmc7044_fmc_out1_DEV_SYSREF_C       0        0        0     3840000          0     0  50000
    hmc7044_fmc_out0_DEV_REFCLK_C       1        1        0   245760000          0     0  50000
 hmc7044_c_out8_REFCLK_OUT3           0        0        0    30720000          0     0  50000
 hmc7044_c_out6_SYNC_OUT2             0        0        0     3840000          0     0  50000
 hmc7044_c_out5_SYNC_OUT1             0        0        0     3840000          0     0  50000
 hmc7044_c_out2_REFCLK_OUT2           7        7        2    30720000          0     0  50000
    hmc7044_out9_FPGA_SYSREF_RX_AB       0        0        0     3840000          0     0  50000
    hmc7044_out8_FPGA_SYSREF_TX_OBS_AB       0        0        0     3840000          0     0  50000
    hmc7044_out7_CORE_CLK_RX_AB       1        1        0   245760000          0     0  50000
    hmc7044_out6_CORE_CLK_TX_OBS_AB       2        2        0   122880000          0     0  50000
    hmc7044_out5_JESD_REFCLK_RX_AB       2        2        1   245760000          0     0  50000
       rx_out_clk                     0        0        0   245760000          0     0  50000
       rx_gt_clk                      1        1        1     9830400          0     0  50000
    hmc7044_out4_JESD_REFCLK_TX_OBS_AB       4        4        2   245760000          0     0  50000
       tx_out_clk                     0        0        0   245760000          0     0  50000
       tx_gt_clk                      1        1        1     4915200          0     0  50000
       rx_os_out_clk                  0        0        0   245760000          0     0  50000
       rx_os_gt_clk                   1        1        1     4915200          0     0  50000
    hmc7044_out3_DEV_SYSREF_B         0        0        0     3840000          0     0  50000
    hmc7044_out2_DEV_REFCLK_B         1        1        0   245760000          0     0  50000
    hmc7044_out1_DEV_SYSREF_A         0        0        0     3840000          0     0  50000
    hmc7044_out0_DEV_REFCLK_A         1        1        0   245760000          0     0  50000
 hmc7044_c_out0_REFCLK_OUT0           0        0        0    30720000          0     0  50000
 audio_clock                          1        1        0    12288000          0     0  50000
 dp_aclk                              1        1        0   100000000        100     0  50000
 aux_ref_clk                          0        0        0    27000000          0     0  50000
 gt_crx_ref_clk                       0        0        0   108000000          0     0  50000
 pss_alt_ref_clk                      0        0        0           0          0     0  50000
 video_clk                            0        0        0    27000000          0     0  50000
 pss_ref_clk                          3        3        3    33333333          0     0  50000
    vpll_post_src                     0        0        0    33333333          0     0  50000
    vpll_pre_src                      0        0        0    33333333          0     0  50000
       vpll_int                       0        0        0  2999999970          0     0  50000
          vpll_half                   0        0        0  1499999985          0     0  50000
             vpll_int_mux             0        0        0  1499999985          0     0  50000
                vpll                  0        0        0  1499999985          0     0  50000
                   dp_video_ref_mux       0        0        0  1499999985          0     0  50000
                      dp_video_ref_div1       0        0        0   299999997          0     0  50000
                         dp_video_ref_div2       0        0        0   299999997          0     0  50000
                            dp_video_ref       0        0        0   299999997          0     0  50000
                   vpll_to_lpd        0        0        0   499999995          0     0  50000
    dpll_post_src                     0        0        0    33333333          0     0  50000
    dpll_pre_src                      1        1        1    33333333          0     0  50000
       dpll_int                       1        1        1  2399999976          0     0  50000
          dpll_half                   1        1        1  1199999988          0     0  50000
             dpll_int_mux             1        1        1  1199999988          0     0  50000
                dpll                  1        1        1  1199999988          0     0  50000
                   gpu_ref_mux        0        0        0  1199999988          0     0  50000
                      gpu_ref_div1       0        0        0   599999994          0     0  50000
                         gpu_ref       0        0        0   599999994          0     0  50000
                            gpu_pp1_ref       0        0        0   599999994          0     0  50000
                            gpu_pp0_ref       0        0        0   599999994          0     0  50000
                   pcie_ref_mux       0        0        0  1199999988          0     0  50000
                      pcie_ref_div1       0        0        0    99999999          0     0  50000
                         pcie_ref       0        0        0    99999999          0     0  50000
                   sata_ref_mux       0        0        0  1199999988          0     0  50000
                      sata_ref_div1       0        0        0    99999999          0     0  50000
                         sata_ref       0        0        0    99999999          0     0  50000
                   dpdma_ref_mux       1        1        1  1199999988          0     0  50000
                      dpdma_ref_div1       1        1        1   599999994          0     0  50000
                         dpdma_ref       1        1        1   599999994          0     0  50000
                   gdma_ref_mux       0        0        0  1199999988          0     0  50000
                      gdma_ref_div1       0        0        0   599999994          0     0  50000
                         gdma_ref       0        0        0   599999994          0     0  50000
                   dp_stc_ref_mux       0        0        0  1199999988          0     0  50000
                      dp_stc_ref_div1       0        0        0    26666667          0     0  50000
                         dp_stc_ref_div2       0        0        0    26666667          0     0  50000
                            dp_stc_ref       0        0        0    26666667          0     0  50000
                   dp_audio_ref_mux       0        0        0  1199999988          0     0  50000
                      dp_audio_ref_div1       0        0        0    22641510          0     0  50000
                         dp_audio_ref_div2       0        0        0    22641510          0     0  50000
                            dp_audio_ref       0        0        0    22641510          0     0  50000
                   dpll_to_lpd        0        0        0   399999996          0     0  50000
    apll_post_src                     0        0        0    33333333          0     0  50000
    apll_pre_src                      0        0        0    33333333          0     0  50000
       apll_int                       0        0        0  2666666640          0     0  50000
          apll_half                   0        0        0  1333333320          0     0  50000
             apll_int_mux             0        0        0  1333333320          0     0  50000
                apll                  0        0        0  1333333320          0     0  50000
                   acpu_mux           0        0        0  1333333320          0     0  50000
                      acpu            0        0        0  1333333320          0     0  50000
    rpll_post_src                     0        0        0    33333333          0     0  50000
    rpll_pre_src                      1        1        1    33333333          0     0  50000
       rpll_int                       1        1        1  1999999980          0     0  50000
          rpll_half                   1        1        1   999999990          0     0  50000
             rpll_int_mux             1        1        1   999999990          0     0  50000
                rpll                  1        1        1   999999990          0     0  50000
                   adma_ref_mux       0        0        0   999999990          0     0  50000
                      adma_ref_div1       0        0        0   499999995          0     0  50000
                         adma_ref       0        0        0   499999995          0     0  50000
                   spi1_ref_mux       0        0        0   999999990          0     0  50000
                      spi1_ref_div1       0        0        0   199999998          0     0  50000
                         spi1_ref_div2       0        0        0   199999998          0     0  50000
                            spi1_ref       0        0        0   199999998          0     0  50000
                   spi0_ref_mux       0        0        0   999999990          0     0  50000
                      spi0_ref_div1       0        0        0    99999999          0     0  50000
                         spi0_ref_div2       0        0        0    99999999          0     0  50000
                            spi0_ref       0        0        0    99999999          0     0  50000
                   sdio1_ref_mux       1        1        1   999999990          0     0  50000
                      sdio1_ref_div1       1        1        1   199999998          0     0  50000
                         sdio1_ref_div2       1        1        1   199999998          0     0  50000
                            sdio1_ref       1        1        1   199999998          0     0  50000
                   rpll_to_fpd        0        0        0   499999995          0     0  50000
    iopll_post_src                    0        0        0    33333333          0     0  50000
    iopll_pre_src                     1        1        1    33333333          0     0  50000
       iopll_int                      1        1        1  2999999970          0     0  50000
          iopll_half                  1        1        1  1499999985          0     0  50000
             iopll_int_mux            1        1        1  1499999985          0     0  50000
                iopll                13       15        8  1499999985          0     0  50000
                   gem3_ref_ung_mux       1        1        0  1499999985          0     0  50000
                      gem3_ref_ung_div1       1        1        0  1499999985          0     0  50000
                         gem3_ref_ung       1        1        0   124999999          0     0  50000
                            gem3_ref       2        2        0   124999999          0     0  50000
                               gem3_tx       1        1        0   124999999          0     0  50000
                   gem2_ref_ung_mux       0        0        0  1499999985          0     0  50000
                      gem2_ref_ung_div1       0        0        0    62500000          0     0  50000
                         gem2_ref_ung       0        0        0    62500000          0     0  50000
                            gem2_ref       0        0        0    62500000          0     0  50000
                               gem2_tx       0        0        0    62500000          0     0  50000
                   gem1_ref_ung_mux       0        0        0  1499999985          0     0  50000
                      gem1_ref_ung_div1       0        0        0    62500000          0     0  50000
                         gem1_ref_ung       0        0        0    62500000          0     0  50000
                            gem1_ref       0        0        0    62500000          0     0  50000
                               gem1_tx       0        0        0    62500000          0     0  50000
                   gem0_ref_ung_mux       0        0        0  1499999985          0     0  50000
                      gem0_ref_ung_div1       0        0        0   124999999          0     0  50000
                         gem0_ref_ung       0        0        0   124999999          0     0  50000
                   pl3_ref_mux        1        1        0  1499999985          0     0  50000
                      pl3_ref_div1       1        1        0    46875000          0     0  50000
                         pl3_ref_div2       1        1        0     9375000          0     0  50000
                            pl3_ref       1        1        0     9375000          0     0  50000
                   pl2_ref_mux        1        1        0  1499999985          0     0  50000
                      pl2_ref_div1       1        1        0    36585366          0     0  50000
                         pl2_ref_div2       1        1        0    12195122          0     0  50000
                            pl2_ref       7        7        0    12195122          0     0  50000
                   pl1_ref_mux        1        1        0  1499999985          0     0  50000
                      pl1_ref_div1       1        1        0    50000000          0     0  50000
                         pl1_ref_div2       1        1        0    50000000          0     0  50000
                            pl1_ref       1        1        0    50000000          0     0  50000
                   pl0_ref_mux        1        1        0  1499999985          0     0  50000
                      pl0_ref_div1       1        1        0    99999999          0     0  50000
                         pl0_ref_div2       1        1        0    99999999          0     0  50000
                            pl0_ref       4        4        0    99999999          0     0  50000
                   ams_ref_mux        1        1        1  1499999985          0     0  50000
                      ams_ref_div1       1        1        1    50000000          0     0  50000
                         ams_ref_div2       1        1        1    50000000          0     0  50000
                            ams_ref       1        1        1    50000000          0     0  50000
                   can1_ref_mux       0        0        0  1499999985          0     0  50000
                      can1_ref_div1       0        0        0    46875000          0     0  50000
                         can1_ref_div2       0        0        0    46875000          0     0  50000
                            can1_ref       0        0        0    46875000          0     0  50000
                               can1       0        0        0    46875000          0     0  50000
                   can0_ref_mux       0        0        0  1499999985          0     0  50000
                      can0_ref_div1       0        0        0    46875000          0     0  50000
                         can0_ref_div2       0        0        0    46875000          0     0  50000
                            can0_ref       0        0        0    46875000          0     0  50000
                               can0       0        0        0    46875000          0     0  50000
                   i2c1_ref_mux       1        1        1  1499999985          0     0  50000
                      i2c1_ref_div1       1        1        1    99999999          0     0  50000
                         i2c1_ref_div2       1        1        1    99999999          0     0  50000
                            i2c1_ref       1        1        1    99999999          0     0  50000
                   i2c0_ref_mux       0        1        1  1499999985          0     0  50000
                      i2c0_ref_div1       0        1        1    99999999          0     0  50000
                         i2c0_ref_div2       0        1        1    99999999          0     0  50000
                            i2c0_ref       0        1        1    99999999          0     0  50000
                   nand_ref_mux       0        0        0  1499999985          0     0  50000
                      nand_ref_div1       0        0        0    46875000          0     0  50000
                         nand_ref_div2       0        0        0     9375000          0     0  50000
                            nand_ref       0        0        0     9375000          0     0  50000
                   uart1_ref_mux       1        1        1  1499999985          0     0  50000
                      uart1_ref_div1       1        1        1    99999999          0     0  50000
                         uart1_ref_div2       1        1        1    99999999          0     0  50000
                            uart1_ref       1        1        1    99999999          0     0  50000
                   uart0_ref_mux       0        0        0  1499999985          0     0  50000
                      uart0_ref_div1       0        0        0    62500000          0     0  50000
                         uart0_ref_div2       0        0        0    62500000          0     0  50000
                            uart0_ref       0        0        0    62500000          0     0  50000
                   sdio0_ref_mux       0        0        0  1499999985          0     0  50000
                      sdio0_ref_div1       0        0        0    99999999          0     0  50000
                         sdio0_ref_div2       0        0        0    99999999          0     0  50000
                            sdio0_ref       0        0        0    99999999          0     0  50000
                   qspi_ref_mux       0        1        1  1499999985          0     0  50000
                      qspi_ref_div1       0        1        1   299999997          0     0  50000
                         qspi_ref_div2       0        1        1   299999997          0     0  50000
                            qspi_ref       0        1        1   299999997          0     0  50000
                   gem_tsu_ref_mux       1        1        1  1499999985          0     0  50000
                      gem_tsu_ref_div1       1        1        1   249999998          0     0  50000
                         gem_tsu_ref_div2       1        1        1   249999998          0     0  50000
                            gem_tsu_ref       1        1        1   249999998          0     0  50000
                               gem_tsu       2        2        0   249999998          0     0  50000
                   usb3_dual_ref_mux       1        1        1  1499999985          0     0  50000
                      usb3_dual_ref_div1       1        1        1    60000000          0     0  50000
                         usb3_dual_ref_div2       1        1        1    20000000          0     0  50000
                            usb3_dual_ref       1        1        1    20000000          0     0  50000
                   usb1_bus_ref_mux       0        0        0  1499999985          0     0  50000
                      usb1_bus_ref_div1       0        0        0   124999999          0     0  50000
                         usb1_bus_ref_div2       0        0        0   124999999          0     0  50000
                            usb1_bus_ref       0        0        0   124999999          0     0  50000
                   usb0_bus_ref_mux       1        1        1  1499999985          0     0  50000
                      usb0_bus_ref_div1       1        1        1   249999998          0     0  50000
                         usb0_bus_ref_div2       1        1        1   249999998          0     0  50000
                            usb0_bus_ref       1        1        1   249999998          0     0  50000
                   lpd_lsbus_mux       1        1        0  1499999985          0     0  50000
                      lpd_lsbus_div1       1        1        0    99999999          0     0  50000
                         lpd_lsbus       7        8        0    99999999          0     0  50000
                            lpd_wdt       0        0        0    99999999          0     0  50000
                   iopll_to_fpd       1        1        0   499999995          0     0  50000
                      topsw_lsbus_mux       1        1        0   499999995          0     0  50000
                         topsw_lsbus_div1       1        1        0    99999999          0     0  50000
                            topsw_lsbus       3        3        0    99999999          0     0  50000
                               fpd_wdt       1        1        0    99999999          0     0  50000
 gem0_ref                             2        2        0           0          0     0  50000
    gem0_tx                           1        1        0           0          0     0  50000
 can1_mio                             0        0        0           0          0     0  50000
 can0_mio                             0        0        0           0          0     0  50000
 gem3_rx                              1        1        0           0          0     0  50000
 gem2_rx                              0        0        0           0          0     0  50000
 gem1_rx                              0        0        0           0          0     0  50000
 gem0_rx                              1        1        0           0          0     0  50000

However, 1G core still does not output any clock. Is it possible that we did not set the output clocks to be differential in the device-tree? We set output to DRIVER_MODE_DUAL_DIV. Could changing this to DRIVER_MODE_SINGLE_DIV_DIFF help?

If this is the case, should we add AD9545_Q1AA as output clock to the system.

0 ADIApproved

on Jan 13, 2021 7:11 AM in reply to Sermed
Hi Sermed,

Yes, the correct configuration for adrv2crr-fmc (looking at the schematics) is to set the output driver mode to DRIVER_MODE_SINGLE_DIV_DIF, sink 15 mA current:

output-clk@AD9545_Q1A {
reg = <AD9545_Q1A>;
adi,output-mode = <DRIVER_MODE_DUAL_DIV_DIF>;
adi,current-source-microamp = <15000>;
}
Cancel
Up 0 Down

Reply

Verify Answer

Cancel

0 Sermed

on Jan 14, 2021 7:21 AM in reply to ADIApproved

Couple of dt configurations I tried, but failed:

		i2c@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>; 

            ad9545_clock: ad9545@4A {
                compatible = "adi,ad9545";
                reg = <0x4A>;

                #address-cells = <1>;
                #size-cells = <0>;

                adi,ref-crystal;
                adi,ref-frequency-hz = <49152000>;

                #clock-cells = <2>;

                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                assigned-clock-phases = <0>, <0>, <0>, <0>;

                aux-nco-clk@AD9545_NCO0 {
                    reg = <AD9545_NCO0>;
                    adi,freq-lock-threshold-ps = <16000000>;
                    adi,phase-lock-threshold-ps = <16000000>;
                };

                ad9545_apll1: pll-clk@AD9545_PLL1 {
                  reg = <AD9545_PLL1>;
                  adi,pll-source = <4>;
                  adi,pll-loop-bandwidth-hz = <200>;
                };

                output-clk@AD9545_Q1A {
                  reg = <AD9545_Q1A>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                  adi,current-source-microamp = <15000>;
                };

                output-clk@AD9545_Q1B {
                  reg = <AD9545_Q1B>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                  adi,current-source-microamp = <15000>;
                };

            };

			/* 4A */

		};

		i2c@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>; 

            ad9545_clock: ad9545@4A {
                compatible = "adi,ad9545";
                reg = <0x4A>;

                #address-cells = <1>;
                #size-cells = <0>;

                adi,ref-crystal;
                adi,ref-frequency-hz = <49152000>;

                #clock-cells = <2>;

                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                assigned-clock-phases = <0>, <0>, <0>, <180>;

                aux-nco-clk@AD9545_NCO0 {
                    reg = <AD9545_NCO0>;
                    adi,freq-lock-threshold-ps = <16000000>;
                    adi,phase-lock-threshold-ps = <16000000>;
                };

                ad9545_apll1: pll-clk@AD9545_PLL1 {
                  reg = <AD9545_PLL1>;
                  adi,pll-source = <4>;
                  adi,pll-loop-bandwidth-hz = <200>;
                };

                output-clk@AD9545_Q1A {
                  reg = <AD9545_Q1A>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                  adi,current-source-microamp = <15000>;
                };

                output-clk@AD9545_Q1AA {
                  reg = <AD9545_Q1AA>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                  adi,current-source-microamp = <15000>;
                };
            };

			/* 4A */

		};

		i2c@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>; 

            ad9545_clock: ad9545@4A {
                compatible = "adi,ad9545";
                reg = <0x4A>;

                #address-cells = <1>;
                #size-cells = <0>;

                adi,ref-crystal;
                adi,ref-frequency-hz = <49152000>;

                #clock-cells = <2>;

                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1AA>;
                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
                assigned-clock-phases = <0>, <0>, <0>, <180>;

                aux-nco-clk@AD9545_NCO0 {
                    reg = <AD9545_NCO0>;
                    adi,freq-lock-threshold-ps = <16000000>;
                    adi,phase-lock-threshold-ps = <16000000>;
                };

                ad9545_apll1: pll-clk@AD9545_PLL1 {
                  reg = <AD9545_PLL1>;
                  adi,pll-source = <4>;
                  adi,pll-loop-bandwidth-hz = <200>;
                };

                output-clk@AD9545_Q1A {
                  reg = <AD9545_Q1A>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                  adi,current-source-microamp = <15000>;
                };

                output-clk@AD9545_Q1AA {
                  reg = <AD9545_Q1AA>;
                  adi,output-mode = <DRIVER_MODE_SINGLE_DIV>;
                  adi,current-source-microamp = <15000>;
                };

            };

			/* 4A */

		};

Electronic Design Services - PartnerZone

Products Mentioned

adrv9009-zu11eg-adrv2crr SFP ethernet clock