adrv9009-zu11eg-adrv2crr SFP ethernet clock

Hi,

I am trying to add ethernet to PL side of SOM system with carrier board. Both 10G or 1G Xilinx ethernet subsystems need 125MHz or 156.25MHz differential clock from FPGA pins. However, I am not sure where to get these clocks from. There are clocks in the carrier board like SFP_REFCLK, ETH_REFCLK1. SFP_REFCLK is generated from HMC7044. In the reference design of this system, HMC7044 pll2 output frequency is set as 2949.12MHz which can be divided by even numbers in the range 0-4096 to output a clock at the SFP_REFCLK as shown in https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts . However, with this configuration, we cannot obtain 156.25MHz or 125MHz with any division. I could not find information regarding ETH_REFCLK1 which is the output of ad9545. I could not find dt-binding about this chip so that I can get my desired clock rate. Is it possible that this ETH_REFCLK1 in the carrier board provides 125 MHz default frequency?

Wrapping up everything, how can I get this 125MHz or 156.25MHz clock while using adrv9009-zu11eg reference design provided by ADI?

Thanks in advance,

Sermed

  • 0
    •  Analog Employees 
    on Dec 29, 2020 10:00 AM 2 months ago

    Hi Sermed,

    We have a Linux driver for ad9545 done. It is used to generate the above frequencies on this board. We will test the SFP and come back with an answer.

    Thanks,

    Alexandru

  • Hi,

    I have seen that you added ad9545 driver to the linux-master branch. Looking at the schematics of the adrv2crr board, I added the below device tree to system-user.dtsi in petalinux. However, I could not obtain any clock from the ETH_REFCLK1 pin. What is wrong or missing in this device tree part?

    /include/ "system-conf.dtsi"
    / {
    };
    
    
    /*
     * I2C1
     */
    #include <dt-bindings/clock/ad9545.h>
    
    &i2c1 {
    	status = "okay";
    	clock-frequency = <400000>;
    	pinctrl-names = "gpio";
    	pinctrl-0 = <&pinctrl_i2c1_gpio>;
    	scl-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>;
    	sda-gpios = <&gpio 33 GPIO_ACTIVE_HIGH>;
    
    	i2c-mux@70 { /* u19 */
    		compatible = "nxp,pca9548"; /* TCA9548 */
    		#address-cells = <1>;
    		#size-cells = <0>;
    		reg = <0x70>;
    
    		i2c@0 { /* Audio ADAU1761 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    
    			adau1761: adau1761@3b {
    				compatible = "adi,adau1761";
    				reg = <0x3b>;
    
    				clocks = <&audio_clock>;
    				clock-names = "mclk";
    
    				#sound-dai-cells = <0>;
    			};
    
    		};
    		i2c@1 {
                #address-cells = <1>;
                #size-cells = <0>;
                ad9545_clock: ad9545@4A {
                        compatible = "adi,ad9545";
                        reg = <0x4A>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                        adi,ref-crystal;
                        adi,ref-frequency-hz = <49152000>;
                        #clock-cells = <2>;
                        clock-output-names = "OUT1B-P", "OUT1B-N";
                        ad9545_apll1: pll-clk@1 {
                            reg = <1>;
                            adi,pll-source = <4>;
                            adi,pll-loop-bandwidth-hz = <200>;
                        };
                        aux_nco0: aux-nco-clk@0 {
                        	reg = <0>;
                        	adi,freq-lock-threshold-ps = <100000>;
                        	adi,phase-lock-threshold-ps = <100000>;
                        };
                        output-clk@8 {
                            reg = <8>;
                            adi,init-freq-hz = <156250000>;
                            adi,init-phase = <0>;
                            adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                            adi,current-source-microamp = <15000>;
                        };
                        output-clk@9 {
                            reg = <9>;
                            adi,init-freq-hz = <156250000>;
                            adi,init-phase = <180>;
                            adi,output-mode = <DRIVER_MODE_SINGLE_DIV_DIF>;
                            adi,current-source-microamp = <15000>;
                        };
                };
        };
    
    			/* 4A */
    
    		};
    		i2c@2 { /* PTN5150 */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <2>;
    
    			/* 1D */
    
    		};
    		i2c@3 { /* QSFP */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <3>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    		i2c@4 { /* SFP+ */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <4>;
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    
    		};
    		i2c@5 { /* FMC HPC */
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <5>;
    
    // 			ad7291@2f {
    // 				compatible = "adi,ad7291";
    // 				reg = <0x2f>;
    // 			};
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = <0x50>;
    			};
    		};
    	};
    	
    

    Thanks,

    Sermed

  • 0
    •  Analog Employees 
    on Jan 11, 2021 9:36 AM 1 month ago in reply to Sermed

    Hi Sermed,

    Can you replace the ad9545 node with this one:

    ad9545_clock: ad9545@4A {
        compatible = "adi,ad9545";
        reg = <0x4A>;

        #address-cells = <1>;
        #size-cells = <0>;

        adi,ref-crystal;
        adi,ref-frequency-hz = <49152000>;

        #clock-cells = <2>;
        assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
        assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
        assigned-clock-phases = <0>, <0>, <0>, <180>;

        aux-nco-clk@AD9545_NCO0 {
            reg = <AD9545_NCO0>;
            adi,freq-lock-threshold-ps = <16000000>;
            adi,phase-lock-threshold-ps = <16000000>;
        };

        ad9545_apll1: pll-clk@AD9545_PLL1 {
          reg = <AD9545_PLL1>;
          adi,pll-source = <4>;
          adi,pll-loop-bandwidth-hz = <200>;
        };

        output-clk@AD9545_Q1A {
          reg = <AD9545_Q1A>;
          adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
          adi,current-source-microamp = <15000>;
        };

        output-clk@AD9545_Q1B {
          reg = <AD9545_Q1B>;
          adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
          adi,current-source-microamp = <15000>;
        };
    };

    Thanks,

    Alexandru Tachici

  • Hi,

    I have tried what you suggested. I fixed couple of my mistakes but still could not obtain the clock. Not sure if I'm making a mistake. I changed the fpga pin from  ETH_REFCLK1 to ETH_REFCLK2 as SFP is in the corresponding transceiver quad. In this device tree, both OUT1A and OUT1B is programmed as 156.25MHz, so there should not be a problem. Did you have a chance to try this?

  • 0
    •  Analog Employees 
    on Jan 12, 2021 3:27 PM 1 month ago in reply to Sermed

    Hi Sermed,

    I have updated today the driver in the Linux main branch: https://github.com/analogdevicesinc/linux/pull/1372. Please try running the latest Linux image and if nothing works run a "dmesg" and paste ithe output here. I have tested this on the eval-board and there should be no problem. I will try a test on the same board as yours too.