ADRV9009 connected to MPSoC Xilinx FPGA

1. What is the recommended way to leverage the ADRV9009 HDL Reference Design example for a custom board that uses Xilinx Zynq Ultrascale+ FPGA to communicate with the ADRV9009?
    a. How should the drivers needed for the ADI IPs and libiio be integrated into Petalinux?
    b. Can someone build a Petalinux OS using the Vivado generated .hdf file from a modified version of the HDL example.

2. Is there a resource on how to create a device tree file for a generic platform interfacing with the ADRV9009?
    a. Is ADI provided yocto layer (meta-adi) a possibility for an OS solution? It seems tailored for the example designs. Can it be modified to fit a custom platform?
    b. For example we use HMC7044 ultra low phase noise clock chip instead of ad9528 that is used on the ADRV9009 evaluation board [1].

3. Is the no-os software portable to run on a linux kernel, and does ADI see any issues if we try to run on the no-os software on a linux kernel?



changed wording for clarification
[edited by: charlyelkhoury at 1:02 PM (GMT 0) on 14 Aug 2020]