LTC2983 & Device Tree (ZynqMP Ultarscale+ ADRV9009-ZU11EG)

Hi,

How are you exactly defining your devicetree? You need to define the ltc2983 properties under the spi controller node where it is attached. Note that on this example, spi0 is just meant to be an example. It does not mean that you have to define it like that. On which platform do you want to use ltc2983?

- Nuno Sá

Where to define the ltc2983 properties is my question. I'm using the adrv9009, in the device tree for this would the ltc2983 properties just need to be defined under the fhm_spi attribute?  

It all depends in which controller is your device attached (physically). AFAIK, in ultrascale you have spi0 and spi1 so it should be one of them. Moreover, you need to set the reg property to the correct value. This corresponds to the spi CS pin...

- Nuno Sá

can the CS pin be any gpio pin from the ultrascale or does it have to be from a specific range?

-Ryne

There is a auxiliary SPI (spi0) interface routed to the PMOD connector on the ZU11EG carrier.

https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v#L260

I assume you don't use an external HMC7044 board in your setup.

So you could reuse this spi0 cs4 node:

https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts#L524

if you use "cs-gpios" property you could use any system GPIO as CS.

Please see here: https://github.com/analogdevicesinc/linux/blob/master/Documentation/devicetree/bindings/spi/spi-bus.txt

-Michael

I'm a little confused on how the chip select pins are mapped in the device tree. For the external HMC7044 it's reg 4 and for the hmc on the carrier it's reg 3. Is there documentation somewhere that shows how these register numbers are assigned to pins?

Hello,

As in Michael's response, in HDL we assign the SPI CS to specific pins: https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v#L256-L260.

reg 4 is used for the expander, at which we connect the external HMC7044 evaluation board. If you want to connect someting else, you can connect it physically to the board and replace: https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-reva-adrv2crr-fmc-reva.dts#L519 with your own peripheral.

Regards,

Adrian 

Hi Adrian,

I'm working with Ryne on this program.  Are there any references to a Device Tree file for the ADRV9009-ZU11EG or similar Zynq system that uses two SPI interfaces?  The ADRV9009-ZU11EG only uses the SPI0 interface. We would like to use the SPI1 interface if possible and may avoid having to re-build the HDL code (Boot.bin file).  I see in the hardware schematics for the RFSOM that the SPI1 interface is mapped to P2.D19, P2.D20, ..., P2.D24 and associated with Processing System(PS) MIO19,MIO20,MIO21,MIO22,MIO23 and MIO18. 

See this snippet of the RFSOM ADRV9009-ZU11EG schematic ... 

Hi Adrian,

I'm working with Ryne on this program.  Are there any references to a Device Tree file for the ADRV9009-ZU11EG or similar Zynq system that uses two SPI interfaces?  The ADRV9009-ZU11EG only uses the SPI0 interface. We would like to use the SPI1 interface if possible and may avoid having to re-build the HDL code (Boot.bin file).  I see in the hardware schematics for the RFSOM that the SPI1 interface is mapped to P2.D19, P2.D20, ..., P2.D24 and associated with Processing System(PS) MIO19,MIO20,MIO21,MIO22,MIO23 and MIO18. 

See this snippet of the RFSOM ADRV9009-ZU11EG schematic ... 

Hello Nathan,

The latest default reference design has GPIOs at P18-P24. You'll need to rebuild the HDL and enable the SPI1 and select MIO 18...23. 

We have for example ADRV9009ZU11EG+FMCOMMS8 where we enabled SPI1 to drive the FMC part of the design:

https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v#L799

In the above case we're using EMIO and PL pins for the SPI1.

The devicetree is modified accordingly: https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8.dts#L84 

In our designs, we typically use EMIO + PL and less MIO to drive peripherals.

Regards,

Adrian