ADRV9009-ZU11EG SOM: External VCO for Clock Distribution


I would like to setup the ADRV9009-ZU11EG SOM with an external VCO at 2.8GHz in order to get data rates of 200MHz for the Tx and Rx paths. This should be possible if I setup the HMC7044 to function as the HMC7043, and prefix the channel divider values based on my planned external VCO frequency. To try this, I made a couple changes to the HMC7044 entries in the devicetree and I fed a 2.8GHz external VCO signal into the Ref_P SMA on the Carrier. I am using the 2019_R1 Linux branch and Rev. A SOM.

From the devicetree binding documentation for the HMC7044: "adi,clkin1-vco-in-enable: CLKIN1 input is used for external VCO."

And from Table 14, Pg 30 of the HMC7044 datasheet: 

I tried adding the devicetree binding like so to the Carrier and SOM HMC7044 entries:

                adi,clkin1-vco-in-enable = <0x1>;

I didn't change anything else in the HMC7044 SOM or carrier devicetree entries, just added the above.

I used IIOScope to peek at the External VCO Enable bit (Reg 0x0005, bit 5) for a boot with the dtb files compiled from the dts/dtsi files with those added entries. Reg 0x0005 bit 5 was set to 1 (read 0x63 -> b0110_0011 from the Debug tab).

Despite showing up as enabled, I didn't notice any changes to the clocking tree the External VCO. I looked at the Eyescan application or "cat /sys/kernel/debug/clk/clk_summary?" output. At least, I expected the Eyescan application to show something with the JESD lanes was wrong, but everything appeared to be operating based on the VCXO, not on the external VCO.

To correctly get this setup to function, I know I need to change the output divide values for all the channels (for example, the Carrier HMC7044's OSCIN output divider value should be 1 to forward 2.8GHz to the SOM HMC7044's CLKIN1 input). Initially I only wanted to change 1 thing at a time.

Am I missing something obvious here? What can I do to get the clocking tree to work off of an external VCO?

Thank you,