from UG-1295:
When establishing a JESD204B link, it is desirable that the data arriving to the deframer does not arrive very close to an LMFC boundary. If this does happen, the deterministic latency can vary from system to system if the data on one system arrives just before an LMFC event, and arrives on another system just after an LMFC event. If this happens, there is an LMFC period difference in the latency between the systems. Furthermore, the architecture in the device does not support a very small delay through the FIFO, and data corruption occurs if the delay is too small. Therefore, it is important that the FIFO depth be checked after the link is established, and the link is adjusted to achieve a FIFO depth that is close to the medium depth. The FIFO depth can be checked in Register 0x15CE for Deframer 0 and in Register 0x161E for Deframer 1. Write to the appropriate register with a value of 0x80 to latch the current FIFO depth, and then read back. The readback value is reported as a signed, twos complement number located in Bits[D5:D0] of the register with valid values from +K2 to −(K/2 − 1). The value reported is the difference of the number of frames between the read and write pointers. If the value is found to be close to 0, for example, −2, −1, 0, +1, or +2, adjust the depth by varying the LMFC offset parameter on either end of the JESD204B link. Note that across multiple system starts, the depth in the FIFO can vary by one or two frames. This variation is expected because sampling phase uncertainties are absorbed by the FIFO to give deterministic latency. Consider this fact when optimizing the JESD204B link and performing multiple system starts to find the worst case depth values for a given LMFC offset.
