Hello All,
I am working on AD9371 board where i was getting sysref phase error when i saw log which is mentioned below:
ad9371 spi1.0: framerStatus (0xBE)
I was trying to implement subclass -1 for deterministic latency. For this, I added lmfcOffset value in ad9371 which is
mentioned below and these value are taken from ADRV9009 dtsi file.
adi,jesd204-rx-framer-lmfc-offset = 31
adi,jesd204-obs-framer-lmfc-offset = 31
adi,jesd204-deframer-lmfc-offset = 17
I did few changes which i have highlighted below:
axi_jesd204_rx.c
writel_relaxed(31<<2, jesd->base + JESD204_RX_REG_LINK_CONF2);
writel_relaxed(31<<2, jesd->base + JESD204_RX_REG_SYSREF_LMFC_OFFSET);
axi_jesd204_tx.c
writel_relaxed(17<<2, jesd->base + JESD204_TX_REG_SYSREF_LMFC_OFFSET);
I used SYSREF_LMFC_OFFSET to address power on variance and it was doing perfectly fine.
I've attached dtsi file to pursue some help from your end.
Regards,
/include/ "system-conf.dtsi"
/ {
chosen {
bootargs = "earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait uio_pdrv_genirq.of_id=generic-uio loglevel=7";
stdout-path = "serial0:115200n8";
};
};
/*
/ {
amba_pl@0 {
/delete-node/ axi_jesd204_rx@80010000;
/delete-node/ axi_jesd204_rx@8000c000;
/delete-node/ axi_jesd204_tx@80014000;
/delete-node/ axi_adxcvr@80080000 ;
/delete-node/ axi_adxcvr@80070000 ;
/delete-node/ axi_adxcvr@80090000 ;
/delete-node/ ad_ip_jesd204_tpl_adc@80024000;
/delete-node/ ad_ip_jesd204_tpl_adc@80030000;
/delete-node/ ad_ip_jesd204_tpl_dac@80028000;
};
};
*/
&dwc3_0 {
status = "okay";
dr_mode = "host";
maximum-speed = "super-speed";
snps,usb3_lpm_capable;
phy-names = "usb3-phy";
phys = <&lane2 0x4 0x0 0x3 0x18CBA80>;
};
&gem0 {
phy-handle = <&phy0>;
is-internal-pcspma;
phy-mode = "sgmii";
phy0: phy@0 {
/* compatible = "marvell, 88E1512"; */
reg = <0x0>;
xlnx,phy-type = <0x4>;
};
};
&gem1 {
phy-handle = <&phy1>;
is-internal-pcspma;
phy-mode = "sgmii";
phy1: phy@1 {
/* compatible = "marvell, 88E1512"; */
reg = <0x1>;
xlnx,phy-type = <0x4>;
};
};
&pinctrl0 {
pini2c0def:i2c0-default {
mux {
groups = "i2c0_9_grp";
function = "i2c0";
};
conf {
groups = "i2c0_9_grp";
bias-pull-up;
slew-rate = <0x1>;
io-standard = <0x0>;
};
};
pini2c0gp:i2c0-gpio {
mux {
groups = "gpio0_38_grp", "gpio0_39_grp";
function = "gpio0";
};
conf {
groups = "gpio0_38_grp", "gpio0_39_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
};
};
pini2c1def:i2c1-default {
mux {
groups = "i2c1_10_grp";
function = "i2c1";
};
conf {
groups = "i2c1_10_grp";
bias-pull-up;
slew-rate = <0x1>;
io-standard = <0x0>;
};
};
pini2c1gp:i2c1-gpio {
mux {
groups = "gpio0_40_grp", "gpio0_41_grp";
function = "gpio0";
};
conf {
groups = "gpio0_40_grp", "gpio0_41_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
};
};
pinuart0def:uart0-default {
mux {
groups = "uart0_10_grp";
function = "uart0";
};
conf {
groups = "uart0_10_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
};
conf-rx {
pins = "MIO42";
bias-high-impedance;
};
conf-tx {
pins = "MIO43";
bias-disable;
};
};
pinuart1def:uart1-default {
mux {
groups = "uart1_11_grp";
function = "uart1";
};
conf {
groups = "uart1_11_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
};
conf-rx {
pins = "MIO45";
bias-high-impedance;
};
conf-tx {
pins = "MIO44";
bias-disable;
};
};
pingem1def:gem1-default {
mux-mdio {
function = "mdio1";
groups = "mdio1_0_grp";
};
conf-mdio {
groups = "mdio1_0_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
bias-disable;
};
};
pingem2def:gem2-default {
mux-mdio {
function = "mdio2";
groups = "mdio1_1_grp";
};
conf-mdio {
groups = "mdio1_1_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
bias-disable;
};
};
pinsdhci:sdhci0-default {
mux {
groups = "sdio0_0_grp";
function = "sdio0";
};
conf {
groups = "sdio0_0_grp";
slew-rate = <0x1>;
io-standard = <0x0>;
bias-disable;
};
};
pingpio:gpio-default {
mux-sw {
function = "gpio0";
groups = "gpio0_74_grp", "gpio0_75_grp";
};
conf-sw {
groups = "gpio0_74_grp", "gpio0_75_grp";
slew-rate = <0x1>;
io-standard = <0>;
};
conf-pull-up {
pins = "MIO74", "MIO75";
bias-pull-up;
};
conf-pull-none {
pins = "MIO64", "MIO65";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0x1>;
io-standard = <0>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
pinctrl_qspi0_default: qspi0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0x1>;
io-standard = <0>;
};
conf-rx {
pins = "MIO52", "MIO53", "MIO55";
bias-high-impedance;
};
conf-tx {
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
"MIO60", "MIO61", "MIO62", "MIO63";
bias-disable;
};
};
};
&gpio {
pinctrl-names = "default";
pinctrl-0 = <&pingpio>;
};
&i2c0 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pini2c0def>;
pinctrl-1 = <&pini2c0gp>;
scl-gpios = <&gpio 0x26 0x0>;
sda-gpios = <&gpio 0x27 0x0>;
EEPROM:eeprom@50 {
compatible = "at,24c256";
reg = <0x50>;
#address-cells = <0x1>;
#size-cells = <0x1>;
board_sn@0 {
reg = <0x0 0x14>;
};
eth_mac@20 {
reg = <0x20 0x6>;
};
board_name@d0 {
reg = <0xd0 0x6>;
};
board_revision@e0 {
reg = <0xe0 0x3>;
};
};
RTC:rtc@68 {
compatible = "dallas,ds1340";
reg = <0x68>;
};
FPGATEMP:fpgaTemp@4C {
compatible = "adt7461";
reg = <0x4C>;
};
i2cswitch@71 {
compatible = "nxp,pca9546";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x71>;
RFM1@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x0>;
};
RFM2@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x1>;
};
PSB@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x2>;
};
hotspot:hotspot@48 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "ti,tmp112";
reg = <0x48>;
};
};
};
&i2c1 {
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pini2c1def>;
pinctrl-1 = <&pini2c1gp>;
scl-gpios = <&gpio 0x28 0x0>;
sda-gpios = <&gpio 0x29 0x0>;
ina226_1@40 {
compatible = "ti,ina226";
reg = <0x40>;
#address-cells = <0x1>;
#size-cells = <0x0>;
shunt-resistor = <0x7d0>;
};
ina226_2@41 {
compatible = "ti,ina226";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x41>;
shunt-resistor = <0x1388>;
};
ina226_3@44 {
compatible = "ti,ina226";
reg = <0x44>;
shunt-resistor = <0x1388>;
};
ina226_4@45 {
compatible = "ti,ina226";
reg = <0x45>;
shunt-resistor = <0x1388>;
};
i2cswitch@70 {
compatible = "nxp,pca9546";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0x70>;
SFP_1:SFP0@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x0>;
};
SFP_2:SFP1@1{
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x1>;
};
SFP_3:SFP2@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x2>;
};
SFP_4:SFP3@3 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "xxx";
reg = <0x3>;
};
};
};
&sdhci0 {
pinctrl-names = "default";
pinctrl-0 = <&pinsdhci>;
/* broken-mmc-highspeed; */
no-1-8-v;
broken-cd;
};
&spi1 {
spidev1: cpld@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "spidev";
reg = <0x0>;
spi-max-frequency = <0x989680>;
};
};
&spi0 {
clk0_ad9528: ad9528-1@2 {
#address-cells = <0x1>;
#size-cells = <0x0>;
#clock-cells = <0x1>;
compatible = "adi,ad9528";
reg = <0x2>;
spi-max-frequency = <0x989680>;
clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4",
"ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9",
"ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
adi,vcxo-freq = <0x7530000>;
adi,refb-enable;
adi,refb-r-div = <0x1>;
/*adi,refa-cmos-neg-inp-enable;*/
adi,ref-mode = <0x3>;
/*adi,osc-in-cmos-neg-inp-enable;*/
/*PLL1 config*/
adi,pll1-feedback-div = <0x8>;
/*adi,pll1-feedback-src-vcxo = <0x1>;*/
adi,pll1-charge-pump-current-nA = <0x1388>;
/*PLL2 config*/
adi,pll2-vco-div-m1 = <0x3>;
adi,pll2-n2-div = <0xa>;
adi,pll2-r1-div = <0x1>;
adi,pll2-charge-pump-current-nA = <0xc4888>;
/* SYSREF config*/
adi,sysref-src = <0x2>; /* SYSREF_SRC_INTERNAL*/
adi,sysref-pattern-mode = <0x1>; /* SYSREF_PATTERN_CONTINUOUS */
adi,sysref-k-div = <2000>;
/*adi,sysref-request-enable; see this */
adi,sysref-nshot-mode = <0x3>; /* SYSREF_NSHOT_4_PULSES */
adi,sysref-request-trigger-mode = <0x3>; /* SYSREF_EDGE_FALLING */
adi,rpole2 = <0x0>; /* RPOLE2_900_OHM */
adi,rzero = <0x2>; /* RZERO_2250_OHM */
adi,cpole1 = <0x2>; /* CPOLE1_16_PF */
adi,status-mon-pin0-function-select = <0x1>; /* PLL1 and PLL2 locked */
adi,status-mon-pin1-function-select = <0x7>; /* REFA Correct */
reset-gpios = <&gpio 0x4a 0x0>;
/*
DEV_CLK 122.88Mhz ---> AD9371_1_P
DEV_CLK 122.88Mhz ---> AD9371_1_N
Channel Divider 5 is used to divide 614.4Mhz so that to generate
122.88Mhz
Cal: 614.4/5 = 122.88Mhz
*/
channel@0 {
reg = <0x0>;
adi,extended-name = "DEV_CLK";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x0>; /* SOURCE_VCO */
};
/*
DEV_CLK 122.88Mhz ---> AD9371_2_P
DEV_CLK 122.88Mhz ---> AD9371_2_N
Channel Divider 5 is used to divide 614.4Mhz so that to generate
122.88Mhz
Cal: 614.4/5 = 122.88Mhz
*/
channel@1 {
reg = <0x1>;
adi,extended-name = "DEV_CLK1";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x0>; /* SOURCE_VCO */
};
/*
Schematic: OUT5 Signal
Signal Name: REF_CLK_OUT_P, REF_CLK_OUT_N
REF_CLK_OUT_P >>--------------JESD0_REF_CLK_P
REF_CLK_OUT_N >>--------------JESD0_REF_CLK_N
Used as JESD0_REF_CLK_P/N which goes into FPGA GTH Serdes Bank
*/
channel@5 {
reg = <0x5>;
adi,extended-name = "FMC_CLK";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x0>; /* SOURCE_VCO */
};
/*
Schematic: OUT6 Signal
Signal Name: AUX_CLK_OUT_P, AUX_CLK_OUT_N
AUX_CLK_OUT_P >>--------------JESD1_REF_CLK_P
AUX_CLK_OUT_N >>--------------JESD1_REF_CLK_N
Used as JESD1_REF_CLK_P/N which goes into FPGA GTH Serdes Bank
*/
channel@6 {
reg = <0x6>;
adi,extended-name = "FMC_CLK1";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x0>; /* SOURCE_VCO */
};
/*
Schematic: OUT2 Signal
Signal Name: SYSREF1_OUT_P, SYSREF1_OUT_N
Used as sysref signal to AD9371. Its a differential
*/
channel@2 {
reg = <0x2>;
adi,extended-name = "DEV_SYSREF";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x3>; /* SOURCE_SYSREF_VCXO */
};
/*
Schematic: OUT3 Signal
Signal Name: SYSREF2_OUT_P, SYSREF2_OUT_N
Used as sysref signal to AD9371. Its a differential
*/
channel@3 {
reg = <0x3>;
adi,extended-name = "DEV_SYSREF1";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x3>; /* SOURCE_SYSREF_VCXO */
};
/*
Schematic: OUT4 Signal
Signal Name: SYSREF3_OUT_P, SYSREF3_OUT_N
Used as sysref signal to FPGA. Its a differential
*/
channel@4 {
reg = <0x4>;
adi,extended-name = "FMC_SYSREF";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0x5>;
adi,signal-source = <0x2>; /* SOURCE_SYSREF_VCO */
};
/*
Schematic: OUT13 Signal
Signal Name: EXT_CLK_OUT_P, EXT_CLK_OUT_N
Its a differential clock out signal
*/
channel@13 {
reg = <0xd>;
adi,extended-name = "TEST_OUT";
adi,driver-mode = <0x0>; /* DRIVER_MODE_LVDS */
adi,divider-phase = <0x0>;
adi,channel-divider = <0xa>;
adi,signal-source = <0x1>; /* SOURCE_VCXO */
};
};
trx0_ad9371: ad9371-phy@0 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "adi,ad9371";
reg = <0>;
/*SPI Setup*/
spi-max-frequency = <0x989680>;
/*?? SPI Mode TODO*/
clocks = <&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi>,
<&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi>,
<&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi>,
<&clk0_ad9528 0>,<&clk0_ad9528 5>, <&clk0_ad9528 2>, <&clk0_ad9528 4>;
clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk","sysref_dev_clk","sysref_fmc_clk";
#clock-cells = <0x1>;
clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
adi,clocks-clk-pll-vco-freq_khz = <9830400>;
adi,clocks-device-clock_khz = <122880>;
adi,clocks-clk-pll-hs-div = <4>;
adi,clocks-clk-pll-vco-div = <2>;
adi,jesd204-obs-framer-over-sample = <0>;
adi,rx-profile-adc-div = <1>;
adi,rx-profile-en-high-rej-dec5 = <1>;
adi,rx-profile-iq-rate_khz = <122880>;
adi,rx-profile-rf-bandwidth_hz = <100000000>;
adi,rx-profile-rhb1-decimation = <1>;
adi,rx-profile-rx-bbf-3db-corner_khz = <100000>;
adi,rx-profile-rx-dec5-decimation = <5>;
adi,rx-profile-rx-fir-decimation = <2>;
adi,rx-profile-rx-fir-gain_db = <(-6)>;
adi,rx-profile-rx-fir-num-fir-coefs = <48>;
adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-5) (-26) (32) (51) (-67) (-116) (140) (212) (-252) (-367) (429) (595) (-688) (-931) (1072) (1427) (-1650) (-2188) (2612) (3496) (-4802) (-7591) (9656) (32317) (32317) (9656) (-7591) (-4802) (3496) (2612) (-2188) (-1650) (1427) (1072) (-931) (-688) (595) (429) (-367) (-252) (212) (140) (-116) (-67) (51) (32) (-26) (-5)>;
adi,rx-profile-custom-adc-profile = /bits/ 16 <534 386 201 98 1280 491 1591 279 1306 104 792 28 48 39 23 187>;
adi,obs-profile-adc-div = <1>;
adi,obs-profile-en-high-rej-dec5 = <1>;
adi,obs-profile-iq-rate_khz = <245760>;
adi,obs-profile-rf-bandwidth_hz = <200000000>;
adi,obs-profile-rhb1-decimation = <1>;
adi,obs-profile-rx-bbf-3db-corner_khz = <100000>;
adi,obs-profile-rx-dec5-decimation = <5>;
adi,obs-profile-rx-fir-decimation = <1>;
adi,obs-profile-rx-fir-gain_db = <6>;
adi,obs-profile-rx-fir-num-fir-coefs = <24>;
adi,obs-profile-rx-fir-coefs = /bits/ 16 <(-289) (81) (-23) (-86) (229) (-354) (397) (-233) (-657) (1699) (-4172) (23010) (-4172) (1699) (-657) (-233) (397) (-354) (229) (-86) (-23) (81) (-289) (0)>;
adi,obs-profile-custom-adc-profile = /bits/ 16 <450 349 201 98 1280 730 1626 818 1476 732 834 20 41 36 24 200>;
adi,obs-settings-custom-loopback-adc-profile = /bits/ 16 <569 369 201 98 1280 291 1541 149 1320 58 807 34 48 40 23 189>;
adi,tx-profile-dac-div = <1>;
adi,tx-profile-iq-rate_khz = <245760>;
adi,tx-profile-primary-sig-bandwidth_hz = <75000000>;
adi,tx-profile-rf-bandwidth_hz = <200000000>;
adi,tx-profile-thb1-interpolation = <2>;
adi,tx-profile-thb2-interpolation = <1>;
adi,tx-profile-tx-bbf-3db-corner_khz = <100000>;
adi,tx-profile-tx-dac-3db-corner_khz = <187000>;
adi,tx-profile-tx-fir-interpolation = <1>;
adi,tx-profile-tx-input-hb-interpolation = <1>;
adi,tx-profile-tx-fir-gain_db = <6>;
adi,tx-profile-tx-fir-num-fir-coefs = <16>;
adi,tx-profile-tx-fir-coefs = /bits/ 16 <(6) (-270) (203) (-168) (-84) (983) (-3222) (21143) (-3222) (983) (-84) (-168) (203) (-270) (6) (0)>;
adi,sniffer-profile-adc-div = <1>;
adi,sniffer-profile-en-high-rej-dec5 = <0>;
adi,sniffer-profile-iq-rate_khz = <30720>;
adi,sniffer-profile-rf-bandwidth_hz = <20000000>;
adi,sniffer-profile-rhb1-decimation = <2>;
adi,sniffer-profile-rx-bbf-3db-corner_khz = <100000>;
adi,sniffer-profile-rx-dec5-decimation = <5>;
adi,sniffer-profile-rx-fir-decimation = <4>;
/*
Old Design
reset-gpios = <&gpio 130 0>;
test-gpios = <&gpio 131 0>;
sysref_req-gpios = <&gpio 136 0>;
rx2_enable-gpios = <&gpio 132 0>;
rx1_enable-gpios = <&gpio 133 0>;
tx2_enable-gpios = <&gpio 134 0>;
tx1_enable-gpios = <&gpio 135 0>;
*/
/* New Design
Offset: 78 added to emio
FPGA gpio bit starts from 32 so
we need to add 32 in emio gpio
eg: gpio_t[82:32]
gpio_i[82:32]
gpio_o[82:32]
Let say reset gpio bit is given by fpga as 20
so we need to add offset of 31
calculate emio num = 20 + 31 = 51
Calculate processor gpio:i (mio start from 0 to 78 so we need
to pick afterwrds.
processor gpio number offset emio = 78 + emio_num
= 78 +51 = 130 ( reset gpio)
*/
reset-gpios = <&gpio 129 0>;
//test-gpios = <&gpio 131 0>; //136
sysref_req-gpios = <&gpio 134 0>; //135
/*
rx2_enable-gpios = <&gpio 130 0>; //131
rx1_enable-gpios = <&gpio 131 0>; //132
tx2_enable-gpios = <&gpio 132 0>; //133
tx1_enable-gpios = <&gpio 133 0>; //134
*/
adi,jesd204-deframer-eq-setting = <3>;
};
/* Second ADI Configuration*/
trx1_ad9371: ad9371-phy@1 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "adi,ad9371";
reg = <1>;
spi-max-frequency = <0x989680>;
clocks = <&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi>,
<&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi>,
<&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi>,
<&clk0_ad9528 1>,<&clk0_ad9528 6>, <&clk0_ad9528 3>, <&clk0_ad9528 4>;
clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk","sysref_dev_clk","sysref_fmc_clk";
#clock-cells = <0x1>;
clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
adi,clocks-clk-pll-vco-freq_khz = <9830400>;
adi,clocks-device-clock_khz = <122880>;
adi,clocks-clk-pll-hs-div = <4>;
adi,clocks-clk-pll-vco-div = <2>;
adi,jesd204-obs-framer-over-sample = <0>;
adi,rx-profile-adc-div = <1>;
adi,rx-profile-en-high-rej-dec5 = <1>;
adi,rx-profile-iq-rate_khz = <122880>;
adi,rx-profile-rf-bandwidth_hz = <100000000>;
adi,rx-profile-rhb1-decimation = <1>;
adi,rx-profile-rx-bbf-3db-corner_khz = <100000>;
adi,rx-profile-rx-dec5-decimation = <5>;
adi,rx-profile-rx-fir-decimation = <2>;
adi,rx-profile-rx-fir-gain_db = <(-6)>;
adi,rx-profile-rx-fir-num-fir-coefs = <48>;
adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-5) (-26) (32) (51) (-67) (-116) (140) (212) (-252) (-367) (429) (595) (-688) (-931) (1072) (1427) (-1650) (-2188) (2612) (3496) (-4802) (-7591) (9656) (32317) (32317) (9656) (-7591) (-4802) (3496) (2612) (-2188) (-1650) (1427) (1072) (-931) (-688) (595) (429) (-367) (-252) (212) (140) (-116) (-67) (51) (32) (-26) (-5)>;
adi,rx-profile-custom-adc-profile = /bits/ 16 <534 386 201 98 1280 491 1591 279 1306 104 792 28 48 39 23 187>;
adi,obs-profile-adc-div = <1>;
adi,obs-profile-en-high-rej-dec5 = <1>;
adi,obs-profile-iq-rate_khz = <245760>;
adi,obs-profile-rf-bandwidth_hz = <200000000>;
adi,obs-profile-rhb1-decimation = <1>;
adi,obs-profile-rx-bbf-3db-corner_khz = <100000>;
adi,obs-profile-rx-dec5-decimation = <5>;
adi,obs-profile-rx-fir-decimation = <1>;
adi,obs-profile-rx-fir-gain_db = <6>;
adi,obs-profile-rx-fir-num-fir-coefs = <24>;
adi,obs-profile-rx-fir-coefs = /bits/ 16 <(-289) (81) (-23) (-86) (229) (-354) (397) (-233) (-657) (1699) (-4172) (23010) (-4172) (1699) (-657) (-233) (397) (-354) (229) (-86) (-23) (81) (-289) (0)>;
adi,obs-profile-custom-adc-profile = /bits/ 16 <450 349 201 98 1280 730 1626 818 1476 732 834 20 41 36 24 200>;
adi,obs-settings-custom-loopback-adc-profile = /bits/ 16 <569 369 201 98 1280 291 1541 149 1320 58 807 34 48 40 23 189>;
adi,tx-profile-dac-div = <1>;
adi,tx-profile-iq-rate_khz = <245760>;
adi,tx-profile-primary-sig-bandwidth_hz = <75000000>;
adi,tx-profile-rf-bandwidth_hz = <200000000>;
adi,tx-profile-thb1-interpolation = <2>;
adi,tx-profile-thb2-interpolation = <1>;
adi,tx-profile-tx-bbf-3db-corner_khz = <100000>;
adi,tx-profile-tx-dac-3db-corner_khz = <187000>;
adi,tx-profile-tx-fir-interpolation = <1>;
adi,tx-profile-tx-input-hb-interpolation = <1>;
adi,tx-profile-tx-fir-gain_db = <6>;
adi,tx-profile-tx-fir-num-fir-coefs = <16>;
adi,tx-profile-tx-fir-coefs = /bits/ 16 <(6) (-270) (203) (-168) (-84) (983) (-3222) (21143) (-3222) (983) (-84) (-168) (203) (-270) (6) (0)>;
adi,sniffer-profile-adc-div = <1>;
adi,sniffer-profile-en-high-rej-dec5 = <0>;
adi,sniffer-profile-iq-rate_khz = <30720>;
adi,sniffer-profile-rf-bandwidth_hz = <20000000>;
adi,sniffer-profile-rhb1-decimation = <2>;
adi,sniffer-profile-rx-bbf-3db-corner_khz = <100000>;
adi,sniffer-profile-rx-dec5-decimation = <5>;
adi,sniffer-profile-rx-fir-decimation = <4>;
reset-gpios = <&gpio 155 0>;
/* New Design ToDo*/
//test-gpios = <&gpio 161 0>;
sysref_req-gpios = <&gpio 134 0>; //135
/*
rx2_enable-gpios = <&gpio 156 0>;
rx1_enable-gpios = <&gpio 157 0>;
tx2_enable-gpios = <&gpio 158 0>;
tx1_enable-gpios = <&gpio 159 0>;
*/
adi,jesd204-deframer-eq-setting = <3>;
};
};
&amba_pl {
#address-cells = <0x1>;
#size-cells = <0x1>;
interrupt-parent = <&gic>;
ranges = <0 0 0 0xffffffff>;
};
/* TBD */
/*
&axi_dma_0{
reg = <0x80001000 0x1000>;
};
&axi_ethernet_0{
reg = <0x80000000 0x1000>;
};
*/
/*
@ AXI ADC HDL driver is the driver for Generic AXI ADC IP core. This driver is split into two parts.
a) Control Driver i.e. SPI ADC Driver which configures the converter internal control registers.
This part is typically instantiated via SPI bus like ad9371_conv.c , ad9361_conv.c
b) AXI ADC Driver - Data Capture driver
Device probing for the data capture driver (AXI ADC) which controls the AXI HDL core registers and DMA,
is delayed until the SPI control driver is fully probed
The device tree phandle "spibus-connected" is used to connect the capture driver with a SPI control driver.
This split is required since AXI-ADC and the SPI-ADC parts are instantiated via differet busses i.e AXI and
SPI. AXI-ADC driver registers the IIO device, the SPI-ADC instance doesn't.
However a shared data structure (struct axiadc_converter) is used so that the methods local to the SPI-ADC
driver can extend the IIO attributes provided the AXI-ADC driver. There is also a callback (post_setup)
provided which calls from AXI-ADC into AXI-SPI driver after AXI-ADC is fully alive. This callback func is
then used to configure the digital data path, test and tune the digial data interface etc
For the AD9371 family of transceivers , things are bit more differentiated. In fact these devices have a
separate IIO devices for the radio control portion. We call them the PHY devices i.e ad9371.c, ad9361.c.
The PHY drivers are intented to be independent from our AXI-ADC capture drivers and underlying HDL designs.
Therefore things related to the AXI-ADC driver are located in the ad9371_conv.c files
@ First ADI TPL Core Block
@ 2018.v2: axi_ad9371_core: axi_ad9371@84a00000
@ 2018.v3: This "AD9371_TOP_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core" has same address like old one axi_ad9371_core:
@ This "AD9371_TOP_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core" is a new block
@ This "AD9371_TOP_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core" is a new block
*/
&AD9371_TOP_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-rx-1.0";
reg = <0x80024000 0x8000>;
/delete-property/ clock-names;
/delete-property/ clocks;
dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_dma 0>;
dma-names = "rx";
/* It is used to connect capture driver ( AXI ADC HDL Driver) with a SPI control driver */
spibus-connected = <&trx0_ad9371>;
};
&AD9371_TOP_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-obs-1.0";
reg = <0x80030000 0x1000>;
dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma 0>;
dma-names = "rx";
clocks = <&trx0_ad9371 1>;
clock-names = "sampl_clk";
};
&AD9371_TOP_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-tx-1.0";
reg = <0x80028000 0x4000>;
dmas = <&AXI_AD_DMA_TOP_axi_ad9371_tx_dma 0>;
dma-names = "tx";
clocks = <&trx0_ad9371 2>;
clock-names = "sampl_clk";
/* It is used to connect capture driver ( AXI ADC HDL Driver) with a SPI control driver */
spibus-connected = <&trx0_ad9371>;
adi,axi-pl-fifo-enable;
};
/* Second ADI TPL Core Block*/
&AD9371_TOP1_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-rx-1.0";
reg = <0x80034000 0x8000>;
/delete-property/ clock-names;
/delete-property/ clocks;
//dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_dma 0>;
//dma-names = "rx";
/* It is used to connect capture driver ( AXI ADC HDL Driver) with a SPI control driver */
spibus-connected = <&trx1_ad9371>;
};
&AD9371_TOP1_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-obs-1.0";
reg = <0x80040000 0x1000>;
//dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma 0>;
//dma-names = "rx";
clocks = <&trx1_ad9371 1>;
clock-names = "sampl_clk";
};
&AD9371_TOP1_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core {
compatible = "adi,axi-ad9371-tx-1.0";
reg = <0x80038000 0x4000>;
//dmas = <&AXI_AD_DMA_TOP_axi_ad9371_tx_dma 0>;
//dma-names = "tx";
clocks = <&trx1_ad9371 2>;
clock-names = "sampl_clk";
/* It is used to connect capture driver ( AXI ADC HDL Driver) with a SPI control driver */
spibus-connected = <&trx1_ad9371>;
adi,axi-pl-fifo-enable;
};
/*
&axi_ddc_rx_dma {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c400000 0x1000>;
#dma-cells = <1>;
#clock-cells = <0>;
clocks = <&clk 73>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <60>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <60>;
adi,destination-bus-type = <0>;
};
};
};
*/
//2019.v2: axi_ad9371_rx_dma
//2018.v3: AXI_AD_DMA_TOP_axi_ad9371_rx_dma
&AXI_AD_DMA_TOP_axi_ad9371_rx_dma {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x800b0000 0x1000>;
#dma-cells = <1>;
#clock-cells = <0>;
//2018.v2: Input Clock Configuration
clocks = <&clk 73>;
/delete-property/ clock-names;
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
//clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};
//2018.v2: axi_ad9371_rx_jesd_rx_axi
//2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi
&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x8000c000 0x4000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk 71>, <&axi_ad9371_rx_clkgen>, <&axi_ad9371_rx_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
adi,octets-per-frame = <4>;
adi,frames-per-multiframe = <32>;
};
/* Second JESD Rx Block*/
&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x8001c000 0x4000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk 71>, <&axi_ad9371_rx_clkgen>, <&axi_ad9371_rx_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk_1";
adi,octets-per-frame = <4>;
adi,frames-per-multiframe = <32>;
};
//2018.v2: axi_ad9371_rx_os_dma
//2018.v3: AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma
&AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x800c0000 0x1000>;
#dma-cells = <1>;
#clock-cells = <0>;
//2018.v2: Input Clock Configuration
clocks = <&clk 73>;
/delete-property/ clock-names;
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk";
//clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <2>;
adi,destination-bus-width = <64>;
adi,destination-bus-type = <0>;
};
};
};
//2018.v2: axi_ad9371_rx_os_jesd_rx_axi
//2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi
&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi{
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x80010000 0x4000>;
// 2018.v2: The clock configuration
// clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>, <&axi_ad9371_rx_os_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
// 2018.v3: New Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
//Clock Output: No Change
#clock-cells = <0>;
clock-output-names = "jesd_rx_os_lane_clk";
adi,octets-per-frame = <2>;
adi,frames-per-multiframe = <32>;
};
/* Second AD9371 JESD Rx OS Block*/
&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi{
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x80020000 0x4000>;
// 2018.v2: The clock configuration
// clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>, <&axi_ad9371_rx_os_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
// 2018.v3: New Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
//Clock Output: No Change
#clock-cells = <0>;
clock-output-names = "jesd_rx_os_lane_clk_1";
adi,octets-per-frame = <2>;
adi,frames-per-multiframe = <32>;
};
//2018.v2: axi_ad9371_rx_os_xcvr
//2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr
&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x80080000 0x10000>;
// 2018.v2: The clock configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>;
clocks = <&clk0_ad9528 5>;
clock-names = "conv";
// 2018.v3: New Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "rx_os_gt_clk", "rx_os_out_clk";
/*2 bit variable. For ultrascale , it selects the PLL reference
clk source to be forwarded to the OUTCLK MUX : 0-CPLL, 3-QPLL*/
adi,sys-clk-select = <0>;
/* 3 bit variable. Controls the OUTCLKSEL multiplexer, controlling what will be
forwarded to OUTCLK pin. Check RX/TXOUTCLKSEL parameter in the transceiver documentation
for the FPGA you are using
*/
adi,out-clk-select = <3>;
/* If set, the transceiver will be used in LPM mode. Otherwise, will be used in DFE mode*/
adi,use-lpm-enable;
/* If set, the CPLL will be used for these transceivers*/
adi,use-cpll-enable;
};
/* Second AD9371 JESD Rx OS Rcvr Block*/
&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x800f0000 0x10000>;
// 2018.v2: The clock configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>;
clocks = <&clk0_ad9528 6>;
clock-names = "conv";
// 2018.v3: New Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "rx_os_gt_clk_1", "rx_os_out_clk_1";
/* 2 bit variable. For ultrascale , it selects the PLL reference
clk source to be forwarded to the OUTCLK MUX : 0-CPLL, 3-QPLL
*/
adi,sys-clk-select = <0>;
/* 3 bit variable. Controls the OUTCLKSEL multiplexer, controlling what will be
forwarded to OUTCLK pin. Check RX/TXOUTCLKSEL parameter in the transceiver documentation
for the FPGA you are using
*/
adi,out-clk-select = <3>;
/* If set, the transceiver will be used in LPM mode. Otherwise, will be used in DFE mode*/
adi,use-lpm-enable;
/* If set, the CPLL will be used for these transceivers*/
adi,use-cpll-enable;
};
//2018.v2: axi_ad9371_rx_xcvr
//2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr
&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x80070000 0x10000>;
// 2018.v2: Input clock configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_rx_clkgen 0>;
clocks = <&clk0_ad9528 5>;
clock-names = "conv";
// 2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "rx_gt_clk", "rx_out_clk";
/* 2 bit variable. For ultrascale , it selects the PLL reference
clk source to be forwarded to the OUTCLK MUX : 0-CPLL, 3-QPLL
*/
adi,sys-clk-select = <0>;
/* 3 bit variable. Controls the OUTCLKSEL multiplexer, controlling what will be
forwarded to OUTCLK pin. Check RX/TXOUTCLKSEL parameter in the transceiver documentation
for the FPGA you are using
*/
adi,out-clk-select = <3>;
/* If set, the transceiver will be used in LPM mode. Otherwise, will be used in DFE mode*/
adi,use-lpm-enable;
/* If set, the CPLL will be used for these transceivers*/
adi,use-cpll-enable;
};
/* Second AD9371 JESD Rx Rcvr Block*/
&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x800e0000 0x10000>;
// 2018.v2: Input clock configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_rx_clkgen 0>;
clocks = <&clk0_ad9528 6>;
clock-names = "conv";
// 2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "rx_gt_clk_1", "rx_out_clk_1";
/* 2 bit variable. For ultrascale , it selects the PLL reference
clk source to be forwarded to the OUTCLK MUX : 0-CPLL, 3-QPLL
*/
adi,sys-clk-select = <0>;
/* 3 bit variable. Controls the OUTCLKSEL multiplexer, controlling what will be
forwarded to OUTCLK pin. Check RX/TXOUTCLKSEL parameter in the transceiver documentation
for the FPGA you are using
*/
adi,out-clk-select = <3>;
/* If set, the transceiver will be used in LPM mode. Otherwise, will be used in DFE mode*/
adi,use-lpm-enable;
/* If set, the CPLL will be used for these transceivers*/
adi,use-cpll-enable;
};
//2018.v2: axi_ad9371_tx_dma
//2018.v3: AXI_AD_DMA_TOP_axi_ad9371_tx_dma
&AXI_AD_DMA_TOP_axi_ad9371_tx_dma {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x800d0000 0x1000>;
#dma-cells = <1>;
#clock-cells = <0>;
// 2018.v2: Input clock configuration
clocks = <&clk 73>;
/delete-property/ clock-names;
// 2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk";
//clocks = <&clk 71>, <&clk 72>, <&clk 72>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <64>;
adi,source-bus-type = <0>;
adi,destination-bus-width = <128>;
adi,destination-bus-type = <1>;
};
};
};
//2018.v2: axi_ad9371_tx_jesd_tx_axi
//2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi
&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x80014000 0x4000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>,<&axi_ad9371_tx_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
#clock-cells = <0>;
clock-output-names = "jesd_tx_lane_clk";
adi,octets-per-frame = <2>; //F
adi,frames-per-multiframe = <32>; //K
adi,converter-resolution = <14>; //N
adi,bits-per-sample = <16>; //N'
adi,converters-per-device = <4>; //M
adi,control-bits-per-sample = <2>; //CS
};
/* Second AD9371 JESD Tx Block */
&AD9371_TOP1_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x80018000 0x4000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>,<&axi_ad9371_tx_xcvr 0>;
clocks = <&clk 71>, <&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr 0>;
clock-names = "s_axi_aclk", "lane_clk";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk", "core_clk";
//clocks = <&clk 71>, <&misc_clk_0>;
#clock-cells = <0>;
clock-output-names = "jesd_tx_lane_clk_1";
adi,octets-per-frame = <2>; //F
adi,frames-per-multiframe = <32>; //K
adi,converter-resolution = <14>; //N
adi,bits-per-sample = <16>; //N'
adi,converters-per-device = <4>; //M
/*
a) 2 Bits per sample
b) Control bits can be used to communicate status info, mark an
inactive converter on the link or control receiver operation
*/
adi,control-bits-per-sample = <2>; //CS
};
//2018.v2: axi_ad9371_tx_xcvr
//2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr
&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr{
compatible = "adi,axi-adxcvr-1.0";
reg = <0x80090000 0x10000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>;
clocks = <&clk0_ad9528 5>;
clock-names = "conv";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "tx_gt_clk", "tx_out_clk";
adi,sys-clk-select = <3>;
adi,out-clk-select = <3>;
};
/* Second AD9371 JESD Tx Rcvr Block */
&AD9371_TOP1_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr{
compatible = "adi,axi-adxcvr-1.0";
reg = <0x80100000 0x10000>;
//2018.v2: Input Clock Configuration
//clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>;
clocks = <&clk0_ad9528 6>;
clock-names = "conv";
//2018.v3: Input Clock Configuration
//clock-names = "s_axi_aclk";
//clocks = <&clk 71>;
#clock-cells = <1>;
clock-output-names = "tx_gt_clk_1", "tx_out_clk_1";
adi,sys-clk-select = <3>;
adi,out-clk-select = <3>;
};
/*
&cpri_zcu102_0{
reg = <0x80004000 0x1000>;
compatible = "generic-uio";
};
&axi_iic_0{
reg = <0x80003000 0x1000>;
};
&user_reg_top_0{
reg = <0x80002000 0x1000>;
compatible = "generic-uio";
};
*/
&PS_TOP_axi_iic_0 {
#address-cells = <1>;
#size-cells = <0>;
clock-names = "s_axi_aclk";
clocks = <&clk 71>;
compatible = "xlnx,xps-iic-2.00.a";
interrupt-names = "iic2intc_irpt";
interrupt-parent = <&gic>;
interrupts = <0 93 4>;
reg = <0x80050000 0x1000>;
};
//Name change: cpri_zcu102_0 -> cpri_temac_top_0
//&cpri_temac_top_0 {
&cpri_temac_top_v1_0 {
clock-names = "s00_axi_aclk";
clocks = <&clk 71>;
compatible = "generic-uio";
reg = <0x80001000 0x1000>;
xlnx,s00-axi-addr-width = <0xc>;
xlnx,s00-axi-data-width = <0x20>;
};
//&csr_reg_top_0 {
&csr_reg_top {
clock-names = "s00_axi_aclk";
clocks = <&clk 74>;
compatible = "generic-uio";
reg = <0x80000000 0x1000>;
xlnx,s00-axi-addr-width = <0xa>;
xlnx,s00-axi-data-width = <0x20>;
};
&psu_ctrl_ipi {
compatible = "xlnx,PERIPHERAL-1.0";
reg = <0xff380000 0x80000>;
};
&psu_message_buffers {
compatible = "xlnx,PERIPHERAL-1.0";
reg = <0xff990000 0x10000>;
};
/*
&cfr_dpd_top_dpd_top {
clock-names = "s_axi_ctrl_2x_aclk", "s_axi_ctrl_aclk", "s_axi_user_aclk";
clocks = <&clk 73>, <&clk 71>, <&clk 71>;
compatible = "generic-uio";
reg = <0x88000000 0x4000000 0x8c000000 0x20000>;
};
&cfr_dpd_top_pc_cfr_top {
clock-names = "s_axi_aclk";
clocks = <&clk 71>;
compatible = "generic-uio";
reg = <0x84000000 0x4000000>;
};
*/
Regards,
Manish
Few wording
[edited by: manish3134 at 9:40 AM (GMT 0) on 16 Apr 2020]
