Custom device tree in yocto and built with petalinux

UPDATE:
In the end it was straight forward... We combined all the information from the system-user.dtsi (bootargs, QSPI and IP status settings) together with daq3 device trees from github and placed them in /meta-adi/meta-adi-xilinx/recipes-bsp/device-tree. We modified device-tree.bbappend and set "KERNEL_DTB = " to the device tree we are using for our custom board.

The system boots from the QSPI flash and mounts a jffsv2 file system. The SPI bus is not connected to the EMIO pins but directly to the MIO pins of the PS as spi1.0.

The problem we are facing now is that the is ADC not showing up in the IIO devices list. Can somebody please have a look at the boot log and device tree and spot for any problems or handles on how to solve this? Any information on how to debug this would be helpful already! Both are attached below.

Details:
- The base design for the HDL firmware and the device tree is the fmcdaq3 project. 
- The ad9528 clock chip is not included on our board but the Si5340 clock generator. This chip is added to the device tree to provide the ADC_CLK and the gtrefclk for the transceivers. (SYSREF is not connected to the ADC on our board.)
- The ad9680 is probed and returns the correct CHIP_ID for the ad9694 ADC. However, it states: "ad9680 spi1.0: Unrecognized CHIP_ID 0xDB"
- The gpio pins for powerdown, FDA and FDB are defined in the device tree and in the HDL firmware.

IIO_INFO shows:
root@grand17mrt:~# iio_info
Library version: 0.18 (git tag: v0.18)
Compiled with backends: local xml ip usb
IIO context created with local backend.
Backend version: 0.18 (git tag: v0.18)
Backend description string: Linux grand17mrt 4.14.0-xilinx- #1 SMP Wed Apr 15 07:22:26 UTC 2020 aarch64
IIO context has 1 attributes:
local,kernel: 4.14.0-xilinx-
IIO context has 2 devices:
iio:device0: ams
30 channels found:
temp1: remote_temp (input)
3 channel-specific attributes found:
attr 0: offset value: -36058
attr 1: raw value: 42332
attr 2: scale value: 7.771514892
--- snip ---
2 channel-specific attributes found:
attr 0: raw value: 39095
attr 1: scale value: 0.015258789
1 device-specific attributes found:
attr 0: sampling_frequency ERROR: Invalid argument (-22)
iio_sysfs_trigger:
0 channels found:
2 device-specific attributes found:
attr 0: add_trigger ERROR: Permission denied (-13)
attr 1: remove_trigger ERROR: Permission denied (-13)
root@grand17mrt:~#

(selection of) the devices are:
root@grand17mrt:~# ls -al /sys/bus/platform/devices/
total 0
84a10000.axi-ad9694-hpc -> ../../../devices/platform/fpga-axi@0/84a10000.axi-ad9694-hpc
84a50000.axi-adxcvr-rx -> ../../../devices/platform/fpga-axi@0/84a50000.axi-adxcvr-rx
84aa0000.axi-jesd204-rx -> ../../../devices/platform/fpga-axi@0/84aa0000.axi-jesd204-rx
85000000.axi-sysid-0 -> ../../../devices/platform/fpga-axi@0/85000000.axi-sysid-0
9c400000.rx-dmac -> ../../../devices/platform/fpga-axi@0/9c400000.rx-dmac
amba_apu@0 -> ../../../devices/platform/amba_apu@0
amba_pl@0 -> ../../../devices/platform/amba_pl@0
ff020000.i2c -> ../../../devices/platform/amba/ff020000.i2c
ff040000.spi -> ../../../devices/platform/amba/ff040000.spi
ff0f0000.spi -> ../../../devices/platform/amba/ff0f0000.spi
ffa50000.ams -> ../../../devices/platform/amba/ffa50000.ams
fpga-axi@0 -> ../../../devices/platform/fpga-axi@0

BOOTLOG

Xilinx Zynq MP First Stage Boot Loader
Release 2018.3   Apr 10 2020  -  10:43:46
NOTICE:  ATF running on XCZU7CG/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x0
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 07:18:47, Apr 15 2020
PMUFW:	v1.1


U-Boot 2018.01 (Apr 15 2020 - 07:43:09 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  3 GiB
EL Level:	EL2
Chip ID:	zu7cg
MMC:
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
*** Warning - bad CRC, using default environment

In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
Bootmode: QSPI_MODE
U-BOOT for grand17mrt

Hit any key to stop autoboot:  0
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
device 0 offset 0x1e40000, size 0x2400000
SF: 37748736 bytes @ 0x1e40000 Read: OK
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  gzip compressed
     Data Start:   0x10000100
     Data Size:    7606919 Bytes = 7.3 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x00080000
     Entry Point:  0x00080000
     Hash algo:    sha1
     Hash value:   7b84b18dbfcaa874922e79d6d3bcda3104041707
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x1074148c
     Data Size:    41778 Bytes = 40.8 KiB
     Architecture: AArch64
     Hash algo:    sha1
     Hash value:   ce5bd739b09949a5589a08010c8e236bae9e539c
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x1074148c
   Uncompressing Kernel Image ... OK
   Loading Device Tree to 0000000007ff2000, end 0000000007fff331 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.0-xilinx- (oe-user@oe-host) (gcc version 7.3.0 (GCC)) #1 SMP Wed Apr 15 07:22:26 UTC 2020
[    0.000000] Boot CPU: AArch64 Processor [410fd034]
[    0.000000] Machine model: ZynqMP ZCU102 Rev1.0
[    0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
[    0.000000] bootconsole [cdns0] enabled
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] cma: Reserved 256 MiB at 0x0000000070000000
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] random: fast init done
[    0.000000] percpu: Embedded 21 pages/cpu @ffffffc87ff94000 s46488 r8192 d31336 u86016
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1034240
[    0.000000] Kernel command line: console=ttyPS0,115200 earlycon clk_ignore_unused root=/dev/mtdblock3 rw rootfstype=jffs2
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] software IO TLB [mem 0x6bfff000-0x6ffff000] (64MB) mapped at [ffffffc06bfff000-ffffffc06fffefff]
[    0.000000] Memory: 3783716K/4194304K available (10492K kernel code, 756K rwdata, 4500K rodata, 512K init, 2164K bss, 148444K reserved, 262144K cma-reserved)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     modules : 0xffffff8000000000 - 0xffffff8008000000   (   128 MB)
[    0.000000]     vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000   (   250 GB)
[    0.000000]       .text : 0xffffff8008080000 - 0xffffff8008ac0000   ( 10496 KB)
[    0.000000]     .rodata : 0xffffff8008ac0000 - 0xffffff8008f30000   (  4544 KB)
[    0.000000]       .init : 0xffffff8008f30000 - 0xffffff8008fb0000   (   512 KB)
[    0.000000]       .data : 0xffffff8008fb0000 - 0xffffff800906d200   (   757 KB)
[    0.000000]        .bss : 0xffffff800906d200 - 0xffffff800928a5b0   (  2165 KB)
[    0.000000]     fixed   : 0xffffffbefe7fd000 - 0xffffffbefec00000   (  4108 KB)
[    0.000000]     PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000   (    16 MB)
[    0.000000]     vmemmap : 0xffffffbf00000000 - 0xffffffc000000000   (     4 GB maximum)
[    0.000000]               0xffffffbf00000000 - 0xffffffbf1dc00000   (   476 MB actual)
[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc880000000   ( 34816 MB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU event tracing is enabled.
[    0.000000] 	RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] arch_timer: cp15 timer(s) running at 99.90MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x170a3d70de, max_idle_ns: 440795202122 ns
[    0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511100ns
[    0.008326] Console: colour dummy device 80x25
[    0.012404] Calibrating delay loop (skipped), value calculated using timer frequency.. 199.80 BogoMIPS (lpj=399600)
[    0.022777] pid_max: default: 32768 minimum: 301
[    0.027473] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.034052] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.041816] ASID allocator initialised with 65536 entries
[    0.046551] Hierarchical SRCU implementation.
[    0.051164] EFI services will not be available.
[    0.055352] zynqmp_plat_init Platform Management API v1.1
[    0.060703] zynqmp_plat_init Trustzone version v1.0
[    0.065617] smp: Bringing up secondary CPUs ...
[    0.070312] Detected VIPT I-cache on CPU1
[    0.070343] CPU1: Booted secondary processor [410fd034]
[    0.070401] smp: Brought up 1 node, 2 CPUs
[    0.083301] SMP: Total of 2 processors activated.
[    0.087978] CPU features: detected feature: 32-bit EL0 Support
[    0.093781] CPU: All CPU(s) started at EL2
[    0.097857] alternatives: patching kernel code
[    0.103060] devtmpfs: initialized
[    0.110211] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.115264] futex hash table entries: 512 (order: 4, 65536 bytes)
[    0.127316] xor: measuring software checksum speed
[    0.165414]    8regs     :  2280.000 MB/sec
[    0.205441]    8regs_prefetch:  2032.000 MB/sec
[    0.245472]    32regs    :  2802.000 MB/sec
[    0.285502]    32regs_prefetch:  2355.000 MB/sec
[    0.285531] xor: using function: 32regs (2802.000 MB/sec)
[    0.289930] pinctrl core: initialized pinctrl subsystem
[    0.295617] NET: Registered protocol family 16
[    0.300401] cpuidle: using governor menu
[    0.303873] vdso: 2 pages (1 code @ ffffff8008ac6000, 1 data @ ffffff8008fb4000)
[    0.310719] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.317964] DMA: preallocated 256 KiB pool for atomic allocations
[    0.345020] reset_zynqmp reset-controller: Xilinx zynqmp reset driver probed
[    0.346941] ARM CCI_400_r1 PMU driver probed
[    0.351189] zynqmp-pinctrl ff180000.pinctrl: zynqmp pinctrl initialized
[    0.371856] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.439323] raid6: int64x1  gen()   400 MB/s
[    0.507378] raid6: int64x1  xor()   440 MB/s
[    0.575429] raid6: int64x2  gen()   683 MB/s
[    0.643428] raid6: int64x2  xor()   596 MB/s
[    0.711511] raid6: int64x4  gen()  1033 MB/s
[    0.779572] raid6: int64x4  xor()   734 MB/s
[    0.847641] raid6: int64x8  gen()   970 MB/s
[    0.915671] raid6: int64x8  xor()   737 MB/s
[    0.983709] raid6: neonx1   gen()   718 MB/s
[    1.051782] raid6: neonx1   xor()   844 MB/s
[    1.119850] raid6: neonx2   gen()  1157 MB/s
[    1.187881] raid6: neonx2   xor()  1189 MB/s
[    1.255947] raid6: neonx4   gen()  1488 MB/s
[    1.324001] raid6: neonx4   xor()  1421 MB/s
[    1.392059] raid6: neonx8   gen()  1631 MB/s
[    1.460113] raid6: neonx8   xor()  1510 MB/s
[    1.460140] raid6: using algorithm neonx8 gen() 1631 MB/s
[    1.464113] raid6: .... xor() 1510 MB/s, rmw enabled
[    1.469048] raid6: using neon recovery algorithm
[    1.475100] SCSI subsystem initialized
[    1.477531] usbcore: registered new interface driver usbfs
[    1.482849] usbcore: registered new interface driver hub
[    1.488125] usbcore: registered new device driver usb
[    1.493182] media: Linux media interface: v0.10
[    1.497642] Linux video capture interface: v2.00
[    1.502247] pps_core: LinuxPPS API ver. 1 registered
[    1.507146] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.516249] PTP clock support registered
[    1.520336] zynqmp-ipi ff9905c0.mailbox: Probed ZynqMP IPI Mailbox driver.
[    1.527110] FPGA manager framework
[    1.530453] fpga-region fpga-full: FPGA Region probed
[    1.535459] Advanced Linux Sound Architecture Driver Initialized.
[    1.541688] Bluetooth: Core ver 2.22
[    1.544998] NET: Registered protocol family 31
[    1.549402] Bluetooth: HCI device and connection manager initialized
[    1.555725] Bluetooth: HCI socket layer initialized
[    1.560572] Bluetooth: L2CAP socket layer initialized
[    1.565607] Bluetooth: SCO socket layer initialized
[    1.571722] clocksource: Switched to clocksource arch_sys_counter
[    1.576586] VFS: Disk quotas dquot_6.6.0
[    1.580454] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.591224] NET: Registered protocol family 2
[    1.591904] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
[    1.598961] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[    1.605869] TCP: Hash tables configured (established 32768 bind 32768)
[    1.611922] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[    1.617875] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[    1.624357] NET: Registered protocol family 1
[    1.628735] RPC: Registered named UNIX socket transport module.
[    1.634442] RPC: Registered udp transport module.
[    1.639106] RPC: Registered tcp transport module.
[    1.643780] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.650843] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    1.657401] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    1.665588] audit: initializing netlink subsys (disabled)
[    1.670700] audit: type=2000 audit(1.623:1): state=initialized audit_enabled=0 res=1
[    1.678105] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[    1.685089] NFS: Registering the id_resolver key type
[    1.689516] Key type id_resolver registered
[    1.693656] Key type id_legacy registered
[    1.697644] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    1.704317] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    1.734996] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[    1.736752] io scheduler noop registered
[    1.740638] io scheduler deadline registered
[    1.744892] io scheduler cfq registered (default)
[    1.749556] io scheduler mq-deadline registered
[    1.754057] io scheduler kyber registered
[    1.759441] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[    1.765122] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[    1.772053] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[    1.778962] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[    1.785892] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[    1.792821] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[    1.799752] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[    1.806672] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[    1.813652] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[    1.820529] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[    1.827450] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[    1.834378] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[    1.841307] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[    1.848234] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[    1.855161] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[    1.862083] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[    1.895806] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.899115] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    1.906890] brd: module loaded
[    1.908188] PLL: shutdown
[    1.908222] zynqmp_pll_disable() clock disable failed for apll_int, ret = -13
[    1.917973] loop: module loaded
[    1.919032] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.926900] m25p80 spi0.0: SPI-NOR-UniqueID 1044007e6a95001607001100c556ee23cb
[    1.932039] m25p80 spi0.0: found n25q512a, expected m25p80
[    1.937721] m25p80 spi0.0: n25q512a (131072 Kbytes)
[    1.942343] 5 ofpart partitions found on MTD device spi0.0
[    1.947782] Creating 5 MTD partitions on "spi0.0":
[    1.952546] 0x000000000000-0x000001e00000 : "boot"
[    1.957795] 0x000001e00000-0x000001e40000 : "bootenv"
[    1.962755] 0x000001e40000-0x000004240000 : "kernel"
[    1.967733] 0x000004240000-0x000007120000 : "jffs2"
[    1.972521] 0x000007120000-0x000007140000 : "spare"
[    1.978289] libphy: Fixed MDIO Bus: probed
[    1.982067] tun: Universal TUN/TAP device driver, 1.6
[    1.986259] CAN device driver interface
[    1.991310] macb ff0e0000.ethernet: Not enabling partial store and forward
[    1.996727] macb ff0e0000.ethernet: invalid hw address, using random
[    2.003478] libphy: MACB_mii_bus: probed
[    2.007435] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 29 (ca:64:a1:11:90:d1)
[    2.016714] TI DP83867 ff0e0000.ethernet-ffffffff:0c: attached PHY driver [TI DP83867] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:0c, irq=POLL)
[    2.030203] usbcore: registered new interface driver asix
[    2.035099] usbcore: registered new interface driver ax88179_178a
[    2.041141] usbcore: registered new interface driver cdc_ether
[    2.046941] usbcore: registered new interface driver net1080
[    2.052570] usbcore: registered new interface driver cdc_subset
[    2.058459] usbcore: registered new interface driver zaurus
[    2.064007] usbcore: registered new interface driver cdc_ncm
[    2.069873] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    2.076261] usbcore: registered new interface driver uas
[    2.081152] usbcore: registered new interface driver usb-storage
[    2.087554] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[    2.094332] i2c /dev entries driver
[    2.098419] IR NEC protocol handler initialized
[    2.102250] IR RC5(x/sz) protocol handler initialized
[    2.107270] IR RC6 protocol handler initialized
[    2.111773] IR JVC protocol handler initialized
[    2.116274] IR Sony protocol handler initialized
[    2.120864] IR SANYO protocol handler initialized
[    2.125539] IR Sharp protocol handler initialized
[    2.130215] IR MCE Keyboard/mouse protocol handler initialized
[    2.136019] IR XMP protocol handler initialized
[    2.141175] usbcore: registered new interface driver uvcvideo
[    2.146235] USB Video Class driver (1.1.1)
[    2.150856] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer at ffffff80092f5000 with timeout 60s
[    2.159371] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer at ffffff80092fd000 with timeout 10s
[    2.168307] Bluetooth: HCI UART driver ver 2.3
[    2.172561] Bluetooth: HCI UART protocol H4 registered
[    2.177665] Bluetooth: HCI UART protocol BCSP registered
[    2.182946] Bluetooth: HCI UART protocol ATH3K registered
[    2.188315] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    2.194583] Bluetooth: HCI UART protocol Intel registered
[    2.199919] Bluetooth: HCI UART protocol QCA registered
[    2.205143] usbcore: registered new interface driver bcm203x
[    2.210767] usbcore: registered new interface driver bpa10x
[    2.216309] usbcore: registered new interface driver bfusb
[    2.221765] usbcore: registered new interface driver btusb
[    2.227193] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    2.232863] usbcore: registered new interface driver ath3k
[    2.238681] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1188000 KHz
[    2.245682] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 1199999 KHz
[    2.254392] sdhci: Secure Digital Host Controller Interface driver
[    2.260270] sdhci: Copyright(c) Pierre Ossman
[    2.264598] sdhci-pltfm: SDHCI platform and OF driver helper
[    2.270467] ledtrig-cpu: registered to indicate activity on CPUs
[    2.276335] usbcore: registered new interface driver usbhid
[    2.281743] usbhid: USB HID core driver
[    2.290076] axi_sysid 85000000.axi-sysid-0: [grand] on [zu7cg] git <8c239d78f3c9f23c50c1644acfeac4bd1fb4f9b5> clean [2020-04-07 06:13:18] UTC
[    2.298547] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    2.305365] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    2.312243] Netfilter messages via NETLINK v0.30.
[    2.316941] ip_tables: (C) 2000-2006 Netfilter Core Team
[    2.322207] Initializing XFRM netlink socket
[    2.326400] NET: Registered protocol family 10
[    2.331174] Segment Routing with IPv6
[    2.334428] ip6_tables: (C) 2000-2006 Netfilter Core Team
[    2.339860] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    2.345961] NET: Registered protocol family 17
[    2.350070] NET: Registered protocol family 15
[    2.354487] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[    2.367377] Ebtables v2.0 registered
[    2.371000] can: controller area network core (rev 20170425 abi 9)
[    2.377107] NET: Registered protocol family 29
[    2.381492] can: raw protocol (rev 20170425)
[    2.385733] can: broadcast manager protocol (rev 20170425 t)
[    2.391364] can: netlink gateway (rev 20170425) max_hops=1
[    2.396960] Bluetooth: RFCOMM TTY layer initialized
[    2.401673] Bluetooth: RFCOMM socket layer initialized
[    2.406780] Bluetooth: RFCOMM ver 1.11
[    2.410500] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    2.415783] Bluetooth: BNEP filters: protocol multicast
[    2.420976] Bluetooth: BNEP socket layer initialized
[    2.425909] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    2.431800] Bluetooth: HIDP socket layer initialized
[    2.436842] 9pnet: Installing 9P2000 support
[    2.440988] Key type dns_resolver registered
[    2.445629] registered taskstats version 1
[    2.449626] Btrfs loaded, crc32c=crc32c-generic
�    2.458779] f�&����ꁛ��ͽ�������AM���/������5R��r����ꁟ��ͽ�������AM���*������5zځ��r���ʢ����э��ͽ�����������3�ͅ����5R��r���ʢ����э��ͽ���ڍ��������ͅ����5R��r���ʚ���9�������r��ɥ������AMŃ
                                           с5%=��™�������BJ�Ł���b�͕}��Ց���������JJ́���Յ����5R�[    2.564101] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 31
[    2.570578] ad9680 spi1.0: Unrecognized CHIP_ID 0xDB
[    2.576941] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    2.583867] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01 00:00:14 UTC (14)
[    2.592163] clk: Not disabling unused clocks
[    2.596624] ALSA device list:
[    2.599580]   No soundcards found.
[    2.731273] random: crng init done
[    3.519420] jffs2: notice: (1) jffs2_build_xattr_subsystem: complete building xattr subsystem, 0 of xdatum (0 unchecked, 0 orphan) and 0 of xref (0 dead, 0 orphan) found.
[    3.536733] VFS: Mounted root (jffs2 filesystem) on device 31:3.
[    3.542990] devtmpfs: mounted
[    3.546134] Freeing unused kernel memory: 512K
INIT: version 2.88 booting
Starting udev
[    4.453479] udevd[1724]: starting version 3.2.2
[    4.520566] udevd[1725]: starting eudev-3.2.2
Fri Mar 27 01:08:09 UTC 2020
Starting internet superserver: inetd.
INIT: Entering runlevel: 5
Configuring network interfaces... [    5.488629] pps pps0: new PPS source ptp0
[    5.492655] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[    5.499333] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
udhcpc: started, v1.27.2
udhcpc: sending discover
[    5.867778] PLL: shutdown
udhcpc: sending discover
udhcpc: sending discover
udhcpc: no lease, forking to background
done.
Starting system message bus: dbus.
Starting Dropbear SSH server: dropbear.
Starting IIO Daemon: iiod
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2018.3 grand17mrt /dev/ttyPS0

grand17mrt login: root
Password:
root@grand17mrt:~# iio_info
Library version: 0.18 (git tag: v0.18)
Compiled with backends: local xml ip usb
IIO context created with local backend.
Backend version: 0.18 (git tag: v0.18)
Backend description string: Linux grand17mrt 4.14.0-xilinx- #1 SMP Wed Apr 15 07:22:26 UTC 2020 aarch64
IIO context has 1 attributes:
	local,kernel: 4.14.0-xilinx-
IIO context has 2 devices:
	iio:device0: ams
		30 channels found:
			temp1: remote_temp (input)
			3 channel-specific attributes found:
				attr  0: offset value: -36058
				attr  1: raw value: 42332
				attr  2: scale value: 7.771514892
			voltage14: vccpsio2 (input)
			2 channel-specific attributes found:
				attr  0: raw value: 19485
				attr  1: scale value: 0.091552734
			voltage0: vcc_pspll0 (input)
			2 channel-specific attributes found:
				attr  0: raw value: 26191
				attr  1: scale value: 0.045776367
			voltage11: vccpsio3 (input)
			2 channel-specific attributes found:
				attr  0: raw value: 19741
				attr  1: scale value: 0.091552734
			voltage1: vcc_psbatt (input)
			2 channel-specific attributes found:
				attr  0: raw value: 4721
				attr  1: scale value: 0.045776367
			voltage15: psmgtravcc (input)
			2 channel-specific attributes found:
				attr  0: raw value: 0
				attr  1: scale value: 0.045776367
			voltage18: vccint (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18459
				attr  1: scale value: 0.045776367
			voltage7: vccpsintlp (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18421
				attr  1: scale value: 0.045776367
			voltage2: vccint (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18388
				attr  1: scale value: 0.045776367
			temp0: ps_temp (input)
			3 channel-specific attributes found:
				attr  0: offset value: -36058
				attr  1: raw value: 42226
				attr  2: scale value: 7.771514892
			voltage16: psmgtravtt (input)
			2 channel-specific attributes found:
				attr  0: raw value: 145
				attr  1: scale value: 0.045776367
			voltage12: vccpsio0 (input)
			2 channel-specific attributes found:
				attr  0: raw value: 19468
				attr  1: scale value: 0.091552734
			voltage6: vccpsintfpddr (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18544
				attr  1: scale value: 0.045776367
			voltage21: vccvrefn (input)
			2 channel-specific attributes found:
				attr  0: raw value: 0
				attr  1: scale value: 0.015258789
			voltage23: vccplintlp (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18380
				attr  1: scale value: 0.045776367
			voltage8: vccpsintfp (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18500
				attr  1: scale value: 0.045776367
			voltage4: vccaux (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39154
				attr  1: scale value: 0.045776367
			voltage25: vccplaux (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39551
				attr  1: scale value: 0.045776367
			voltage5: vcc_psddrpll (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39500
				attr  1: scale value: 0.045776367
			voltage9: vccpsaux (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39487
				attr  1: scale value: 0.045776367
			voltage19: vccaux (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39202
				attr  1: scale value: 0.045776367
			voltage22: vccbram (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18486
				attr  1: scale value: 0.045776367
			voltage20: vccvrefp (input)
			2 channel-specific attributes found:
				attr  0: raw value: 27328
				attr  1: scale value: 0.015258789
			voltage10: vccpsddr (input)
			2 channel-specific attributes found:
				attr  0: raw value: 26129
				attr  1: scale value: 0.045776367
			voltage13: vccpsio1 (input)
			2 channel-specific attributes found:
				attr  0: raw value: 19498
				attr  1: scale value: 0.091552734
			temp2: pl_temp (input)
			3 channel-specific attributes found:
				attr  0: offset value: -36058
				attr  1: raw value: 42252
				attr  2: scale value: 7.771514892
			voltage3: vccbram (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18455
				attr  1: scale value: 0.045776367
			voltage24: vccplintfp (input)
			2 channel-specific attributes found:
				attr  0: raw value: 18350
				attr  1: scale value: 0.045776367
			voltage17: vccams (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39332
				attr  1: scale value: 0.015258789
			voltage26: vccams (input)
			2 channel-specific attributes found:
				attr  0: raw value: 39095
				attr  1: scale value: 0.015258789
		1 device-specific attributes found:
				attr  0: sampling_frequency ERROR: Invalid argument (-22)
	iio_sysfs_trigger:
		0 channels found:
		2 device-specific attributes found:
				attr  0: add_trigger ERROR: Permission denied (-13)
				attr  1: remove_trigger ERROR: Permission denied (-13)
root@grand17mrt:~# ls -al /sys/bus/platform/devices/
total 0
drwxr-xr-x    2 root     root             0 Jan  1  1970 .
drwxr-xr-x    4 root     root             0 Jan  1  1970 ..
lrwxrwxrwx    1 root     root             0 Jan  1  1970 84a10000.axi-ad9694-hpc -> ../../../devices/platform/fpga-axi@0/84a10000.axi-ad9694-hpc
lrwxrwxrwx    1 root     root             0 Jan  1  1970 84a50000.axi-adxcvr-rx -> ../../../devices/platform/fpga-axi@0/84a50000.axi-adxcvr-rx
lrwxrwxrwx    1 root     root             0 Jan  1  1970 84aa0000.axi-jesd204-rx -> ../../../devices/platform/fpga-axi@0/84aa0000.axi-jesd204-rx
lrwxrwxrwx    1 root     root             0 Jan  1  1970 85000000.axi-sysid-0 -> ../../../devices/platform/fpga-axi@0/85000000.axi-sysid-0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 9c400000.rx-dmac -> ../../../devices/platform/fpga-axi@0/9c400000.rx-dmac
lrwxrwxrwx    1 root     root             0 Jan  1  1970 Fixed MDIO bus.0 -> ../../../devices/platform/Fixed MDIO bus.0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 alarmtimer -> ../../../devices/platform/alarmtimer
lrwxrwxrwx    1 root     root             0 Jan  1  1970 amba -> ../../../devices/platform/amba
lrwxrwxrwx    1 root     root             0 Jan  1  1970 amba_apu@0 -> ../../../devices/platform/amba_apu@0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 amba_pl@0 -> ../../../devices/platform/amba_pl@0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 clk -> ../../../devices/platform/clk
lrwxrwxrwx    1 root     root             0 Jan  1  1970 cpu_opp_table -> ../../../devices/platform/cpu_opp_table
lrwxrwxrwx    1 root     root             0 Jan  1  1970 cpufreq-dt -> ../../../devices/platform/cpufreq-dt
lrwxrwxrwx    1 root     root             0 Jan  1  1970 dcc -> ../../../devices/platform/dcc
lrwxrwxrwx    1 root     root             0 Jan  1  1970 edac -> ../../../devices/platform/edac
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fclk0 -> ../../../devices/platform/fclk0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd070000.memory-controller -> ../../../devices/platform/amba/fd070000.memory-controller
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd400000.zynqmp_phy -> ../../../devices/platform/amba/fd400000.zynqmp_phy
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd4d0000.watchdog -> ../../../devices/platform/amba/fd4d0000.watchdog
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd500000.dma -> ../../../devices/platform/amba/fd500000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd510000.dma -> ../../../devices/platform/amba/fd510000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd520000.dma -> ../../../devices/platform/amba/fd520000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd530000.dma -> ../../../devices/platform/amba/fd530000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd540000.dma -> ../../../devices/platform/amba/fd540000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd550000.dma -> ../../../devices/platform/amba/fd550000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd560000.dma -> ../../../devices/platform/amba/fd560000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd570000.dma -> ../../../devices/platform/amba/fd570000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd6e0000.cci -> ../../../devices/platform/amba/fd6e0000.cci
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fd6e9000.pmu -> ../../../devices/platform/amba/fd6e0000.cci/fd6e9000.pmu
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff000000.serial -> ../../../devices/platform/amba/ff000000.serial
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff010000.serial -> ../../../devices/platform/amba/ff010000.serial
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff020000.i2c -> ../../../devices/platform/amba/ff020000.i2c
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff040000.spi -> ../../../devices/platform/amba/ff040000.spi
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff0a0000.gpio -> ../../../devices/platform/amba/ff0a0000.gpio
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff0e0000.ethernet -> ../../../devices/platform/amba/ff0e0000.ethernet
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff0f0000.spi -> ../../../devices/platform/amba/ff0f0000.spi
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff150000.watchdog -> ../../../devices/platform/amba/ff150000.watchdog
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff180000.pinctrl -> ../../../devices/platform/amba/ff180000.pinctrl
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff960000.memory-controller -> ../../../devices/platform/amba/ff960000.memory-controller
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ff9905c0.mailbox -> ../../../devices/platform/ff9905c0.mailbox
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffa00000.perf-monitor -> ../../../devices/platform/amba/ffa00000.perf-monitor
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffa50000.ams -> ../../../devices/platform/amba/ffa50000.ams
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffa60000.rtc -> ../../../devices/platform/amba/ffa60000.rtc
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffa80000.dma -> ../../../devices/platform/amba/ffa80000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffa90000.dma -> ../../../devices/platform/amba/ffa90000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffaa0000.dma -> ../../../devices/platform/amba/ffaa0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffab0000.dma -> ../../../devices/platform/amba/ffab0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffac0000.dma -> ../../../devices/platform/amba/ffac0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffad0000.dma -> ../../../devices/platform/amba/ffad0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffae0000.dma -> ../../../devices/platform/amba/ffae0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 ffaf0000.dma -> ../../../devices/platform/amba/ffaf0000.dma
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fpga-axi@0 -> ../../../devices/platform/fpga-axi@0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 fpga-full -> ../../../devices/platform/fpga-full
lrwxrwxrwx    1 root     root             0 Jan  1  1970 gpio-keys -> ../../../devices/platform/gpio-keys
lrwxrwxrwx    1 root     root             0 Jan  1  1970 leds -> ../../../devices/platform/leds
lrwxrwxrwx    1 root     root             0 Jan  1  1970 nvmem_firmware -> ../../../devices/platform/nvmem_firmware
lrwxrwxrwx    1 root     root             0 Jan  1  1970 pcap -> ../../../devices/platform/pcap
lrwxrwxrwx    1 root     root             0 Jan  1  1970 pmu -> ../../../devices/platform/pmu
lrwxrwxrwx    1 root     root             0 Jan  1  1970 power-domains -> ../../../devices/platform/power-domains
lrwxrwxrwx    1 root     root             0 Jan  1  1970 psci -> ../../../devices/platform/psci
lrwxrwxrwx    1 root     root             0 Jan  1  1970 reg-dummy -> ../../../devices/platform/reg-dummy
lrwxrwxrwx    1 root     root             0 Jan  1  1970 regulatory.0 -> ../../../devices/platform/regulatory.0
lrwxrwxrwx    1 root     root             0 Jan  1  1970 reset-controller -> ../../../devices/platform/reset-controller
lrwxrwxrwx    1 root     root             0 Jan  1  1970 serial8250 -> ../../../devices/platform/serial8250
lrwxrwxrwx    1 root     root             0 Jan  1  1970 sha384 -> ../../../devices/platform/sha384
lrwxrwxrwx    1 root     root             0 Jan  1  1970 snd-soc-dummy -> ../../../devices/platform/snd-soc-dummy
lrwxrwxrwx    1 root     root             0 Jan  1  1970 timer -> ../../../devices/platform/timer
lrwxrwxrwx    1 root     root             0 Jan  1  1970 zynqmp-power -> ../../../devices/platform/zynqmp-power
lrwxrwxrwx    1 root     root             0 Jan  1  1970 zynqmp_aes -> ../../../devices/platform/zynqmp_aes
lrwxrwxrwx    1 root     root             0 Jan  1  1970 zynqmp_rsa -> ../../../devices/platform/zynqmp_rsa

root@grand17mrt:/sys/bus/platform/devices/84a50000.axi-adxcvr-rx# ls -la
total 0
drwxr-xr-x    3 root     root             0 Jan  1  1970 .
drwxr-xr-x    8 root     root             0 Jan  1  1970 ..
-rw-r--r--    1 root     root          4096 Mar 27 01:30 driver_override
-r--r--r--    1 root     root          4096 Mar 27 01:30 modalias
lrwxrwxrwx    1 root     root             0 Mar 27 01:30 of_node -> ../../../../firmware/devicetree/base/fpga-axi@0/axi-adxcvr-rx@84a50000
drwxr-xr-x    2 root     root             0 Mar 27 01:30 power
lrwxrwxrwx    1 root     root             0 Mar 27 01:30 subsystem -> ../../../../bus/platform
-rw-r--r--    1 root     root          4096 Jan  1  1970 uevent
root@grand17mrt:/sys/bus/platform/drivers# ls -al dma-axi-dmac/
total 0
drwxr-xr-x    2 root     root             0 Mar 27 01:21 .
drwxr-xr-x  123 root     root             0 Jan  1  1970 ..
lrwxrwxrwx    1 root     root             0 Mar 27 01:41 9c400000.rx-dmac -> ../../../../devices/platform/fpga-axi@0/9c400000.rx-dmac
--w-------    1 root     root          4096 Mar 27 01:41 bind
--w-------    1 root     root          4096 Mar 27 01:41 uevent
--w-------    1 root     root          4096 Mar 27 01:41 unbind
root@grand17mrt:/sys/bus/platform/drivers# ls -al axi_adxcvr/
total 0
drwxr-xr-x    2 root     root             0 Mar 27 01:26 .
drwxr-xr-x  123 root     root             0 Jan  1  1970 ..
--w-------    1 root     root          4096 Mar 27 01:26 bind
--w-------    1 root     root          4096 Mar 27 01:26 uevent
--w-------    1 root     root          4096 Mar 27 01:26 unbind
root@grand17mrt:/sys/bus/platform/drivers# ls -al axi-jesd204-rx/
total 0
drwxr-xr-x    2 root     root             0 Mar 27 01:26 .
drwxr-xr-x  123 root     root             0 Jan  1  1970 ..
--w-------    1 root     root          4096 Mar 27 01:26 bind
--w-------    1 root     root          4096 Mar 27 01:26 uevent
--w-------    1 root     root          4096 Mar 27 01:26 unbind
root@grand17mrt:/sys/bus/platform/drivers#

DEVICE TREE

/*
 * dts file from: FMCDAQ3 on Xilinx ZynqMP ZCU102 Rev 1.0
 *            to: GRANDproto_v1 Xilinx ZynqMP ZU7CG Rev 1.0
 *
 * Copyright (C) 2018 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/iio/frequency/ad9528.h>
#include "zynqmp-zcu102-rev1.0.dts"
/ {

    /* U-BOOT ARGUMENTS AND ROOTFS SETTINGS */
    chosen  {
        bootargs = "console=ttyPS0,115200 earlycon clk_ignore_unused root=/dev/mtdblock3 rw rootfstype=jffs2";
        stdout-path = "serial0:115200n8";
        xlnx,eeprom = &eeprom;
        };
    
    /* XTAL FOR Si5340 */
    xtal48MHz: xtal_48_clock {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
         clock-frequency = <48000000>;
    };

    /* AXI INTERFACE */
    fpga_axi: fpga-axi@0 {
        interrupt-parent = <&gic>;
        compatible = "simple-bus";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0 0 0 0xffffffff>;

        rx_dma: rx-dmac@9c400000 {
            #dma-cells = <1>;
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x9c400000 0x10000>;
            interrupts = <0 109 0>;
            clocks = <&clk 71>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <1>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <0>;
                };
            };
        };

        axi_ad9694_core: axi-ad9694-hpc@84a10000 {
            compatible = "adi,axi-ad9680-1.0";
            reg = <0x84a10000 0x10000>;
            dmas = <&rx_dma 0>;
            dma-names = "rx";
            spibus-connected = <&adc0_ad9694>;
        };

        axi_ad9694_jesd: axi-jesd204-rx@84aa0000 {
            compatible = "adi,axi-jesd204-rx-1.0";
            reg = <0x84aa0000 0x4000>;
            interrupts = <0 107 0>;

            clocks = <&clk 71>, <&axi_ad9694_adxcvr 1>, <&axi_ad9694_adxcvr 0>;
            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

            adi,octets-per-frame = <1>;
            adi,frames-per-multiframe = <32>;

            #clock-cells = <0>;
            clock-output-names = "jesd_adc_lane_clk";
        };

        axi_ad9694_adxcvr: axi-adxcvr-rx@84a50000 {
            compatible = "adi,axi-adxcvr-1.0";
            reg = <0x84a50000 0x1000>;

            clocks = <&si5340 0 2>;
            clock-names = "conv";
            
            adi,sys-clk-select = <0>;
            adi,out-clk-select = <4>;
            adi,use-lpm-enable;
            adi,use-cpll-enable;

            #clock-cells = <1>;
            clock-output-names = "adc_gt_clk", "rx_out_clk";
        };

        axi_sysid_0: axi-sysid-0@85000000 {
            compatible = "adi,axi-sysid-1.00.a";
            reg = <0x85000000 0x10000>;
        };
    };
};
/* END AXI INTERFACE */

&spi0 {
    status = "okay";
    num-cs = <1>;

    adc0_ad9694: ad9694@0 {
        compatible = "adi,ad9680";
        reg = <0>;
        spi-max-frequency = <10000000>;
        adi,spi-3wire-enable;
        spi-cpol;
        spi-cpha;

        /* gpio =       78 + 38||35||34 */
        powerdown-gpios = <&gpio 116 0>;
        fastdetect-a-gpios = <&gpio 113 0>;
        fastdetect-b-gpios = <&gpio 114 0>;
    
        clocks =  <&axi_ad9694_jesd>, <&si5340 1 3>;
        clock-names = "jesd_adc_clk", "adc_clk";
        /*assigned-clock-parents = <&si5340 1 3>; */
        /*assigned-clock-rates   = <1000000000>;  */
    };
};

&qspi {
    status = "okay";
    is-dual = <1>;
    has-io-mode = <1>;
    /delete-node/ flash@0;
    flash@0 {
        compatible = "micron,m25p80", "spi-flash", "n25q512a"; /* dual 512Mb, 1Gb total */
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        reg = <0x0>;
        spi-tx-bus-width = <0x1>;
        spi-rx-bus-width = <0x4>; 
        spi-max-frequency = <0x66ff300>; 
        partition@boot {
            label = "boot";
            reg = <0x0 0x1e00000>;
        };
        partition@bootenv {
            label = "bootenv";
            reg = <0x1e00000 0x40000>;
        };
        partition@kernel {
            label = "kernel";
            reg = <0x1e40000 0x2400000>;
        };
        partition@jffs2 {
            label = "jffs2";
            reg = <0x4240000 0x2EE0000>;
        };
        partition@spare {
            label = "spare";
            reg = <0x7120000 0x20000>;
        };      
    };
};


/* I2C0 BUS */
&i2c0 {
    status = "okay";
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c0_default>;
    pinctrl-1 = <&pinctrl_i2c0_gpio>;
    scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
    sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
    /delete-node/ gpio@20;
    /delete-node/ gpio@21;
    /delete-node/ i2c-mux@75;

    /* EEPROM */
    eeprom: eeprom@34 {
        compatible = "atmel,24c08";
        pagesize = <32>;
        #address-cells = <1>;
        #size-cells = <1>;
        reg = <0x34>;
    };

    /* Programmable clock */
    si5340: si5340@76 {
        reg = <0x76>;
        compatible = "silabs,si5340";
        #clock-cells = <2>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&xtal48MHz>;
        clock-names = "xtal";

        silabs,pll-m-num = <13600>; /* PLL at 13.6 GHz */
        silabs,pll-m-den = <48>;
        silabs,reprogram; /* Chips are not programmed, always reset */

        assigned-clocks = <&si5340 1 0>,
                          <&si5340 1 1>,
                          <&si5340 1 2>,
                          <&si5340 1 3>,
                          <&si5340 1 4>,
                          <&si5340 0 0>,
                          <&si5340 0 1>,
                          <&si5340 0 2>,
                          <&si5340 0 3>;
        assigned-clock-parents = <0>, <0>, <0>, <0>, <0>,
                          <&si5340 1 3>,
                          <&si5340 1 2>,
                          <&si5340 1 4>,
                          <&si5340 1 1>,
                          <&si5340 1 1>,
                          <&si5340 1 0>,
                          <&si5340 1 0>,
                          <&si5340 1 0>,
                          <&si5340 1 3>,
                          <&si5340 1 0>;
        assigned-clock-rates =  <400000000>, /* synth 0 */
                          <594000000>,
                          <104000000>,
                          <0>,
                          <594000000>,
                          <27000000>, /* out 0 */
                          <300000000>,
                          <500000000>,
                          <1000000000>;
        out@0 {
            /* PS_REF_CLK (27MHz) */
            reg = <0>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            silabs,synth-master;            
            always-on; /* assigned-clocks does not enable, so do it here */
        };

        out@1 {
            /* PL_DDR_CLK (300MHz) */
            reg = <1>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            silabs,synth-master;
            always-on;
        };

        out@2 {
            /* MGTREFCLK0 HDMI TX refclk (500MHz) */
            reg = <2>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            silabs,synth-master;
            always-on;
        };

        out@3 {
            /* ADC_REF_CLK (1000MHz) */
            reg = <3>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };
    };

    /* MAXIM_PMBUS - 00 */
    u88: max15301@0A { /* u88 */
        compatible = "maxim,max15301";
        reg = <0x0A>;
    };
    u91: max15303@0B { /* u91 */
        compatible = "maxim,max15303";
        reg = <0x0B>;
    };
    u81: max15303@10 { /* u81 */
        compatible = "maxim,max15303";
        reg = <0x10>;
    };
    u79: max15301@13 { /* u79 */
        compatible = "maxim,max15301";
        reg = <0x13>;
    };
    u77: max15303@14 { /* u77 */
        compatible = "maxim,max15303";
        reg = <0x14>;
    };
    u75: max15303@15 { /* u75 */
        compatible = "maxim,max15303";
        reg = <0x15>;
    };
    u71: max15303@16 { /* u71 */
        compatible = "maxim,max15303";
        reg = <0x16>;
    };
    u73: max15303@17 { /* u73 */
        compatible = "maxim,max15303";
        reg = <0x17>;
    };
        u68: max15301@1a { /* u68 */
        compatible = "maxim,max15301";
        reg = <0x1a>;
    };
    u50: max15303@1d { /* u50 */
        compatible = "maxim,max15303";
        reg = <0x1d>;
    };
        u52: max20751@72 { /* u52 */
        compatible = "maxim,max20751";
        reg = <0x72>;
    };
    u54: max20751@73 { /* u54 */
        compatible = "maxim,max20751";
        reg = <0x73>;
    };
};
/*END I2C0 BUS */


/* DEVICE TREE DISABLES */
&i2c1 {
    status = "disabled";

        /delete-node/ i2c-mux@74;
        /delete-node/ i2c-mux@75;
};

&sdhci1 {
 status = "disabled";
};

&pcie {
 status = "disabled";
};

&sata {
 status = "disabled";
};

&can1 {
 status = "disabled";
};

&zynqmp_dpsub {
 status = "disabled";
};

&usb0 {
 status = "disabled";
};

&gpu {
 status = "disabled";
};

&xlnx_dpdma {
 status = "disabled";
};

&spi0 {
    status = "okay";
};

&spi1 {
    status = "disabled";
};


/* PINCTRL SETTINGS */
&pinctrl0 {
    status = "okay";
    pinctrl_i2c0_default: i2c0-default {
        mux {
            groups = "i2c0_3_grp";
            function = "i2c0";
        };

        conf {
            groups = "i2c0_3_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_default: i2c1-default {
        mux {
            groups = "i2c1_4_grp";
            function = "i2c1";
        };

        conf {
            groups = "i2c1_4_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_gpio: i2c1-gpio {
        mux {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };
    pinctrl_uart0_default: uart0-default {
        mux {
            groups = "uart0_4_grp";
            function = "uart0";
        };

        conf {
            groups = "uart0_4_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO18";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO19";
            bias-disable;
        };
    };

    pinctrl_uart1_default: uart1-default {
        mux {
            groups = "uart1_5_grp";
            function = "uart1";
        };

        conf {
            groups = "uart1_5_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO21";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO20";
            bias-disable;
        };
    };

    pinctrl_usb0_default: usb0-default {
        mux {
            groups = "usb0_0_grp";
            function = "usb0";
        };

        conf {
            groups = "usb0_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO52", "MIO53", "MIO55";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
                   "MIO60", "MIO61", "MIO62", "MIO63";
            bias-disable;
        };
    };

    pinctrl_gem3_default: gem3-default {
        mux {
            function = "ethernet3";
            groups = "ethernet3_0_grp";
        };

        conf {
            groups = "ethernet3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
                                    "MIO75";
            bias-high-impedance;
            low-power-disable;
        };

        conf-tx {
            pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
                                    "MIO69";
            bias-disable;
            low-power-enable;
        };

        mux-mdio {
            function = "mdio3";
            groups = "mdio3_0_grp";
        };

        conf-mdio {
            groups = "mdio3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };
    };

    pinctrl_can1_default: can1-default {
        mux {
            function = "can1";
            groups = "can1_6_grp";
        };

        conf {
            groups = "can1_6_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO25";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO24";
            bias-disable;
        };
    };

    pinctrl_sdhci1_default: sdhci1-default {
        mux {
            groups = "sdio1_0_grp";
            function = "sdio1";
        };

        conf {
            groups = "sdio1_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };

        mux-cd {
            groups = "sdio1_cd_0_grp";
            function = "sdio1_cd";
        };

        conf-cd {
            groups = "sdio1_cd_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-wp {
            groups = "sdio1_wp_0_grp";
            function = "sdio1_wp";
        };

        conf-wp {
            groups = "sdio1_wp_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_gpio_default: gpio-default {
        mux-sw {
            function = "gpio0";
            groups = "gpio0_22_grp", "gpio0_23_grp";
        };

        conf-sw {
            groups = "gpio0_22_grp", "gpio0_23_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-msp {
            function = "gpio0";
            groups = "gpio0_13_grp", "gpio0_38_grp";
        };

        conf-msp {
            groups = "gpio0_13_grp", "gpio0_38_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-pull-up {
            pins = "MIO22", "MIO23";
            bias-pull-up;
        };

        conf-pull-none {
            pins = "MIO13", "MIO38";
            bias-disable;
        };
    };
};

Hi Rene,

What version of petalinux/meta-adi branch are you using? So, the way to change/extend the devicetree is through system-user.dtsi. Note at the end of device-tree.bbappend we include the system dtsi at the end of the top devicetree. There, you should be able to delete the nodes you want as we do for example for all our pl-delete-nodes-* files (or change nodes). I would double check why is this failing since it could just be a problem in the your devicetree...

Your problem with the devicetree is the compatible string. So you are setting it to ad9680, and you have an ad9694 device. So the driver will read the id as 0xdb from the device and compare it against 0xc5 which is the expected for ad9680. You should use "adi,ad9694"...

- Nuno Sá

Can someone provide a handle on solving this problem? We are still stuck on the -22 error.

Can you provide more information about your use case?

Sample rate, JESD204 mode, how many lanes, ADCs, FPGA synthesis parameters, etc.

-Michael

To add on mhennerich comments. Your issue seems to be related with clocks configuration. You mentioned you are using the si5340 clock generator and it seems we don't have the driver for it in on our tree so which one are you using? Did you backported the driver in upstream kernel?

I never really played with clock default assignments so I might be wrong but AFAIU, there's a one to one relation between assigned-clocks, assigned-clock-parents and assigned-clock-rates which seems not to be the case in your devicetree. Maybe you should double check those configurations...

- Nuno Sá

Of the 4 available ADC's, 2 are configured following the HDL design for daq3 please have a look at our HDL git repo. This is a copy from the daq3 project (including the ZCU102 carrier) with the modifications for the GRAND project but follows the same setup as the Analog Devices HDL repo.

The ADC clock runs on 1GHz and the transceiver clock on 31.25MHz. Initialy this is 500MHz (configured in the Si5340 N.V.M.) but the driver sets it to 31.25MHz

Also the Analog Device repo meta-adi is adapted to our use case and can be found in the same repo at meta-adi.

I will make a clock diagram asap and post it, maybe that sorts things out.

Ok – using a 1GHz ADC clock will result in 10Gbps lane rate for L=2.

The AD9694 is a 500MHz 14-bit ADC, however using it out of spec in 8-bit (NP=8) mode clocking it 1GHz may work.

However, I think there is a different generic for almost the same ADC (AD9094), however tested for this mode operation.

Anyways this is not the main problem here. I think your project uses L=4.

But the diver configures for L=2.

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad9680.c#L1208

So the math needs to be changed:

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/adc/ad9680.c#L1139

Maybe you should have based your design on this:

https://github.com/analogdevicesinc/hdl/tree/master/projects/ad_fmclidar1_ebz

And then use this devicetree as a base:

https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-fmclidar1.dts

Also your link clock needs to be lane_rate/40. So for 10Gbps you need to provide a 250MHz clock.

In your configuration you could have used 500MHz and with adi,out-clk-select = <4>

And with the proper connection it would have done the div2 for you.

Anyways, enable debug information in the adxcvr driver, you get the -22 -EINVAL because with the GTH/CPLL reference clock provided the 10Gbps wasn’t possible.

In order to enable DEBUG add:

#define DEBUG

Before the first include and then rebuild your kernel.

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/jesd204/axi_adxcvr.c

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/jesd204/xilinx_transceiver.c

-Michael

RH: --> Do you understand why the link clock is changed from 500MHz (set in Si5340 chip) to 31.25MHz set by the driver?

Ok – using a 1GHz ADC clock will result in 10Gbps lane rate for L=2.
RH: --> You mean this L is defined in the driver (following your pointer below) my hardware should be set to use 4 lanes.

The AD9694 is a 500MHz 14-bit ADC, however using it out of spec in 8-bit (NP=8) mode clocking it 1GHz may work.
RH: --> My intention is to use the ADC in 14-bit mode. If it is set to 8-bit I have made a mistake, can you point me to this setting?

However, I think there is a different generic for almost the same ADC (AD9094), however tested for this mode operation.

Anyways this is not the main problem here. I think your project uses L=4.
But the diver configures for L=2.
github.com/.../ad9680.c
RH: --> Why is this the case? The ad9680 has 4 lanes available as well.

So the math needs to be changed:
github.com/.../ad9680.c

Maybe you should have based your design on this:
github.com/.../ad_fmclidar1_ebz
RH: --> Would you advise to change to this design at this point and why? To me it looks like the ad9680.c driver is prepared (tested?) to be used for the ad9694 ADC.

And then use this devicetree as a base:
github.com/.../zynqmp-zcu102-rev10-fmclidar1.dts

Also your link clock needs to be lane_rate/40. So for 10Gbps you need to provide a 250MHz clock.

In your configuration you could have used 500MHz and with adi,out-clk-select = <4>
RH: --> Ok, I will change it in the device tree.

And with the proper connection it would have done the div2 for you.

Anyways, enable debug information in the adxcvr driver, you get the -22 -EINVAL because with the GTH/CPLL reference clock provided the 10Gbps wasn’t possible.

In order to enable DEBUG add:
#define DEBUG
Before the first include and then rebuild your kernel.
github.com/.../axi_adxcvr.c
github.com/.../xilinx_transceiver.c
RH: --> Following the Xilinx Forum and adding the # define DEBUG in the drivers did not result in more information about the -22 error. Anything I am forgetting? The boot message remains the same: 

R_Hab said:

RH: --> My intention is to use the ADC in 14-bit mode. If it is set to 8-bit I have made a mistake, can you point me to this setting?

Can't tell for sure. I'm still waiting for your clock diagram, including the CCF phandles.

Maybe setting a different output influences this one. I'm not familiar with the SI5340 at all.

R_Hab said:

RH: --> You mean this L is defined in the driver (following your pointer below) my hardware should be set to use 4 lanes.

For the AD9694 case L and NP is hardcoded in the ad9680.c driver, take a look at the source. The device supports a large number of configurations, we picked one. There is an overhaul of these drivers on the way, to allow greater flexibility but this may take a few more months until we have converted all drivers.

R_Hab said:

RH: --> My intention is to use the ADC in 14-bit mode. If it is set to 8-bit I have made a mistake, can you point me to this setting?

The max rate is then 500 MSPS. Like I said above the configuration is hard-coded in the source. You need to revise the setup code for AD9694 in the ad9680.c driver file.

R_Hab said:

RH: --> Why is this the case? The ad9680 has 4 lanes available as well.

Yes L=4 is one of many possible configurations.

R_Hab said:

RH: --> Following the Xilinx Forum and adding the # define DEBUG in the drivers did not result in more information about the -22 error. Anything I am forgetting? The boot message remains the same: 

I assume you rebuild the kernel. The default log level might not print debug. After your kernel booted inspect your kernel messages using the dmesg command.

In theory -22 originates here:

https://github.com/analogdevicesinc/linux/blob/master/drivers/iio/jesd204/xilinx_transceiver.c#L424

And in cased you added DEBUG before the first include in this driver, you should have seen the:

dev_dbg(xcvr->dev,
"CPLL: failed to find setting for lane rate %u kHz with reference clock %u kHz\n",
lane_rate_khz, refclk_khz);

...debug messages. 

PDF

Thanks for your patience about the diagram. It took some time to get the terminology right. While making it I came across some peculiarities:

- My initial idea was to "quickly" check if one link was operational and then implement the second link. This does seem to match with some parameters in the driver. What would you suggest? First get one link working (with this version of the driver) or switch to two links and go for the four ADC over two links?

- Because the daq3 design only uses 1 SYNCIN going to the ADC the other one is not connected. This seems like a problem. Should I tie SYNCIN_AB and SYNC_CD together and connect it to the lane_clk coming from the axi_ad9694_jesd?  Does link 0 only become active if all SYNCIN (ABCD) inputs are connected?

- As a reply to NSA:

1. No I did not backport the driver I copied it from https://elixir.bootlin.com/linux/latest/source/drivers/clk/clk-si5341.c
2. Can you explain a bit more on what you mean with "there's a one to one relation between assigned-clocks, assigned-clock-parents and assigned-clock-rates"? My latest device tree I will attach below.

- Tomorrow I will try modifying the driver again.

GRAND Device tree 8 Jul 2020

/*
 * dts file from: FMCDAQ3 on Xilinx ZynqMP ZCU102 Rev 1.0
 *            to: GRANDproto_v1 Xilinx ZynqMP ZU7CG Rev 1.0
 *
 * Copyright (C) 2018 Analog Devices Inc.
 * Modified by R. Habraken: Radboud University Nijmegen
 *
 * Licensed under the GPL-2.
 */

/* i2c and axi-bus*/


#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/iio/frequency/ad9528.h>
#include "zynqmp-zcu102-rev1.0.dts"
/ {

    /* U-BOOT ARGUMENTS AND ROOTFS SETTINGS */
    chosen  {
        bootargs = "console=ttyPS0,115200 earlyprintk clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2";
        stdout-path = "serial0:115200n8";
        xlnx,eeprom = &eeprom;
        };
    
    /* XTAL FOR Si5340 */
    xtal48MHz: xtal_48_clock {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
         clock-frequency = <48000000>;
    };

    /* AXI INTERFACE */
    fpga_axi: fpga-axi@0 {
        interrupt-parent = <&gic>;
        compatible = "simple-bus";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0 0 0 0xffffffff>;

        rx_dma: rx-dmac@9c400000 {
            #dma-cells = <1>;
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x9c400000 0x10000>;
            interrupts = <0 109 0>;
            clocks = <&clk 71>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <1>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <0>;
                };
            };
        };

        axi_ad9694_core: axi-ad9694-hpc@84a10000 {
            compatible = "adi,axi-ad9694-1.0";
            reg = <0x84a10000 0x10000>;
            dmas = <&rx_dma 0>;
            dma-names = "rx";
            spibus-connected = <&adc0_ad9694>;
        };

        axi_ad9694_jesd: axi-jesd204-rx@84aa0000 {
            compatible = "adi,axi-jesd204-rx-1.0";
            reg = <0x84aa0000 0x4000>;
            interrupts = <0 107 0>;

            clocks = <&clk 71>, <&axi_ad9694_adxcvr 1>, <&axi_ad9694_adxcvr 0>;
            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

            adi,octets-per-frame = <1>;
            adi,frames-per-multiframe = <32>;

            #clock-cells = <0>;
            clock-output-names = "jesd_adc_lane_clk";
        };

        axi_ad9694_adxcvr: axi-adxcvr-rx@84a50000 {
            compatible = "adi,axi-adxcvr-1.0";
            reg = <0x84a50000 0x1000>;

            clocks = <&si5340 0 2>;
            clock-names = "conv";
            
            adi,sys-clk-select = <0>;
            adi,out-clk-select = <4>;
            adi,use-lpm-enable;
            adi,use-cpll-enable;

            #clock-cells = <1>;
            clock-output-names = "adc_gt_clk", "rx_out_clk";
        };

        axi_sysid_0: axi-sysid-0@85000000 {
            compatible = "adi,axi-sysid-1.00.a";
            reg = <0x85000000 0x10000>;
        };
    };
};
/* END AXI INTERFACE */


&spi0 {
    status = "okay";
    num-cs = <1>;

    adc0_ad9694: ad9694@0 {
        compatible = "adi,ad9694";
        reg = <0>;
        spi-max-frequency = <10000000>;
        adi,spi-3wire-enable;
        spi-cpol;
        spi-cpha;

        /* gpio =       78 + 38||35||34 */
        powerdown-gpios = <&gpio 116 0>;
        fastdetect-a-gpios = <&gpio 113 0>;
        fastdetect-b-gpios = <&gpio 114 0>;
    
        clocks =  <&axi_ad9694_jesd>, <&si5340 0 3>, <&si5340 0 2>;
        clock-names = "jesd_adc_clk", "adc_clk", "adc_sysref";
        /*assigned-clock-parents = <&si5340 1 3>; */
        /*assigned-clock-rates   = <1000000000>;  */
    };
};

&qspi {
    status = "okay";
    is-dual = <1>;
    has-io-mode = <1>;
    /delete-node/ flash@0;
    flash@0 {
        compatible = "micron,m25p80", "spi-flash", "n25q512a"; /* dual 512Mb, 1Gb total */
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        reg = <0x0>;
        spi-tx-bus-width = <0x1>;
        spi-rx-bus-width = <0x4>; 
        spi-max-frequency = <0x66ff300>; 
        partition@boot {
            label = "boot";
            reg = <0x0 0x1e00000>;
        };

        partition@bootenv {
            label = "bootenv";
            reg = <0x1e00000 0x40000>;
        };

        partition@kernel {
            label = "kernel";
            reg = <0x1e40000 0x2400000>;
        };

        partition@jffs2 {
            label = "jffs2";
            reg = <0x4240000 0x2EE0000>;
        };
        partition@spare {
            label = "spare";
            reg = <0x7120000 0x20000>;
        };      
    };
};


/* I2C0 BUS */
&i2c0 {
    status = "okay";
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c0_default>;
    pinctrl-1 = <&pinctrl_i2c0_gpio>;
    scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
    sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
    /delete-node/ gpio@20;
    /delete-node/ gpio@21;
    /delete-node/ i2c-mux@75;

    /* EEPROM */
    eeprom: eeprom@54 {
        compatible = "at,24c08","atmel,24c08";
        pagesize = <16>;
        reg = <0x54>;
    };

    /* Programmable clock */
    si5340: si5340@76 {
        reg = <0x76>;
        compatible = "silabs,si5340";
        #clock-cells = <2>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&xtal48MHz>;
        clock-names = "xtal";

        silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
        silabs,pll-m-den = <48>;

        assigned-clocks = <&si5340 1 0>,
                          <&si5340 1 1>,
                          <&si5340 1 2>,
                          <&si5340 1 3>,
                          <&si5340 0 0>,
                          <&si5340 0 1>,
                          <&si5340 0 2>,
                          <&si5340 0 3>;
        assigned-clock-parents = <0>, <0>, <0>, <0>,
                          <&si5340 1 1>, /* output 0 uses PLL 1 */
                          <&si5340 1 2>, /* output 1 uses PLL 2 */
                          <&si5340 1 0>, /* output 2 uses PLL 0 */
                          <&si5340 1 0>; /* output 3 uses PLL 0 */
        assigned-clock-rates = <2000000000>,
                          <162000000>,
                          <600000000>,
                          <0>,
                          <27000000>, /* out 0 */
                          <300000000>,
                          <500000000>, /*500 MHz */
                          <1000000000>;

        out@1 {
            /* PL_DDR_CLK (300MHz) */
            reg = <1>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@2 {
            /* MGTREFCLK0 RX refclk (500MHz) */
            reg = <2>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@3 {
            /* ADC_REF_CLK (1000MHz) */
            reg = <3>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };
    };

    /* MAXIM_PMBUS - 00 */
    u88: max15301@0A { /* u88 */
        compatible = "maxim,max15301";
        reg = <0x0A>;
    };
    u91: max15303@0B { /* u91 */
        compatible = "maxim,max15303";
        reg = <0x0B>;
    };
    u81: max15303@10 { /* u81 */
        compatible = "maxim,max15303";
        reg = <0x10>;
    };
    u79: max15301@13 { /* u79 */
        compatible = "maxim,max15301";
        reg = <0x13>;
    };
    u77: max15303@14 { /* u77 */
        compatible = "maxim,max15303";
        reg = <0x14>;
    };
    u75: max15303@15 { /* u75 */
        compatible = "maxim,max15303";
        reg = <0x15>;
    };
    u71: max15303@16 { /* u71 */
        compatible = "maxim,max15303";
        reg = <0x16>;
    };
    u73: max15303@17 { /* u73 */
        compatible = "maxim,max15303";
        reg = <0x17>;
    };
    u68: max15301@1a { /* u68 */
        compatible = "maxim,max15301";
        reg = <0x1a>;
    };
    u50: max15303@1d { /* u50 */
        compatible = "maxim,max15303";
        reg = <0x1d>;
    };
    u52: max20751@72 { /* u52 */
        compatible = "maxim,max20751";
        reg = <0x72>;
    };
    u54: max20751@73 { /* u54 */
        compatible = "maxim,max20751";
        reg = <0x73>;
    };
};
/*END I2C0 BUS */


/* DEVICE TREE DISABLES */
&i2c1 {
    status = "disabled";

        /delete-node/ i2c-mux@74;
        /delete-node/ i2c-mux@75;
};

&sdhci1 {
 status = "disabled";
};

&pcie {
 status = "disabled";
};

&sata {
 status = "disabled";
};

&can1 {
 status = "disabled";
};

&zynqmp_dpsub {
 status = "disabled";
};

&usb0 {
 status = "disabled";
};

&gpu {
 status = "disabled";
};

&xlnx_dpdma {
 status = "disabled";
};

&spi0 {
    status = "okay";
};

&spi1 {
    status = "disabled";
};

&uart0 {
    status = "okay";
};

&uart1 {
    status = "okay";
};

/* PINCTRL SETTINGS */
&pinctrl0 {
    status = "okay";
    pinctrl_i2c0_default: i2c0-default {
        mux {
            groups = "i2c0_3_grp";
            function = "i2c0";
        };

        conf {
            groups = "i2c0_3_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_default: i2c1-default {
        mux {
            groups = "i2c1_4_grp";
            function = "i2c1";
        };

        conf {
            groups = "i2c1_4_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_gpio: i2c1-gpio {
        mux {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };
    pinctrl_uart0_default: uart0-default {
        mux {
            groups = "uart0_4_grp";
            function = "uart0";
        };

        conf {
            groups = "uart0_4_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO18";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO19";
            bias-disable;
        };
    };

    pinctrl_uart1_default: uart1-default {
        mux {
            groups = "uart1_5_grp";
            function = "uart1";
        };

        conf {
            groups = "uart1_5_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO21";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO20";
            bias-disable;
        };
    };

    pinctrl_usb0_default: usb0-default {
        mux {
            groups = "usb0_0_grp";
            function = "usb0";
        };

        conf {
            groups = "usb0_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO52", "MIO53", "MIO55";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
                   "MIO60", "MIO61", "MIO62", "MIO63";
            bias-disable;
        };
    };

    pinctrl_gem3_default: gem3-default {
        mux {
            function = "ethernet3";
            groups = "ethernet3_0_grp";
        };

        conf {
            groups = "ethernet3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
                                    "MIO75";
            bias-high-impedance;
            low-power-disable;
        };

        conf-tx {
            pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
                                    "MIO69";
            bias-disable;
            low-power-enable;
        };

        mux-mdio {
            function = "mdio3";
            groups = "mdio3_0_grp";
        };

        conf-mdio {
            groups = "mdio3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };
    };

    pinctrl_can1_default: can1-default {
        mux {
            function = "can1";
            groups = "can1_6_grp";
        };

        conf {
            groups = "can1_6_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO25";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO24";
            bias-disable;
        };
    };

    pinctrl_sdhci1_default: sdhci1-default {
        mux {
            groups = "sdio1_0_grp";
            function = "sdio1";
        };

        conf {
            groups = "sdio1_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };

        mux-cd {
            groups = "sdio1_cd_0_grp";
            function = "sdio1_cd";
        };

        conf-cd {
            groups = "sdio1_cd_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-wp {
            groups = "sdio1_wp_0_grp";
            function = "sdio1_wp";
        };

        conf-wp {
            groups = "sdio1_wp_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_gpio_default: gpio-default {
        mux-sw {
            function = "gpio0";
            groups = "gpio0_22_grp", "gpio0_23_grp";
        };

        conf-sw {
            groups = "gpio0_22_grp", "gpio0_23_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-msp {
            function = "gpio0";
            groups = "gpio0_13_grp", "gpio0_38_grp";
        };

        conf-msp {
            groups = "gpio0_13_grp", "gpio0_38_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-pull-up {
            pins = "MIO22", "MIO23";
            bias-pull-up;
        };

        conf-pull-none {
            pins = "MIO13", "MIO38";
            bias-disable;
        };
    };
};

GRAND Device tree 8 Jul 2020

/*
 * dts file from: FMCDAQ3 on Xilinx ZynqMP ZCU102 Rev 1.0
 *            to: GRANDproto_v1 Xilinx ZynqMP ZU7CG Rev 1.0
 *
 * Copyright (C) 2018 Analog Devices Inc.
 * Modified by R. Habraken: Radboud University Nijmegen
 *
 * Licensed under the GPL-2.
 */

/* i2c and axi-bus*/


#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/iio/frequency/ad9528.h>
#include "zynqmp-zcu102-rev1.0.dts"
/ {

    /* U-BOOT ARGUMENTS AND ROOTFS SETTINGS */
    chosen  {
        bootargs = "console=ttyPS0,115200 earlyprintk clk_ignore_unused root=mtd:jffs2 rw rootfstype=jffs2";
        stdout-path = "serial0:115200n8";
        xlnx,eeprom = &eeprom;
        };
    
    /* XTAL FOR Si5340 */
    xtal48MHz: xtal_48_clock {
        compatible = "fixed-clock";
        #clock-cells = <0x0>;
         clock-frequency = <48000000>;
    };

    /* AXI INTERFACE */
    fpga_axi: fpga-axi@0 {
        interrupt-parent = <&gic>;
        compatible = "simple-bus";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        ranges = <0 0 0 0xffffffff>;

        rx_dma: rx-dmac@9c400000 {
            #dma-cells = <1>;
            compatible = "adi,axi-dmac-1.00.a";
            reg = <0x9c400000 0x10000>;
            interrupts = <0 109 0>;
            clocks = <&clk 71>;

            adi,channels {
                #size-cells = <0>;
                #address-cells = <1>;

                dma-channel@0 {
                    reg = <0>;
                    adi,source-bus-width = <64>;
                    adi,source-bus-type = <1>;
                    adi,destination-bus-width = <64>;
                    adi,destination-bus-type = <0>;
                };
            };
        };

        axi_ad9694_core: axi-ad9694-hpc@84a10000 {
            compatible = "adi,axi-ad9694-1.0";
            reg = <0x84a10000 0x10000>;
            dmas = <&rx_dma 0>;
            dma-names = "rx";
            spibus-connected = <&adc0_ad9694>;
        };

        axi_ad9694_jesd: axi-jesd204-rx@84aa0000 {
            compatible = "adi,axi-jesd204-rx-1.0";
            reg = <0x84aa0000 0x4000>;
            interrupts = <0 107 0>;

            clocks = <&clk 71>, <&axi_ad9694_adxcvr 1>, <&axi_ad9694_adxcvr 0>;
            clock-names = "s_axi_aclk", "device_clk", "lane_clk";

            adi,octets-per-frame = <1>;
            adi,frames-per-multiframe = <32>;

            #clock-cells = <0>;
            clock-output-names = "jesd_adc_lane_clk";
        };

        axi_ad9694_adxcvr: axi-adxcvr-rx@84a50000 {
            compatible = "adi,axi-adxcvr-1.0";
            reg = <0x84a50000 0x1000>;

            clocks = <&si5340 0 2>;
            clock-names = "conv";
            
            adi,sys-clk-select = <0>;
            adi,out-clk-select = <4>;
            adi,use-lpm-enable;
            adi,use-cpll-enable;

            #clock-cells = <1>;
            clock-output-names = "adc_gt_clk", "rx_out_clk";
        };

        axi_sysid_0: axi-sysid-0@85000000 {
            compatible = "adi,axi-sysid-1.00.a";
            reg = <0x85000000 0x10000>;
        };
    };
};
/* END AXI INTERFACE */


&spi0 {
    status = "okay";
    num-cs = <1>;

    adc0_ad9694: ad9694@0 {
        compatible = "adi,ad9694";
        reg = <0>;
        spi-max-frequency = <10000000>;
        adi,spi-3wire-enable;
        spi-cpol;
        spi-cpha;

        /* gpio =       78 + 38||35||34 */
        powerdown-gpios = <&gpio 116 0>;
        fastdetect-a-gpios = <&gpio 113 0>;
        fastdetect-b-gpios = <&gpio 114 0>;
    
        clocks =  <&axi_ad9694_jesd>, <&si5340 0 3>, <&si5340 0 2>;
        clock-names = "jesd_adc_clk", "adc_clk", "adc_sysref";
        /*assigned-clock-parents = <&si5340 1 3>; */
        /*assigned-clock-rates   = <1000000000>;  */
    };
};

&qspi {
    status = "okay";
    is-dual = <1>;
    has-io-mode = <1>;
    /delete-node/ flash@0;
    flash@0 {
        compatible = "micron,m25p80", "spi-flash", "n25q512a"; /* dual 512Mb, 1Gb total */
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        reg = <0x0>;
        spi-tx-bus-width = <0x1>;
        spi-rx-bus-width = <0x4>; 
        spi-max-frequency = <0x66ff300>; 
        partition@boot {
            label = "boot";
            reg = <0x0 0x1e00000>;
        };

        partition@bootenv {
            label = "bootenv";
            reg = <0x1e00000 0x40000>;
        };

        partition@kernel {
            label = "kernel";
            reg = <0x1e40000 0x2400000>;
        };

        partition@jffs2 {
            label = "jffs2";
            reg = <0x4240000 0x2EE0000>;
        };
        partition@spare {
            label = "spare";
            reg = <0x7120000 0x20000>;
        };      
    };
};


/* I2C0 BUS */
&i2c0 {
    status = "okay";
    clock-frequency = <400000>;
    pinctrl-names = "default", "gpio";
    pinctrl-0 = <&pinctrl_i2c0_default>;
    pinctrl-1 = <&pinctrl_i2c0_gpio>;
    scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
    sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
    /delete-node/ gpio@20;
    /delete-node/ gpio@21;
    /delete-node/ i2c-mux@75;

    /* EEPROM */
    eeprom: eeprom@54 {
        compatible = "at,24c08","atmel,24c08";
        pagesize = <16>;
        reg = <0x54>;
    };

    /* Programmable clock */
    si5340: si5340@76 {
        reg = <0x76>;
        compatible = "silabs,si5340";
        #clock-cells = <2>;
        #address-cells = <1>;
        #size-cells = <0>;
        clocks = <&xtal48MHz>;
        clock-names = "xtal";

        silabs,pll-m-num = <14000>; /* PLL at 14.0 GHz */
        silabs,pll-m-den = <48>;

        assigned-clocks = <&si5340 1 0>,
                          <&si5340 1 1>,
                          <&si5340 1 2>,
                          <&si5340 1 3>,
                          <&si5340 0 0>,
                          <&si5340 0 1>,
                          <&si5340 0 2>,
                          <&si5340 0 3>;
        assigned-clock-parents = <0>, <0>, <0>, <0>,
                          <&si5340 1 1>, /* output 0 uses PLL 1 */
                          <&si5340 1 2>, /* output 1 uses PLL 2 */
                          <&si5340 1 0>, /* output 2 uses PLL 0 */
                          <&si5340 1 0>; /* output 3 uses PLL 0 */
        assigned-clock-rates = <2000000000>,
                          <162000000>,
                          <600000000>,
                          <0>,
                          <27000000>, /* out 0 */
                          <300000000>,
                          <500000000>, /*500 MHz */
                          <1000000000>;

        out@1 {
            /* PL_DDR_CLK (300MHz) */
            reg = <1>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@2 {
            /* MGTREFCLK0 RX refclk (500MHz) */
            reg = <2>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };

        out@3 {
            /* ADC_REF_CLK (1000MHz) */
            reg = <3>;
            silabs,format = <1>; /* LVDS 3v3 */
            silabs,common-mode = <3>;
            silabs,amplitude = <3>;
            always-on;
        };
    };

    /* MAXIM_PMBUS - 00 */
    u88: max15301@0A { /* u88 */
        compatible = "maxim,max15301";
        reg = <0x0A>;
    };
    u91: max15303@0B { /* u91 */
        compatible = "maxim,max15303";
        reg = <0x0B>;
    };
    u81: max15303@10 { /* u81 */
        compatible = "maxim,max15303";
        reg = <0x10>;
    };
    u79: max15301@13 { /* u79 */
        compatible = "maxim,max15301";
        reg = <0x13>;
    };
    u77: max15303@14 { /* u77 */
        compatible = "maxim,max15303";
        reg = <0x14>;
    };
    u75: max15303@15 { /* u75 */
        compatible = "maxim,max15303";
        reg = <0x15>;
    };
    u71: max15303@16 { /* u71 */
        compatible = "maxim,max15303";
        reg = <0x16>;
    };
    u73: max15303@17 { /* u73 */
        compatible = "maxim,max15303";
        reg = <0x17>;
    };
    u68: max15301@1a { /* u68 */
        compatible = "maxim,max15301";
        reg = <0x1a>;
    };
    u50: max15303@1d { /* u50 */
        compatible = "maxim,max15303";
        reg = <0x1d>;
    };
    u52: max20751@72 { /* u52 */
        compatible = "maxim,max20751";
        reg = <0x72>;
    };
    u54: max20751@73 { /* u54 */
        compatible = "maxim,max20751";
        reg = <0x73>;
    };
};
/*END I2C0 BUS */


/* DEVICE TREE DISABLES */
&i2c1 {
    status = "disabled";

        /delete-node/ i2c-mux@74;
        /delete-node/ i2c-mux@75;
};

&sdhci1 {
 status = "disabled";
};

&pcie {
 status = "disabled";
};

&sata {
 status = "disabled";
};

&can1 {
 status = "disabled";
};

&zynqmp_dpsub {
 status = "disabled";
};

&usb0 {
 status = "disabled";
};

&gpu {
 status = "disabled";
};

&xlnx_dpdma {
 status = "disabled";
};

&spi0 {
    status = "okay";
};

&spi1 {
    status = "disabled";
};

&uart0 {
    status = "okay";
};

&uart1 {
    status = "okay";
};

/* PINCTRL SETTINGS */
&pinctrl0 {
    status = "okay";
    pinctrl_i2c0_default: i2c0-default {
        mux {
            groups = "i2c0_3_grp";
            function = "i2c0";
        };

        conf {
            groups = "i2c0_3_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_default: i2c1-default {
        mux {
            groups = "i2c1_4_grp";
            function = "i2c1";
        };

        conf {
            groups = "i2c1_4_grp";
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c1_gpio: i2c1-gpio {
        mux {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_16_grp", "gpio0_17_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_i2c0_gpio: i2c0-gpio {
        mux {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            function = "gpio0";
        };

        conf {
            groups = "gpio0_14_grp", "gpio0_15_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };
    pinctrl_uart0_default: uart0-default {
        mux {
            groups = "uart0_4_grp";
            function = "uart0";
        };

        conf {
            groups = "uart0_4_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO18";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO19";
            bias-disable;
        };
    };

    pinctrl_uart1_default: uart1-default {
        mux {
            groups = "uart1_5_grp";
            function = "uart1";
        };

        conf {
            groups = "uart1_5_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO21";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO20";
            bias-disable;
        };
    };

    pinctrl_usb0_default: usb0-default {
        mux {
            groups = "usb0_0_grp";
            function = "usb0";
        };

        conf {
            groups = "usb0_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO52", "MIO53", "MIO55";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
                   "MIO60", "MIO61", "MIO62", "MIO63";
            bias-disable;
        };
    };

    pinctrl_gem3_default: gem3-default {
        mux {
            function = "ethernet3";
            groups = "ethernet3_0_grp";
        };

        conf {
            groups = "ethernet3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
                                    "MIO75";
            bias-high-impedance;
            low-power-disable;
        };

        conf-tx {
            pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
                                    "MIO69";
            bias-disable;
            low-power-enable;
        };

        mux-mdio {
            function = "mdio3";
            groups = "mdio3_0_grp";
        };

        conf-mdio {
            groups = "mdio3_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };
    };

    pinctrl_can1_default: can1-default {
        mux {
            function = "can1";
            groups = "can1_6_grp";
        };

        conf {
            groups = "can1_6_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-rx {
            pins = "MIO25";
            bias-high-impedance;
        };

        conf-tx {
            pins = "MIO24";
            bias-disable;
        };
    };

    pinctrl_sdhci1_default: sdhci1-default {
        mux {
            groups = "sdio1_0_grp";
            function = "sdio1";
        };

        conf {
            groups = "sdio1_0_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
            bias-disable;
        };

        mux-cd {
            groups = "sdio1_cd_0_grp";
            function = "sdio1_cd";
        };

        conf-cd {
            groups = "sdio1_cd_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-wp {
            groups = "sdio1_wp_0_grp";
            function = "sdio1_wp";
        };

        conf-wp {
            groups = "sdio1_wp_0_grp";
            bias-high-impedance;
            bias-pull-up;
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };
    };

    pinctrl_gpio_default: gpio-default {
        mux-sw {
            function = "gpio0";
            groups = "gpio0_22_grp", "gpio0_23_grp";
        };

        conf-sw {
            groups = "gpio0_22_grp", "gpio0_23_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        mux-msp {
            function = "gpio0";
            groups = "gpio0_13_grp", "gpio0_38_grp";
        };

        conf-msp {
            groups = "gpio0_13_grp", "gpio0_38_grp";
            slew-rate = <SLEW_RATE_SLOW>;
            io-standard = <IO_STANDARD_LVCMOS18>;
        };

        conf-pull-up {
            pins = "MIO22", "MIO23";
            bias-pull-up;
        };

        conf-pull-none {
            pins = "MIO13", "MIO38";
            bias-disable;
        };
    };
};

Hey,

What I mean is that for example line 8 of assigned-clocks (<&si5340 0 3>;) will be have as a parent "<&si5340 1 0>;" and will be set at 500MHz at boot. So there's one-to-one relation between each line of the properties. I can be wrong, but in your previous devicetree it looked that there were some mistakes/oddities. In this new devicetree things look better...

- Nuno Sá

You are right indeed, the previous DT contained some errors. The reason for the missing debug info was the LOGLEVEL_DEFAULT config as Michael suggested. Thanks guys! I have some more info now, hopefully this shows the way forward :-).

udevd[1725]: starting version 3.2.2
udevd[1726]: starting eudev-3.2.2
si5341: loading out-of-tree module taints kernel.
si5341 0-0076: Chip: 5340 Grade: 0 Rev: 3
ad9680 spi1.0: ad9680_spi_read: REG: 0x4 VAL: 0xDB (0)
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8096
axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
cpll: fb_div_N2=2
cpll: refclk_div=1
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: CPLL: failed to find setting for lane rate 10000000 kHz with reference clock 500000 kHz
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8096
axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
cpll: fb_div_N2=2
cpll: refclk_div=1
axi_adxcvr 84a50000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using GTH4 at 0x84A50000 mapped to 0xffffff800936d000. Number of lanes: 4.
ad9680 spi1.0: ad9680_spi_read: REG: 0x4 VAL: 0xDB (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x0 VAL: 0x81 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x9 VAL: 0x3 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x8 VAL: 0x3 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x108 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x580 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x581 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x570 VAL: 0x48 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x583 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x5B2 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x584 VAL: 0x1 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x5B3 VAL: 0x11 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x58B VAL: 0x81 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x58D VAL: 0x1F (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x58F VAL: 0x7 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x590 VAL: 0x27 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x120 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x121 VAL: 0xF (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x120 VAL: 0xC (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1 VAL: 0x2 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x56E VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1228 VAL: 0x4F (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1228 VAL: 0xF (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1222 VAL: 0x4 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1222 VAL: 0x0 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1262 VAL: 0x8 (0)
ad9680 spi1.0: ad9680_spi_write: REG: 0x1262 VAL: 0x0 (0)
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 31250000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8096
axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
cpll: fb_div_N2=2
cpll: refclk_div=1
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 625000 Hz Parent Rate 31250000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: CPLL: failed to find setting for lane rate 625000 kHz with reference clock 31250 kHz
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 31250000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8096
axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
cpll: fb_div_N2=2
cpll: refclk_div=1
axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_round_rate: Rate 10000000 Hz Parent Rate 31250000 Hz
axi_adxcvr 84a50000.axi-adxcvr-rx: CPLL: failed to find setting for lane rate 10000000 kHz with reference clock 31250 kHz
ad9680 spi1.0: Failed to set lane rate to 10000000 kHz: -22
ad9680 spi1.0: Failed to initialize: -22
ad9680: probe of spi1.0 failed with error -22

This is unexpected –

I tried a similar configuration CPLL reference 500MHz and lane rate 10Gbps on a ZCU102 (GTH4)

And it succeeds both on master and 2019_R1. Did you make any modifications?

What fpga and speed grade are you using?

Master:
[    9.870605] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    9.870616] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    9.870750] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    9.872308] axi_adxcvr 84a50000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using GTH4 at 0x84A50000 mapped to 0x(____ptrval____). Number of lanes: 4.
[    9.885682] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    9.885692] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_set_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    9.885754] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    9.886111] axi_adxcvr 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using GTH4 at 0x84A60000 mapped to 0x(____ptrval____). Number of lanes: 4.
[    9.928671] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_round_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    9.928679] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_enable: TX
[    9.979336] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_round_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    9.999586] ad9680 spi1.2: AD9680 PLL LOCKED
[   10.003866] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_enable: RX
[   10.028102] cf_axi_adc 84a10000.axi-ad9680-hpc: ADI AIM (10.01.b) at 0x84A10000 mapped to 0x(____ptrval____), probed ADC AD9680 as MASTER
[   10.061969] cf_axi_dds 84a04000.axi-ad9144-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0x(____ptrval____), probed DDS AD9144

2019_R1:
[    4.477964] ad9523 spi1.0: probed ad9523-1
[    4.509657] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    4.509664] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    4.509670] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
[    4.509676] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
[    4.509680] axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
[    4.509680] cpll: fb_div_N2=2
[    4.509680] cpll: refclk_div=1
[    4.509685] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    4.509691] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
[    4.509696] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x28, val 0x8A
[    4.509702] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
[    4.509707] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
[    4.509711] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x2A, val 0x8216
[    4.509717] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
[    4.509723] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    4.509727] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x63, val 0x80C0
[    4.509733] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    4.509739] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x349B
[    4.509744] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x6D, val 0x349B
[    4.509750] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x6D val 0x349B
[    4.509755] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x8A
[    4.509759] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x28, val 0x8A
[    4.509765] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x28 val 0x8A
[    4.509770] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
[    4.509775] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x2A, val 0x8216
[    4.509781] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x2A val 0x8216
[    4.509786] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
[    4.509790] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x63, val 0x80C0
[    4.509796] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x63 val 0x80C0
[    4.509801] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x349B
[    4.509806] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x6D, val 0x349B
[    4.509812] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x6D val 0x349B
[    4.509817] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x8A
[    4.509821] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x28, val 0x8A
[    4.509827] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x28 val 0x8A
[    4.509832] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
[    4.509836] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x2A, val 0x8216
[    4.509842] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x2A val 0x8216
[    4.509847] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x63 val 0x80C0
[    4.509852] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x63, val 0x80C0
[    4.509858] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x63 val 0x80C0
[    4.509863] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x6D val 0x349B
[    4.509867] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x6D, val 0x349B
[    4.509873] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x6D val 0x349B
[    4.509881] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x8A
[    4.509886] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x28, val 0x8A
[    4.509892] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x28 val 0x8A
[    4.509897] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
[    4.509901] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x2A, val 0x8216
[    4.509907] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x2A val 0x8216
[    4.509912] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x63 val 0x80C0
[    4.509917] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x63, val 0x80C0
[    4.509923] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x63 val 0x80C0
[    4.509928] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x6D val 0x349B
[    4.509932] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x6D, val 0x349B
[    4.509938] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x6D val 0x349B
[    4.509964] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    4.509969] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    4.509975] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x28 val 0x8A
[    4.509980] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x2A val 0x8216
[    4.509984] axi_adxcvr 84a50000.axi-adxcvr-rx: cpll: fb_div_N1=5
[    4.509984] cpll: fb_div_N2=2
[    4.509984] cpll: refclk_div=1
[    4.511313] axi_adxcvr 84a50000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using GTH4 at 0x84A50000 mapped to 0xffffff8009605000. Number of lanes: 4.
[    4.524560] mmc0: new SDHC card at address e624
[    4.529269] mmcblk0: mmc0:e624 SL08G 7.40 GiB 
[    4.534006] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    4.534013] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
[    4.534018] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    4.534024] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x12
[    4.534028] axi_adxcvr 84a60000.axi-adxcvr-tx: qpll: fb_div=20, qpll: refclk_div=1
[    4.534032] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_set_rate: Rate 10000000 Hz Parent Rate 500000000 Hz
[    4.534039] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x12
[    4.534043] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 0, reg 0x14, val 0x12
[    4.534050] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x12
[    4.534055] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    4.534059] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 0, reg 0x18, val 0x808
[    4.534065] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    4.534070] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
[    4.534075] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7C, val 0xE0
[    4.534081] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
[    4.534086] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x9805
[    4.534090] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 256, reg 0x7A, val 0x9805
[    4.534096] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7A val 0x9805
[    4.534101] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0xE0
[    4.534105] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7C, val 0xE0
[    4.534112] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7C val 0xE0
[    4.534117] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x9805
[    4.534121] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 257, reg 0x7A, val 0x9805
[    4.534127] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 257, reg 0x7A val 0x9805
[    4.534132] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0xE0
[    4.534136] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7C, val 0xE0
[    4.534142] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7C val 0xE0
[    4.534148] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x9805
[    4.534152] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 258, reg 0x7A, val 0x9805
[    4.534158] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 258, reg 0x7A val 0x9805
[    4.534163] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0xE0
[    4.534167] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7C, val 0xE0
[    4.534173] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7C val 0xE0
[    4.534178] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x9805
[    4.534182] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_write: drp_port: 259, reg 0x7A, val 0x9805
[    4.534189] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 259, reg 0x7A val 0x9805
[    4.534232] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    4.534238] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x7C val 0xE0
[    4.534243] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    4.534248] axi_adxcvr 84a60000.axi-adxcvr-tx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x12
[    4.534252] axi_adxcvr 84a60000.axi-adxcvr-tx: qpll: fb_div=20, qpll: refclk_div=1
[    4.534560] axi_adxcvr 84a60000.axi-adxcvr-tx: AXI-ADXCVR-TX (17.01.a) using GTH4 at 0x84A60000 mapped to 0xffffff800960d000. Number of lanes: 4.
[    4.548787]  mmcblk0: p1 p2 p3
[    4.579534] ad9680 spi1.2: AD9680 PLL LOCKED
[    4.583807] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_enable: RX
[    4.613576] axi_adxcvr 84a60000.axi-adxcvr-tx: adxcvr_clk_enable: TX
[    4.676448] cf_axi_adc 84a10000.axi-ad9680-hpc: ADI AIM (10.01.b) at 0x84A10000 mapped to 0xffffff800d170000, probed ADC AD9680 as MASTER
[    4.705485] cf_axi_dds 84a04000.axi-ad9144-hpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.01.b) at 0x84A04000 mapped to 0xffffff800d190000, probed DDS AD9144

I tried a similar configuration CPLL reference 500MHz and lane rate 10Gbps on a ZCU102 (GTH4)

RH: How did you connect to SYNCIN pins? Does that really matter? 

Did you make any modifications?

RH: Yes I removed all instances of the ad9528 and ad9152 from the tcl scripts and built the firmware for our FPGA.

What fpga and speed grade are you using?

RH: FPGA: xczu7cg-fbvb900-1-e, so speed grade -1. I've checked this before but stopped at the max line rate for the GTH (10.3125Gb/s). Now, looking closer again the CPLL line rate range is limited to 8.5 Gb/s! So this could be the issue since I use the CPLL for the transceivers. Is this configurable somehow or should I dig into the tcl scripts to change this? (Using the XCZU9EG fpga (with -2 speed grade) on the ZCU102 ref board at a minimum of 0.85V the max CPLL line rate is 12.5 Gb/s, so that should indeed work.)

ok, clear! I will rebuilt the firmware and connect all the SYNCIN inputs towards the ADC to the same signal (rx_sync_0) coming from the axi_ad9694_jesd interface. Do you agree? 

adi,out-clk-select = <4> can stay to <4>?

Thanks for the details!

These have disappeared now!

ad9680 spi1.0: Failed to set lane rate to 10000000 kHz: -22
ad9680 spi1.0: Failed to initialize: -22
ad9680: probe of spi1.0 failed with error -22

- the qpll is selected now

- syncinA/B/C/D are tied together

- removed: /* adi,use-cpll-enable; */

New debug info:

[ 6.804308] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[ 6.813053] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[ 6.822448] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[ 6.831583] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x2E
[ 6.840630] axi_adxcvr 84a50000.axi-adxcvr-rx: qpll: fb_div=48, qpll: refclk_div=1
[ 6.848204] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 24000000 Hz Parent Rate 500000000 Hz
[ 6.849379] PLL: shutdown
[ 6.860738] axi_adxcvr 84a50000.axi-adxcvr-rx: QPLL: failed to find setting for lane rate 24000000 kHz with reference clock 500000 kHz
[ 6.872928] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[ 6.881635] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[ 6.891030] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[ 6.900176] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x2E
[ 6.909221] axi_adxcvr 84a50000.axi-adxcvr-rx: qpll: fb_div=48, qpll: refclk_div=1
[ 6.921587] axi_adxcvr 84a50000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using GTH4 at 0x84A50000 mapped to 0xffffff800936d000. Number of lanes: 4.

Where is this coming from? --> Rate 24000000 Hz The 10Gb/s lane rate seems to have changed now.

I think that is caused by the default parameters set for the adxcvr IP.  It is used during  the first attempt but there should be further attempts where the correct rate is used. Do you have the full log ? 

can you share a clk_summary? 

Also can you share the link status ? 

grep "" /sys/bus/platform/devices/*.axi-jesd*/status*

grep "" /sys/bus/platform/devices/*.axi-jesd*/lane*

Thanks,

Laszlo

see below:

Xilinx Zynq MP First Stage Boot Loader 
Release 2018.3   Jul  9 2020  -  14:42:21
NOTICE:  ATF running on XCZU7CG/silicon v4/RTL5.1 at 0xfffea000
NOTICE:  BL31: Secure code at 0x60000000
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v1.5(release):xilinx-v2018.2-919-g08560c36
NOTICE:  BL31: Built : 14:40:34, Jul  9 2020
PMUFW:	v1.1


U-Boot 2018.01 (Jul 09 2020 - 14:55:59 +0000) Xilinx ZynqMP ZCU102 rev1.0

I2C:   ready
DRAM:  3 GiB
EL Level:	EL2
Chip ID:	zu7cg
SF: Detected n25q512a with page size 512 Bytes, erase size 128 KiB, total 128 MiB
In:    serial@ff000000
Out:   serial@ff000000
Err:   serial@ff000000
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
Net:   ZYNQ GEM: ff0e0000, phyaddr c, interface rgmii-id
eth0: ethernet@ff0e0000
Hit any key to stop autoboot:  0 
ZynqMP> run netboot
Using ethernet@ff0e0000 device
TFTP from server 192.168.10.1; our IP address is 192.168.10.2
Filename 'image.ub'.
Load address: 0x10000000
Loading: #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 #################################################################
	 770.5 KiB/s
done
Bytes transferred = 7651256 (74bfb8 hex)
## Loading kernel from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'kernel@1' kernel subimage
     Description:  Linux kernel
     Type:         Kernel Image
     Compression:  gzip compressed
     Data Start:   0x10000100
     Data Size:    7607852 Bytes = 7.3 MiB
     Architecture: AArch64
     OS:           Linux
     Load Address: 0x00080000
     Entry Point:  0x00080000
     Hash algo:    sha1
     Hash value:   8ecd5d04e75d2ec2d4de5ec13ddb3bb2b0426c19
   Verifying Hash Integrity ... sha1+ OK
## Loading fdt from FIT Image at 10000000 ...
   Using 'conf@system-top.dtb' configuration
   Trying 'fdt@system-top.dtb' fdt subimage
     Description:  Flattened Device Tree blob
     Type:         Flat Device Tree
     Compression:  uncompressed
     Data Start:   0x10741830
     Data Size:    41489 Bytes = 40.5 KiB
     Architecture: AArch64
     Hash algo:    sha1
     Hash value:   a8a1afc3d2f0dba0d7b6395f6b8de6edd322ee8b
   Verifying Hash Integrity ... sha1+ OK
   Booting using the fdt blob at 0x10741830
   Uncompressing Kernel Image ... OK
   Loading Device Tree to 0000000007ff2000, end 0000000007fff210 ... OK

Starting kernel ...

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 4.14.0-xilinx- (oe-user@oe-host) (gcc version 7.3.0 (GCC)) #3 SMP Thu Jul 9 14:59:14 UTC 2020
[    0.000000] Boot CPU: AArch64 Processor [410fd034]
[    0.000000] Machine model: ZynqMP ZCU102 Rev1.0
[    0.000000] efi: Getting EFI parameters from FDT:
[    0.000000] efi: UEFI not found.
[    0.000000] cma: Reserved 256 MiB at 0x0000000070000000
[    0.000000] On node 0 totalpages: 1048576
[    0.000000]   DMA zone: 7168 pages used for memmap
[    0.000000]   DMA zone: 0 pages reserved
[    0.000000]   DMA zone: 524288 pages, LIFO batch:31
[    0.000000]   Normal zone: 7168 pages used for memmap
[    0.000000]   Normal zone: 524288 pages, LIFO batch:31
[    0.000000] psci: probing for conduit method from DT.
[    0.000000] psci: PSCIv1.1 detected in firmware.
[    0.000000] psci: Using standard PSCI v0.2 function IDs
[    0.000000] psci: MIGRATE_INFO_TYPE not supported.
[    0.000000] random: fast init done
[    0.000000] percpu: Embedded 21 pages/cpu @ffffffc87ff94000 s46488 r8192 d31336 u86016
[    0.000000] pcpu-alloc: s46488 r8192 d31336 u86016 alloc=21*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1 
[    0.000000] Detected VIPT I-cache on CPU0
[    0.000000] CPU features: enabling workaround for ARM erratum 845719
[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 1034240
[    0.000000] Kernel command line: earlyprintk console=ttyPS0,115200 clk_ignore_unused root=/dev/nfs nfsroot=192.168.10.1:/srv/nfs,vers=3,nolock,tcp ip=192.168.10.2:192.168.10.1 rw nfsrootdebug
[    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[    0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes)
[    0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes)
[    0.000000] software IO TLB [mem 0x6bfff000-0x6ffff000] (64MB) mapped at [ffffffc06bfff000-ffffffc06fffefff]
[    0.000000] Memory: 3783716K/4194304K available (10492K kernel code, 756K rwdata, 4500K rodata, 512K init, 2164K bss, 148444K reserved, 262144K cma-reserved)
[    0.000000] Virtual kernel memory layout:
[    0.000000]     modules : 0xffffff8000000000 - 0xffffff8008000000   (   128 MB)
[    0.000000]     vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000   (   250 GB)
[    0.000000]       .text : 0xffffff8008080000 - 0xffffff8008ac0000   ( 10496 KB)
[    0.000000]     .rodata : 0xffffff8008ac0000 - 0xffffff8008f30000   (  4544 KB)
[    0.000000]       .init : 0xffffff8008f30000 - 0xffffff8008fb0000   (   512 KB)
[    0.000000]       .data : 0xffffff8008fb0000 - 0xffffff800906d200   (   757 KB)
[    0.000000]        .bss : 0xffffff800906d200 - 0xffffff800928a5b0   (  2165 KB)
[    0.000000]     fixed   : 0xffffffbefe7fd000 - 0xffffffbefec00000   (  4108 KB)
[    0.000000]     PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000   (    16 MB)
[    0.000000]     vmemmap : 0xffffffbf00000000 - 0xffffffc000000000   (     4 GB maximum)
[    0.000000]               0xffffffbf00000000 - 0xffffffbf1dc00000   (   476 MB actual)
[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc880000000   ( 34816 MB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000] 	RCU event tracing is enabled.
[    0.000000] 	RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
[    0.000000] GIC: Using split EOI/Deactivate mode
[    0.000000] arch_timer: cp15 timer(s) running at 99.90MHz (phys).
[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x170a3d70de, max_idle_ns: 440795202122 ns
[    0.000003] sched_clock: 56 bits at 99MHz, resolution 10ns, wraps every 4398046511100ns
[    0.000329] Console: colour dummy device 80x25
[    0.000347] Calibrating delay loop (skipped), value calculated using timer frequency.. 199.80 BogoMIPS (lpj=399600)
[    0.000354] pid_max: default: 32768 minimum: 301
[    0.000453] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.000469] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes)
[    0.001049] ASID allocator initialised with 65536 entries
[    0.001095] Hierarchical SRCU implementation.
[    0.001427] EFI services will not be available.
[    0.001450] zynqmp_plat_init Platform Management API v1.1
[    0.001455] zynqmp_plat_init Trustzone version v1.0
[    0.001520] smp: Bringing up secondary CPUs ...
[    0.001769] Detected VIPT I-cache on CPU1
[    0.001798] CPU1: Booted secondary processor [410fd034]
[    0.001852] smp: Brought up 1 node, 2 CPUs
[    0.001860] SMP: Total of 2 processors activated.
[    0.001865] CPU features: detected feature: 32-bit EL0 Support
[    0.001873] CPU: All CPU(s) started at EL2
[    0.001884] alternatives: patching kernel code
[    0.002624] devtmpfs: initialized
[    0.007144] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[    0.007157] futex hash table entries: 512 (order: 4, 65536 bytes)
[    0.012655] xor: measuring software checksum speed
[    0.052014]    8regs     :  2280.000 MB/sec
[    0.092041]    8regs_prefetch:  2032.000 MB/sec
[    0.132071]    32regs    :  2802.000 MB/sec
[    0.172101]    32regs_prefetch:  2355.000 MB/sec
[    0.172106] xor: using function: 32regs (2802.000 MB/sec)
[    0.172175] pinctrl core: initialized pinctrl subsystem
[    0.172752] NET: Registered protocol family 16
[    0.173399] cpuidle: using governor menu
[    0.173963] vdso: 2 pages (1 code @ ffffff8008ac6000, 1 data @ ffffff8008fb4000)
[    0.173972] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[    0.174420] DMA: preallocated 256 KiB pool for atomic allocations
[    0.195704] reset_zynqmp reset-controller: Xilinx zynqmp reset driver probed
[    0.196231] ARM CCI_400_r1 PMU driver probed
[    0.200403] zynqmp-pinctrl ff180000.pinctrl: zynqmp pinctrl initialized
[    0.213887] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
[    0.280304] raid6: int64x1  gen()   399 MB/s
[    0.348390] raid6: int64x1  xor()   440 MB/s
[    0.416501] raid6: int64x2  gen()   683 MB/s
[    0.484525] raid6: int64x2  xor()   596 MB/s
[    0.552593] raid6: int64x4  gen()  1033 MB/s
[    0.620643] raid6: int64x4  xor()   733 MB/s
[    0.688749] raid6: int64x8  gen()   970 MB/s
[    0.756780] raid6: int64x8  xor()   733 MB/s
[    0.824878] raid6: neonx1   gen()   719 MB/s
[    0.892916] raid6: neonx1   xor()   844 MB/s
[    0.960980] raid6: neonx2   gen()  1157 MB/s
[    1.029036] raid6: neonx2   xor()  1188 MB/s
[    1.097110] raid6: neonx4   gen()  1489 MB/s
[    1.165170] raid6: neonx4   xor()  1420 MB/s
[    1.233254] raid6: neonx8   gen()  1632 MB/s
[    1.301288] raid6: neonx8   xor()  1510 MB/s
[    1.301292] raid6: using algorithm neonx8 gen() 1632 MB/s
[    1.301296] raid6: .... xor() 1510 MB/s, rmw enabled
[    1.301300] raid6: using neon recovery algorithm
[    1.302752] SCSI subsystem initialized
[    1.302790] libata version 3.00 loaded.
[    1.302917] usbcore: registered new interface driver usbfs
[    1.302948] usbcore: registered new interface driver hub
[    1.302981] usbcore: registered new device driver usb
[    1.303043] media: Linux media interface: v0.10
[    1.303065] Linux video capture interface: v2.00
[    1.303101] pps_core: LinuxPPS API ver. 1 registered
[    1.303105] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[    1.303119] PTP clock support registered
[    1.303348] zynqmp-ipi ff9905c0.mailbox: Probed ZynqMP IPI Mailbox driver.
[    1.303471] FPGA manager framework
[    1.303574] fpga-region fpga-full: FPGA Region probed
[    1.303658] Advanced Linux Sound Architecture Driver Initialized.
[    1.303901] Bluetooth: Core ver 2.22
[    1.303922] NET: Registered protocol family 31
[    1.303926] Bluetooth: HCI device and connection manager initialized
[    1.303933] Bluetooth: HCI socket layer initialized
[    1.303939] Bluetooth: L2CAP socket layer initialized
[    1.303958] Bluetooth: SCO socket layer initialized
[    1.305298] clocksource: Switched to clocksource arch_sys_counter
[    1.305370] VFS: Disk quotas dquot_6.6.0
[    1.305410] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[    1.311882] NET: Registered protocol family 2
[    1.312186] TCP established hash table entries: 32768 (order: 6, 262144 bytes)
[    1.312392] TCP bind hash table entries: 32768 (order: 7, 524288 bytes)
[    1.312805] TCP: Hash tables configured (established 32768 bind 32768)
[    1.312869] UDP hash table entries: 2048 (order: 4, 65536 bytes)
[    1.312942] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes)
[    1.313081] NET: Registered protocol family 1
[    1.313333] RPC: Registered named UNIX socket transport module.
[    1.313338] RPC: Registered udp transport module.
[    1.313342] RPC: Registered tcp transport module.
[    1.313345] RPC: Registered tcp NFSv4.1 backchannel transport module.
[    1.313352] PCI: CLS 0 bytes, default 128
[    1.313776] hw perfevents: no interrupt-affinity property for /pmu, guessing.
[    1.313875] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
[    1.314430] audit: initializing netlink subsys (disabled)
[    1.315105] audit: type=2000 audit(1.307:1): state=initialized audit_enabled=0 res=1
[    1.315166] workingset: timestamp_bits=62 max_order=20 bucket_order=0
[    1.315793] NFS: Registering the id_resolver key type
[    1.315810] Key type id_resolver registered
[    1.315814] Key type id_legacy registered
[    1.315823] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[    1.315840] jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
[    1.339454] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[    1.339462] io scheduler noop registered
[    1.339466] io scheduler deadline registered
[    1.339481] io scheduler cfq registered (default)
[    1.339486] io scheduler mq-deadline registered
[    1.339490] io scheduler kyber registered
[    1.341022] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
[    1.341171] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
[    1.341330] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
[    1.341474] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
[    1.341616] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
[    1.341763] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
[    1.341907] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
[    1.342053] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
[    1.342247] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
[    1.342393] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
[    1.342533] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
[    1.342676] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
[    1.342819] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
[    1.342964] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
[    1.343108] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
[    1.343249] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
[    1.374524] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    1.377135] cacheinfo: Unable to detect cache hierarchy for CPU 0
[    1.381411] brd: module loaded
[    1.384805] loop: module loaded
[    1.385522] mtdoops: mtd device (mtddev=name/number) must be supplied
[    1.386884] m25p80 spi0.0: SPI-NOR-UniqueID 1044007e6a95001607001100c556ee23cb
[    1.386891] m25p80 spi0.0: found n25q512a, expected m25p80
[    1.387016] m25p80 spi0.0: n25q512a (131072 Kbytes)
[    1.387037] 5 ofpart partitions found on MTD device spi0.0
[    1.387041] Creating 5 MTD partitions on "spi0.0":
[    1.387048] 0x000000000000-0x000001e00000 : "boot"
[    1.387463] 0x000001e00000-0x000001e40000 : "bootenv"
[    1.387849] 0x000001e40000-0x000004240000 : "kernel"
[    1.388230] 0x000004240000-0x000007120000 : "jffs2"
[    1.388610] 0x000007120000-0x000007140000 : "spare"
[    1.389981] libphy: Fixed MDIO Bus: probed
[    1.391010] tun: Universal TUN/TAP device driver, 1.6
[    1.391203] CAN device driver interface
[    1.392676] macb ff0e0000.ethernet: Not enabling partial store and forward
[    1.393135] libphy: MACB_mii_bus: probed
[    1.394119] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 29 (aa:bb:cc:dd:ee:ff)
[    1.394128] TI DP83867 ff0e0000.ethernet-ffffffff:0c: attached PHY driver [TI DP83867] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:0c, irq=POLL)
[    1.394716] usbcore: registered new interface driver asix
[    1.394762] usbcore: registered new interface driver ax88179_178a
[    1.394787] usbcore: registered new interface driver cdc_ether
[    1.394811] usbcore: registered new interface driver net1080
[    1.394835] usbcore: registered new interface driver cdc_subset
[    1.394861] usbcore: registered new interface driver zaurus
[    1.394896] usbcore: registered new interface driver cdc_ncm
[    1.395176] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
[    1.395639] usbcore: registered new interface driver uas
[    1.395673] usbcore: registered new interface driver usb-storage
[    1.396130] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
[    1.396175] i2c /dev entries driver
[    1.396864] IR NEC protocol handler initialized
[    1.396868] IR RC5(x/sz) protocol handler initialized
[    1.396872] IR RC6 protocol handler initialized
[    1.396876] IR JVC protocol handler initialized
[    1.396879] IR Sony protocol handler initialized
[    1.396883] IR SANYO protocol handler initialized
[    1.396886] IR Sharp protocol handler initialized
[    1.396890] IR MCE Keyboard/mouse protocol handler initialized
[    1.396894] IR XMP protocol handler initialized
[    1.397625] usbcore: registered new interface driver uvcvideo
[    1.397629] USB Video Class driver (1.1.1)
[    1.398209] cdns-wdt fd4d0000.watchdog: Xilinx Watchdog Timer at ffffff80092f5000 with timeout 60s
[    1.398380] cdns-wdt ff150000.watchdog: Xilinx Watchdog Timer at ffffff80092fd000 with timeout 10s
[    1.398579] Bluetooth: HCI UART driver ver 2.3
[    1.398585] Bluetooth: HCI UART protocol H4 registered
[    1.398589] Bluetooth: HCI UART protocol BCSP registered
[    1.398593] Bluetooth: HCI UART protocol ATH3K registered
[    1.398597] Bluetooth: HCI UART protocol Three-wire (H5) registered
[    1.398635] Bluetooth: HCI UART protocol Intel registered
[    1.398640] Bluetooth: HCI UART protocol QCA registered
[    1.398673] usbcore: registered new interface driver bcm203x
[    1.398703] usbcore: registered new interface driver bpa10x
[    1.398732] usbcore: registered new interface driver bfusb
[    1.398760] usbcore: registered new interface driver btusb
[    1.398765] Bluetooth: Generic Bluetooth SDIO driver ver 0.1
[    1.398809] usbcore: registered new interface driver ath3k
[    1.399228] cpufreq: cpufreq_online: CPU0: Running at unlisted freq: 1188000 KHz
[    1.399276] cpufreq: cpufreq_online: CPU0: Unlisted initial frequency changed to: 1199999 KHz
[    1.399548] sdhci: Secure Digital Host Controller Interface driver
[    1.399552] sdhci: Copyright(c) Pierre Ossman
[    1.399556] sdhci-pltfm: SDHCI platform and OF driver helper
[    1.400984] ledtrig-cpu: registered to indicate activity on CPUs
[    1.401116] usbcore: registered new interface driver usbhid
[    1.401120] usbhid: USB HID core driver
[    1.407055] axi_sysid 85000000.axi-sysid-0: [grand] on [zu7cg] git <bc93cf83123783d1f08af0d771c1dcd76f022ef8> clean [2020-07-09 14:08:37] UTC
[    1.407384] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[    1.408147] pktgen: Packet Generator for packet performance testing. Version: 2.75
[    1.408303] Netfilter messages via NETLINK v0.30.
[    1.408427] ip_tables: (C) 2000-2006 Netfilter Core Team
[    1.408549] Initializing XFRM netlink socket
[    1.408605] NET: Registered protocol family 10
[    1.409019] Segment Routing with IPv6
[    1.409060] ip6_tables: (C) 2000-2006 Netfilter Core Team
[    1.409170] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
[    1.409504] NET: Registered protocol family 17
[    1.409516] NET: Registered protocol family 15
[    1.409530] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
[    1.409535] Ebtables v2.0 registered
[    1.409617] can: controller area network core (rev 20170425 abi 9)
[    1.409647] NET: Registered protocol family 29
[    1.409652] can: raw protocol (rev 20170425)
[    1.409656] can: broadcast manager protocol (rev 20170425 t)
[    1.409663] can: netlink gateway (rev 20170425) max_hops=1
[    1.409717] Bluetooth: RFCOMM TTY layer initialized
[    1.409727] Bluetooth: RFCOMM socket layer initialized
[    1.409737] Bluetooth: RFCOMM ver 1.11
[    1.409743] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
[    1.409747] Bluetooth: BNEP filters: protocol multicast
[    1.409753] Bluetooth: BNEP socket layer initialized
[    1.409757] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
[    1.409763] Bluetooth: HIDP socket layer initialized
[    1.409860] 9pnet: Installing 9P2000 support
[    1.409875] Key type dns_resolver registered
[    1.410424] registered taskstats version 1
[    1.410733] Btrfs loaded, crc32c=crc32c-generic
[    1.415248] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 38, base_baud = 6243750) is a xuartps
[    2.981939] console [ttyPS0] enabled
[    2.986032] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 39, base_baud = 6243750) is a xuartps
[    2.997541] PLL: shutdown
[    3.000157] zynqmp_pll_disable() clock disable failed for apll_int, ret = -13
[    3.007378] at24 0-0054: 1024 byte 24c08 EEPROM, writable, 16 bytes/write
[    3.060444] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 31
[    3.066964] ad9680 spi1.0: ad9680_spi_read: REG: 0x4 VAL: 0x0 (0)
[    3.073049] ad9680 spi1.0: Unrecognized CHIP_ID 0x0
[    3.079306] input: gpio-keys as /devices/platform/gpio-keys/input/input0
[    3.086194] rtc_zynqmp ffa60000.rtc: setting system clock to 1970-01-01 00:00:31 UTC (31)
[    3.096140] pps pps0: new PPS source ptp0
[    3.100155] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
[    3.106811] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
[    6.145390] macb ff0e0000.ethernet eth0: link up (1000/Full)
[    6.157344] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
[    6.181287] IP-Config: Guessing netmask 255.255.255.0
[    6.186330] IP-Config: Complete:
[    6.189550]      device=eth0, hwaddr=aa:bb:cc:dd:ee:ff, ipaddr=192.168.10.2, mask=255.255.255.0, gw=255.255.255.255
[    6.199974]      host=192.168.10.2, domain=, nis-domain=(none)
[    6.205797]      bootserver=192.168.10.1, rootserver=192.168.10.1, rootpath=
[    6.212887] clk: Not disabling unused clocks
[    6.217181] ALSA device list:
[    6.220141]   No soundcards found.
[    6.233441] VFS: Mounted root (nfs filesystem) on device 0:15.
[    6.239780] devtmpfs: mounted
[    6.242871] Freeing unused kernel memory: 512K
INIT: version 2.88 booting
Starting udev
[    6.559154] udevd[1725]: starting version 3.2.2
[    6.633823] udevd[1726]: starting eudev-3.2.2
[    6.746881] si5341: loading out-of-tree module taints kernel.
[    6.764918] si5341 0-0076: Chip: 5340 Grade: 0 Rev: 3
[    6.804308] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    6.813053] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    6.822448] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    6.831583] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x2E
[    6.840630] axi_adxcvr 84a50000.axi-adxcvr-rx: qpll: fb_div=48, qpll: refclk_div=1
[    6.848204] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_set_rate: Rate 24000000 Hz Parent Rate 500000000 Hz
[    6.849379] PLL: shutdown
[    6.860738] axi_adxcvr 84a50000.axi-adxcvr-rx: QPLL: failed to find setting for lane rate 24000000 kHz with reference clock 500000 kHz
[    6.872928] axi_adxcvr 84a50000.axi-adxcvr-rx: adxcvr_clk_recalc_rate: Parent Rate 500000000 Hz
[    6.881635] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 256, reg 0x63 val 0x80C0
[    6.891030] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x18 val 0x808
[    6.900176] axi_adxcvr 84a50000.axi-adxcvr-rx: xilinx_xcvr_drp_read: drp_port: 0, reg 0x14 val 0x2E
[    6.909221] axi_adxcvr 84a50000.axi-adxcvr-rx: qpll: fb_div=48, qpll: refclk_div=1
[    6.921587] axi_adxcvr 84a50000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.01.a) using GTH4 at 0x84A50000 mapped to 0xffffff800936d000. Number of lanes: 4.
Thu Jul  9 15:01:03 UTC 2020
Starting internet superserver: inetd.
Configuring packages on first boot....
 (This may take several minutes. Please do not power off the machine.)
Running postinst /etc/rpm-postinsts/100-sysvinit-inittab...
update-rc.d: /etc/init.d/run-postinsts exists during rc.d purge (continuing)
 Removing any system startup links for run-postinsts ...
  /etc/rcS.d/S99run-postinsts
INIT: Entering runlevel: 5
Configuring network interfaces... RTNETLINK answers: File exists
ifup skipped for nfsroot interface eth0
run-parts: /etc/network/if-pre-up.d/nfsroot: exit status 1
Starting system message bus: dbus.
Starting Dropbear SSH server: Generating key, this may take a while...
[   22.270638] random: crng init done
Public key portion is:
ssh-rsa AAAAB3NzaC1yc2EAAAADAQABAAABAQCS19lHevlXbYn2mm8gaIMmFXKrHe/0zdOc3bER884uC4ILnHr6pe7kpitggySd8vBgaxogM4bu104k4ArT71rqmdw9zba4lTpW5iFN9Nlz9AGlBGyNlsyodzQjck1lwlRnVTF1Rbip1iAns5Sl7/jaNefBID4uLNYYLWDULAjieXfbLtyBuQqs7e1fgAinyjdeiU298tHVfwJSS0mNtZ5sLyxybZNzMaS+f3GKbeet5zU4++t4Vyw0T/VAJUR/mk9lfx+TUkDvrQZuE2/vKHglK6jDlDwlqIM8Wuh9ambXMXwjVMTrU3XsIjZep1of5n85W7F6WkFfgSQIdxbShaHZ root@grand_zcu7
Fingerprint: md5 11:85:d4:a5:a8:d6:d7:d5:d0:aa:ab:b4:80:52:cf:ec
dropbear.
Starting IIO Daemon: iiod
Starting syslogd/klogd: done
Starting tcf-agent: OK

PetaLinux 2018.3 grand_zcu7 /dev/ttyPS0

grand_zcu7 login: root
Password: 
root@grand_zcu7:/sys/bus/iio/devices/iio:device0# cat /sys/kernel/debug/clk/clk_summary 
   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 xtal_48_clock                            2            2    48000000          0 0  
    si5340                                1            2    14000000          0 0  
       si5340.N3                          0            0           0          0 0  
       si5340.N2                          0            1   600000000          0 0  
          si5340.1                        0            1   300000000          0 0  
       si5340.N1                          0            0   162000000          0 0  
          si5340.0                        0            0    27000000          0 0  
       si5340.N0                          1            2  2000000000          0 0  
          si5340.3                        0            1  1000000000          0 0  
          si5340.2                        1            2   500000000          0 0  
             rx_out_clk                   0            0   250000000          0 0  
             adc_gt_clk                   0            0    24000000          0 0  
                jesd_adc_lane_clk           0            0    24000000          0 0  
 dp_aclk                                  0            0   100000000        100 0  
 aux_ref_clk                              0            0    27000000          0 0  
 gt_crx_ref_clk                           0            0   108000000          0 0  
 pss_alt_ref_clk                          0            0           0          0 0  
 video_clk                                0            0    27000000          0 0  
 pss_ref_clk                              1            1    27000000          0 0  
    vpll_post_src                         0            0    27000000          0 0  
    vpll_pre_src                          0            0    27000000          0 0  
       vpll_int                           0            0  2997000000          0 0  
          vpll_half                       0            0  1498500000          0 0  
             vpll_int_mux                 0            0  1498500000          0 0  
                vpll                      0            0  1498500000          0 0  
                   dp_stc_ref_mux           0            0  1498500000          0 0  
                      dp_stc_ref_div1           0            0    29970000          0 0  
                         dp_stc_ref_div2           0            0      936563          0 0  
                            dp_stc_ref           0            0      936563          0 0  
                   dp_audio_ref_mux           0            0  1498500000          0 0  
                      dp_audio_ref_div1           0            0    42814286          0 0  
                         dp_audio_ref_div2           0            0    14271429          0 0  
                            dp_audio_ref           0            0    14271429          0 0  
                   vpll_to_lpd            0            0   499500000          0 0  
    dpll_post_src                         0            0    27000000          0 0  
    dpll_pre_src                          0            0    27000000          0 0  
       dpll_int                           0            0  2133000000          0 0  
          dpll_half                       0            0  1066500000          0 0  
             dpll_int_mux                 0            0  1066500000          0 0  
                dpll                      0            0  1066500000          0 0  
                   gpu_ref_mux            0            0  1066500000          0 0  
                      gpu_ref_div1           0            0   213300000          0 0  
                         gpu_ref           0            0   213300000          0 0  
                            gpu_pp1_ref           0            0   213300000          0 0  
                            gpu_pp0_ref           0            0   213300000          0 0  
                   pcie_ref_mux           0            0  1066500000          0 0  
                      pcie_ref_div1           0            0    88875000          0 0  
                         pcie_ref           0            0    88875000          0 0  
                   sata_ref_mux           0            0  1066500000          0 0  
                      sata_ref_div1           0            0    88875000          0 0  
                         sata_ref           0            0    88875000          0 0  
                   dp_video_ref_mux           0            0  1066500000          0 0  
                      dp_video_ref_div1           0            0   106650000          0 0  
                         dp_video_ref_div2           0            0   106650000          0 0  
                            dp_video_ref           0            0   106650000          0 0  
                   dpll_to_lpd            0            0   533250000          0 0  
    apll_post_src                         0            0    27000000          0 0  
    apll_pre_src                          0            0    27000000          0 0  
       apll_int                           0            0  2376000000          0 0  
          apll_half                       0            0  1188000000          0 0  
             apll_int_mux                 0            0  1188000000          0 0  
                apll                      0            0  1188000000          0 0  
                   dpdma_ref_mux           0            0  1188000000          0 0  
                      dpdma_ref_div1           0            0   594000000          0 0  
                         dpdma_ref           0            0   594000000          0 0  
                   gdma_ref_mux           0            0  1188000000          0 0  
                      gdma_ref_div1           0            0   594000000          0 0  
                         gdma_ref           0            0   594000000          0 0  
                   acpu_mux               0            0  1188000000          0 0  
                      acpu                0            0  1188000000          0 0  
    rpll_post_src                         0            0    27000000          0 0  
    rpll_pre_src                          0            0    27000000          0 0  
       rpll_int                           0            0  2997000000          0 0  
          rpll_half                       0            0  1498500000          0 0  
             rpll_int_mux                 0            0  1498500000          0 0  
                rpll                      0            0  1498500000          0 0  
                   spi1_ref_mux           0            0  1498500000          0 0  
                      spi1_ref_div1           0            0    99900000          0 0  
                         spi1_ref_div2           0            0    99900000          0 0  
                            spi1_ref           0            0    99900000          0 0  
                   spi0_ref_mux           0            0  1498500000          0 0  
                      spi0_ref_div1           0            0    99900000          0 0  
                         spi0_ref_div2           0            0    99900000          0 0  
                            spi0_ref           0            0    99900000          0 0  
                   rpll_to_fpd            0            0   499500000          0 0  
    iopll_post_src                        0            0    27000000          0 0  
    iopll_pre_src                         1            1    27000000          0 0  
       iopll_int                          1            1  1998000000          0 0  
          iopll_half                      1            1   999000000          0 0  
             iopll_int_mux                1            1   999000000          0 0  
                iopll                     6            9   999000000          0 0  
                   gem3_ref_ung_mux           1            1   999000000          0 0  
                      gem3_ref_ung_div1           1            1   999000000          0 0  
                         gem3_ref_ung           1            1   124875000          0 0  
                            gem3_ref           2            2   124875000          0 0  
                               gem3_tx           1            1   124875000          0 0  
                   gem2_ref_ung_mux           0            0   999000000          0 0  
                      gem2_ref_ung_div1           0            0    41625000          0 0  
                         gem2_ref_ung           0            0    41625000          0 0  
                            gem2_ref           0            0    41625000          0 0  
                               gem2_tx           0            0    41625000          0 0  
                   gem1_ref_ung_mux           0            0   999000000          0 0  
                      gem1_ref_ung_div1           0            0    41625000          0 0  
                         gem1_ref_ung           0            0    41625000          0 0  
                            gem1_ref           0            0    41625000          0 0  
                               gem1_tx           0            0    41625000          0 0  
                   gem0_ref_ung_mux           0            0   999000000          0 0  
                      gem0_ref_ung_div1           0            0    41625000          0 0  
                         gem0_ref_ung           0            0    41625000          0 0  
                            gem0_ref           0            0    41625000          0 0  
                               gem0_tx           0            0    41625000          0 0  
                   pl3_ref_mux            0            0   999000000          0 0  
                      pl3_ref_div1           0            0    31218750          0 0  
                         pl3_ref_div2           0            0     6243750          0 0  
                            pl3_ref           0            0     6243750          0 0  
                   pl2_ref_mux            0            0   999000000          0 0  
                      pl2_ref_div1           0            0   499500000          0 0  
                         pl2_ref_div2           0            0   499500000          0 0  
                            pl2_ref           0            0   499500000          0 0  
                   pl1_ref_mux            0            0   999000000          0 0  
                      pl1_ref_div1           0            0   249750000          0 0  
                         pl1_ref_div2           0            0   249750000          0 0  
                            pl1_ref           0            0   249750000          0 0  
                   pl0_ref_mux            1            1   999000000          0 0  
                      pl0_ref_div1           1            1    99900000          0 0  
                         pl0_ref_div2           1            1    99900000          0 0  
                            pl0_ref           3            3    99900000          0 0  
                   ams_ref_mux            1            1   999000000          0 0  
                      ams_ref_div1           1            1    49950000          0 0  
                         ams_ref_div2           1            1    49950000          0 0  
                            ams_ref           1            1    49950000          0 0  
                   adma_ref_mux           0            0   999000000          0 0  
                      adma_ref_div1           0            0   499500000          0 0  
                         adma_ref           0            0   499500000          0 0  
                   can1_ref_mux           0            0   999000000          0 0  
                      can1_ref_div1           0            0    31218750          0 0  
                         can1_ref_div2           0            0    31218750          0 0  
                            can1_ref           0            0    31218750          0 0  
                               can1           0            0    31218750          0 0  
                   can0_ref_mux           0            0   999000000          0 0  
                      can0_ref_div1           0            0    31218750          0 0  
                         can0_ref_div2           0            0    31218750          0 0  
                            can0_ref           0            0    31218750          0 0  
                               can0           0            0    31218750          0 0  
                   i2c1_ref_mux           0            0   999000000          0 0  
                      i2c1_ref_div1           0            0    99900000          0 0  
                         i2c1_ref_div2           0            0    99900000          0 0  
                            i2c1_ref           0            0    99900000          0 0  
                   i2c0_ref_mux           0            1   999000000          0 0  
                      i2c0_ref_div1           0            1    99900000          0 0  
                         i2c0_ref_div2           0            1    99900000          0 0  
                            i2c0_ref           0            1    99900000          0 0  
                   nand_ref_mux           0            0   999000000          0 0  
                      nand_ref_div1           0            0    31218750          0 0  
                         nand_ref_div2           0            0     6243750          0 0  
                            nand_ref           0            0     6243750          0 0  
                   uart1_ref_mux           0            1   999000000          0 0  
                      uart1_ref_div1           0            1    99900000          0 0  
                         uart1_ref_div2           0            1    99900000          0 0  
                            uart1_ref           0            1    99900000          0 0  
                   uart0_ref_mux           1            1   999000000          0 0  
                      uart0_ref_div1           1            1    99900000          0 0  
                         uart0_ref_div2           1            1    99900000          0 0  
                            uart0_ref           1            1    99900000          0 0  
                   sdio1_ref_mux           0            0   999000000          0 0  
                      sdio1_ref_div1           0            0    66600000          0 0  
                         sdio1_ref_div2           0            0    66600000          0 0  
                            sdio1_ref           0            0    66600000          0 0  
                   sdio0_ref_mux           0            0   999000000          0 0  
                      sdio0_ref_div1           0            0    66600000          0 0  
                         sdio0_ref_div2           0            0    66600000          0 0  
                            sdio0_ref           0            0    66600000          0 0  
                   qspi_ref_mux           0            1   999000000          0 0  
                      qspi_ref_div1           0            1   124875000          0 0  
                         qspi_ref_div2           0            1   124875000          0 0  
                            qspi_ref           0            1   124875000          0 0  
                   gem_tsu_ref_mux           1            1   999000000          0 0  
                      gem_tsu_ref_div1           1            1   249750000          0 0  
                         gem_tsu_ref_div2           1            1   249750000          0 0  
                            gem_tsu_ref           1            1   249750000          0 0  
                               gem_tsu           1            1   249750000          0 0  
                   usb3_dual_ref_mux           0            0   999000000          0 0  
                      usb3_dual_ref_div1           0            0    31218750          0 0  
                         usb3_dual_ref_div2           0            0     6243750          0 0  
                            usb3_dual_ref           0            0     6243750          0 0  
                   usb1_bus_ref_mux           0            0   999000000          0 0  
                      usb1_bus_ref_div1           0            0    83250000          0 0  
                         usb1_bus_ref_div2           0            0    83250000          0 0  
                            usb1_bus_ref           0            0    83250000          0 0  
                   usb0_bus_ref_mux           0            0   999000000          0 0  
                      usb0_bus_ref_div1           0            0    83250000          0 0  
                         usb0_bus_ref_div2           0            0    83250000          0 0  
                            usb0_bus_ref           0            0    83250000          0 0  
                   iopll_to_fpd           1            1   499500000          0 0  
                      topsw_lsbus_mux           1            1   499500000          0 0  
                         topsw_lsbus_div1           1            1    99900000          0 0  
                            topsw_lsbus           1            1    99900000          0 0  
                               wdt           2            2    99900000          0 0  
 can1_mio                                 0            0           0          0 0  
 can0_mio                                 0            0           0          0 0  
 gem3_rx                                  1            1           0          0 0  
 gem2_rx                                  0            0           0          0 0  
 gem1_rx                                  0            0           0          0 0  
 gem0_rx                                  0            0           0          0 0  
root@grand_zcu7:/sys/bus/iio/devices/iio:device0# grep "" /sys/bus/platform/devices/*.axi-jesd*/status*
Link is disabled
Measured Link Clock: 250.250 MHz
Reported Link Clock: 250.000 MHz
External reset is deasserted
root@grand_zcu7:/sys/bus/iio/devices/iio:device0# grep "" /sys/bus/platform/devices/*.axi-jesd*/lane*
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane0_info:Errors: 0
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane0_info:CGS state: INIT
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane0_info:Initial Frame Synchronization: No
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane1_info:Errors: 0
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane1_info:CGS state: INIT
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane1_info:Initial Frame Synchronization: No
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane2_info:Errors: 0
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane2_info:CGS state: INIT
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane2_info:Initial Frame Synchronization: No
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane3_info:Errors: 0
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane3_info:CGS state: INIT
/sys/bus/platform/devices/84aa0000.axi-jesd204-rx/lane3_info:Initial Frame Synchronization: No
root@grand_zcu7:/sys/bus/iio/devices/iio:device0# 

I've just noticed something strange in the bootlog: the device id of the ad9694 is not read correctly anymore. Previous this was reported as: "ad9680 spi1.0: ad9680_spi_read: REG: 0x4 VAL: 0xDB (0)". Now it returns 0x0 (see bootlog above). This seems strange to me since the only thing I changed was the CPLL / QPLL setting and the addition of the SYNCin pins.