We have ADRV9361-Z7035 evaluation board, We have 40 MHz TCXO with higher stability , which has 3.3 V Vdd , I am new to FPGA world, Is it possible to replace 40 MHz rakon TCXO(which is used with 1.8 V Vdd) given in the default ADRV9361-Z7035 evaluation board by our 40 MHz TCXO , which has 3.3 V Vdd and we want enable of TCXO from bank 34 same as given in ADRV9361-Z7035 board.
similarly, at 33.33 MHz for PS clock, we want to replace 33.33 MEMS clock oscillator given in ADRV9361-Z7035 by 3.3 V Vdd 33.33 MHz TCXO, which has higher stability . As in evaluation board, 33.33 MHz oscillator has given Vdd from VCCPCOM-1P8V. We want minimal changes in evaluation board as our agenda is only to change TCXO (which has 3.3 V Vdd instead of 1.8 V Vdd)?
Which is the better idea, whether to use level translator or Change Vdd from different bank?