I am wondering how to synchronize the output of 4 AD9361s such that data from both comes out simultaneously without some delay due to SPI writes. In my layout I have connected the same enable, length matched to all of the AD9361 devices as well as the TXNRX to each of the devices all length matched (same trace name). I guess my question is if I just use spi writes will the valid and enable signals lag the other devices? I have an axi stream combine that will not output until all of the valids are '1'. Ie, will the util_wfifo partially fill up for some devices and not the others introducing an offset in time of the data? Or, should I use the pin control mode to set all of them to RX state simultaneously? If I use the pin control method, what do you suggest to accomplish this? Write custom VHDL? Or, is there some C API I can take advantage of?