I have been working with AD9364. I'm setting parallel port configuration register are as follows : 0x010 = 0xC8, 0x011 = 0x00, 0x012 = 0x10 mean I'm using dual port , double data rate full duplex mode.I would like to know about
1) what is the maximum interface rate that AD9364 can support?
2)will the interface rate depend on enable or disable fir filter?
Thank you for your information..but In the AD9364 datasheet UG-673 they have mentioned that The maximum DATA_CLK rate is increased to 245.76 MHz in LVDS mode(Full duplex mode)...i.e we can go upto 122…
1) 61.44 MSPS
2) FIR filter can certainly be configured to use an interpolation/decimation factor of 1. It's purpose though is to compensate for the inband ripple introduced by the halfband filters. But, from the point of view of maximum interface rate, enabling/disabling the FIR will not have any effect on the maximum interface rate you would get from the part i.e., 61.44 MSPS.
Thank you for your information..but In the AD9364 datasheet UG-673 they have mentioned that The maximum DATA_CLK rate is increased to 245.76 MHz in LVDS mode(Full duplex mode)...i.e we can go upto 122.66 Interface rate beacause data clock = 2 * sampling clock/interface rate..Please correct me if i am wrong.
Vinod, can you confirm that 61.44 MSPS is the maximum interface rate for 9364. Thanks. The corresponding table in UG570 shows that Maximum LVDS Data Rate in 1R1T configuration is 61.44 MSPS.
Maximum sampling rate is 61.44MSPS given in UG570..I would like to know about information they have given in UG-673.can anyone help me with the same.
For more information about AD9361 chip specs/details, you can refer a question to the AD9361 design sub-forum here: https://ez.analog.com/wide-band-rf-transceivers/design-support/
We usually just integrate transceivers here in Linux & no-OS, and we are also users of these chips.