ADRV900x multi-board LO SYNC accuracy and manually phase fine tuning

In the webcast "Multi-Channel Phase And Frequency Synchronization Made Easy" page 38 (or 24:00 min) is mentioned that the phase offset which is unique for every RF-SOM must be measured and corrected to get a multi-SOM phased array. 

1. Is this procedure necessary if a separate clock module with a HMC7044 is used which distributes DEVCLK and SYSREF to all the SOMs (like in webcast slides p.42)?

2. The measured phase offset is saved in an EEPROM. Where exactly is this offset applied to the LO signal? In the FPGA or in the ADRV9009? What is the name of the function?

3. In UG1295 figure 73 says LO SYNC tracking maintains ~3.0 degrees of phase delay between RF-chips at 3500MHz (period time = 286ps, time for 3 degrees = 2,4ps). How is it possible to fine tune so exactly when the HMC987 allows fine tuning only in 25ps steps? Is this accuracy only achieved by exact signal length matching or is there a mechanism to fine tune the phase even more (<25ps)

Analog Devices technical article "RF Transceivers Enable Forced Spurious Decorrelation in Digital Beamforming Phased Arrays" says: A calibration is performed across the channels by adjusting the NCO phase to ensure the RF signals are in phase at the 8-way combiner and coherently combine.

4. How and where can the NCO phase be adjusted?  

Thank you very much in advance,

Will



Added question 4
[edited by: WillR at 3:21 PM (GMT 0) on 29 Jul 2019]

Top Replies

    •  Analog Employees 
    Jul 30, 2019 +1 verified
    1. Is this procedure necessary if a separate clock module with a HMC7044 is used which distributes DEVCLK and SYSREF to all the SOMs (like in webcast slides p.42)?

    Yes.

    2. The measured…
Parents
  • +1
    •  Analog Employees 
    on Jul 30, 2019 10:03 AM over 1 year ago
    1. Is this procedure necessary if a separate clock module with a HMC7044 is used which distributes DEVCLK and SYSREF to all the SOMs (like in webcast slides p.42)?

    Yes.

    2. The measured phase offset is saved in an EEPROM. Where exactly is this offset applied to the LO signal? In the FPGA or in the ADRV9009? What is the name of the function?

    This phase offset will be used in FPGA. 

    For more information please refer to the link below,

    wiki.analog.com/.../adrv9009-zu11eg

    or post your your queries here, https://ez.analog.com/linux-device-drivers/linux-software-drivers

    3. In UG1295 figure 73 says LO SYNC tracking maintains ~3.0 degrees of phase delay between RF-chips at 3500MHz (period time = 286ps, time for 3 degrees = 2,4ps). How is it possible to fine tune so exactly when the HMC987 allows fine tuning only in 25ps steps? Is this accuracy only achieved by exact signal length matching or is there a mechanism to fine tune the phase even more (<25ps)

    This is the phase difference between the Transmitter 1 output of each chip with the different power-up.

    Please refer to UG-1295 section RF PLL PHASE SYNCHRONIZATION for more details.

    Analog Devices technical article "RF Transceivers Enable Forced Spurious Decorrelation in Digital Beamforming Phased Arrays" says: A calibration is performed across the channels by adjusting the NCO phase to ensure the RF signals are in phase at the 8-way combiner and coherently combine.

    4. How and where can the NCO phase be adjusted?  

    Please get in touch with our local FAE. They will have more information on this.

Reply
  • +1
    •  Analog Employees 
    on Jul 30, 2019 10:03 AM over 1 year ago
    1. Is this procedure necessary if a separate clock module with a HMC7044 is used which distributes DEVCLK and SYSREF to all the SOMs (like in webcast slides p.42)?

    Yes.

    2. The measured phase offset is saved in an EEPROM. Where exactly is this offset applied to the LO signal? In the FPGA or in the ADRV9009? What is the name of the function?

    This phase offset will be used in FPGA. 

    For more information please refer to the link below,

    wiki.analog.com/.../adrv9009-zu11eg

    or post your your queries here, https://ez.analog.com/linux-device-drivers/linux-software-drivers

    3. In UG1295 figure 73 says LO SYNC tracking maintains ~3.0 degrees of phase delay between RF-chips at 3500MHz (period time = 286ps, time for 3 degrees = 2,4ps). How is it possible to fine tune so exactly when the HMC987 allows fine tuning only in 25ps steps? Is this accuracy only achieved by exact signal length matching or is there a mechanism to fine tune the phase even more (<25ps)

    This is the phase difference between the Transmitter 1 output of each chip with the different power-up.

    Please refer to UG-1295 section RF PLL PHASE SYNCHRONIZATION for more details.

    Analog Devices technical article "RF Transceivers Enable Forced Spurious Decorrelation in Digital Beamforming Phased Arrays" says: A calibration is performed across the channels by adjusting the NCO phase to ensure the RF signals are in phase at the 8-way combiner and coherently combine.

    4. How and where can the NCO phase be adjusted?  

    Please get in touch with our local FAE. They will have more information on this.

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