Products Mentioned

AD9361S Recommended for New Designs
The AD9361S-CSL is a high performance, highly integrated, RF agile transceiver designed for use in 3G and 4G applications. Its programmability and wideband...
Datasheet
AD9361S on Analog.com

  • State Verified Answer
  • +1 person also asked this people also asked this
  • Replies 5 replies
  • Subscribers 58 subscribers
  • Views 3200 views
  • Users 0 members are here
Options 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

		
ad9361_probe Unsupported Product ID 0xFF



		

			

									
					    gpaden
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Jun 24, 2019 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    Hello,
    

    We have a custom board with two ad9361s and a Zynq. We have succesfully built BOOT.BINs and device tree for an "fmcomms2" which is able to find the ad9361 and all associated SPI devices (axi-ad9361, DDS, and phy). However when we try to create BOOT.BIN and devecetree for an "fmcomms5" to find both AD9361s we see the following messages while booting:
    

    

    ad9361 spi1.0: ad9361_probe : enter (ad9361)
    

    ad9361 spi1.0: ad9361_probe : Unsupported PRODUCT_ID 0xFF 
    

    ad9361 spi1.1: ad9361_probe : enter (ad9361)
    

    ad9361 spi1.1: ad9361_probe : Unsupported PRODUCT_ID 0xFF 
    

    

    I have searched through previous threads to try to find the cause of this, but have been unsuccesfull. We are sure that the reset_b signal is connecte to the right pin, and we have checked the supply and reference voltages. What should we do to troubleshoot this issue. What are the causes for the PRODUCT_ID 0xFF
    
									
			        
		
    

				
						
        

    
    Tags: 
                                            
                 ad9361
                
                                                    
                 AD9361S
                
                                                    
                 Wideband Transceiver IC
                
                                                    
                 RF Integrated Transceivers
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jun 25, 2019 2:24 AM
            
            
					
      
	
      

		
		
      
					
      Hi gpaden,
      

      Unsupported PRODUCT_ID is issued after first SPI read in the ad9361_probe function. This means to me that SPI communication with your chips is not working.
      

      How are pins SPI_ENB connected? Also can you please post here your device tree to have a look at it?
      

      Also if you have access to a logic analyzer you can try to debug the SPI bus.
      

      

      Regards,
      

      Bogdan
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Jun 25, 2019 3:31 AM
            
            
					
      
	
      

		
		
      
					
      Hello,
      

      

      There could be an issue with the spi communication. Do you have a logic analyzer to probe the SPI lines and check the communication ?
      

      

      Regards,
      

      Mircea
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      • 

	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
			
													0
							
			
				
									
							        
			
			
			
        
            
						
                            
            
            				
            
                on Jun 25, 2019 11:22 AM
            
            
												
						in reply to btogorean
					
									
        
	
        

		
		
        
					
        I have inserted the devicetree for the "fmcomms5" (or dual ad9361 configuration) at the bottom of this post.
        

        I will check with my colleagues when they get in about the Logic Analyzer and SPI_ENB pin connection.
        

        

        Additionally I experimented with interchanging the devicetree and BOOT.BIN. _f5 is for fmcomms5, _f2 is for fmcomms2 (single AD9361)
        

        devicetree_f5, BOOT.BIN_f5  -->  both say unsupoorted product_id 0xFF
        

        devicetree_f3, BOOT.BIN_f3  -->  single AD9361 initialized, DDS and cf_axi_adc are properly mapped
        

        devicetree_f3, BOOT.BIN_f5  -->  unsupoorted_product_id 0xff
        

        devicetree_f3, BOOT.BIN_f3  -->  single AD9361 initialized, DDS and cf_axi_adc are properly mapped, second AD9361 has unsupported product_id 0x0
        

        

        Does this indicate that the problem is in the fmcomms5 BOOT.bin? and likelt has to do with the SPI comms?
        

        

        

        

        /dts-v1/;

/ {
	#address-cells = <0x1>;
	#size-cells = <0x1>;
	compatible = "xlnx,zynq-7000";
	interrupt-parent = <0x4>;

	// Zynq CPUs
	cpus {
		#address-cells = <0x1>;
		#size-cells = <0x0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x0>;
			clocks = <0x1 0x3>;
			clock-latency = <0x3e8>;
			cpu0-supply = <0x2>;
			operating-points = <0xa2c2a 0xf4240 0x51615 0xf4240>;
		};

		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0x1>;
			clocks = <0x1 0x3>;
		};
	};

	fpga-full {
		compatible = "fpga-region";
		fpga-mgr = <0x3>;
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;
	};

	pmu@f8891000 {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0x0 0x5 0x4 0x0 0x6 0x4>;
		interrupt-parent = <0x4>;
		reg = <0xf8891000 0x1000 0xf8893000 0x1000>;
	};

	fixedregulator {
		compatible = "regulator-fixed";
		regulator-name = "VCCPINT";
		regulator-min-microvolt = <0xf4240>;
		regulator-max-microvolt = <0xf4240>;
		regulator-boot-on;
		regulator-always-on;
		linux,phandle = <0x2>;
		phandle = <0x2>;
	};

	// PS Peripherals
	amba {
		u-boot,dm-pre-reloc;
		compatible = "simple-bus";
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		interrupt-parent = <0x4>;
		ranges;

		adc@f8007100 {
			compatible = "xlnx,zynq-xadc-1.00.a";
			reg = <0xf8007100 0x20>;
			interrupts = <0x0 0x7 0x4>;
			interrupt-parent = <0x4>;
			clocks = <0x1 0xc>;
		};

		can@e0008000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x1 0x13 0x1 0x24>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0008000 0x1000>;
			interrupts = <0x0 0x1c 0x4>;
			interrupt-parent = <0x4>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		can@e0009000 {
			compatible = "xlnx,zynq-can-1.0";
			status = "disabled";
			clocks = <0x1 0x14 0x1 0x25>;
			clock-names = "can_clk", "pclk";
			reg = <0xe0009000 0x1000>;
			interrupts = <0x0 0x33 0x4>;
			interrupt-parent = <0x4>;
			tx-fifo-depth = <0x40>;
			rx-fifo-depth = <0x40>;
		};

		// GPIO pins that interface with AD9361
		gpio@e000a000 {
			compatible = "xlnx,zynq-gpio-1.0";
			#gpio-cells = <0x2>;
			clocks = <0x1 0x2a>;
			gpio-controller;
			interrupt-controller;
			#interrupt-cells = <0x2>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x14 0x4>;
			reg = <0xe000a000 0x1000>;
			linux,phandle = <0x45>;
			phandle = <0x45>;
		};

		// Unused I2C
		i2c@e0004000 {
			compatible = "cdns,i2c-r1p10";
			status = "disabled";
			clocks = <0x1 0x26>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x19 0x4>;
			reg = <0xe0004000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		// I2C for Trenz System Controller
		i2c@e0005000 {
			compatible = "cdns,i2c-r1p10";
			status = "okay";
			clocks = <0x1 0x27>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x30 0x4>;
			reg = <0xe0005000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-frequency = <0x61a80>;
		};

		interrupt-controller@f8f01000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <0x3>;
			interrupt-controller;
			reg = <0xf8f01000 0x1000 0xf8f00100 0x100>;
			num_cpus = <0x2>;
			num_interrupts = <0x60>;
			linux,phandle = <0x4>;
			phandle = <0x4>;
		};

		cache-controller@f8f02000 {
			compatible = "arm,pl310-cache";
			reg = <0xf8f02000 0x1000>;
			interrupts = <0x0 0x2 0x4>;
			arm,data-latency = <0x3 0x2 0x2>;
			arm,tag-latency = <0x2 0x2 0x2>;
			cache-unified;
			cache-level = <0x2>;
		};

		memory-controller@f8006000 {
			compatible = "xlnx,zynq-ddrc-a05";
			reg = <0xf8006000 0x1000>;
		};

		ocmc@f800c000 {
			compatible = "xlnx,zynq-ocmc-1.0";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x3 0x4>;
			reg = <0xf800c000 0x1000>;
		};

		// UART
		serial@e0000000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "okay";
			clocks = <0x1 0x17 0x1 0x28>;
			clock-names = "uart_clk", "pclk";
			reg = <0xe0000000 0x1000>;
			interrupts = <0x0 0x1b 0x4>;
			device_type = "serial";
			port-number = <0x0>;
		};

		serial@e0001000 {
			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
			status = "disabled";
			clocks = <0x1 0x18 0x1 0x29>;
			clock-names = "uart_clk", "pclk";
			reg = <0xe0001000 0x1000>;
			interrupts = <0x0 0x32 0x4>;
			device_type = "serial";
			port-number = <0x1>;
		};

		// AD9361
		spi@e0006000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0006000 0x1000>;
			status = "okay";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x1a 0x4>;
			clocks = <0x1 0x19 0x1 0x22>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

			ad9361-phy@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				compatible = "adi,ad9361";
				reg = <0x0>;
				spi-cpha;
				spi-max-frequency = <0x989680>;
//				clocks = <0x42 0x0>;
				clocks = <0x42>;
				clock-names = "ad9361_ext_refclk";
				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
				adi,digital-interface-tune-skip-mode = <0x0>;
				adi,pp-tx-swap-enable;
				adi,pp-rx-swap-enable;
				adi,rx-frame-pulse-mode-enable;
				adi,lvds-mode-enable;
				adi,lvds-bias-mV = <0x96>;
				adi,lvds-rx-onchip-termination-enable;
				adi,rx-data-delay = <0x4>;
				adi,tx-fb-clock-delay = <0x7>;
				adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
				adi,2rx-2tx-mode-enable;
				adi,frequency-division-duplex-mode-enable;
				adi,rx-rf-port-input-select = <0x0>;
				adi,tx-rf-port-input-select = <0x0>;
				adi,tx-attenuation-mdB = <0x2710>;
				adi,tx-lo-powerdown-managed-enable;
				adi,rf-rx-bandwidth-hz = <0x112a880>;
				adi,rf-tx-bandwidth-hz = <0x112a880>;
				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,gc-rx1-mode = <0x2>;
				adi,gc-rx2-mode = <0x2>;
				adi,gc-adc-ovr-sample-size = <0x4>;
				adi,gc-adc-small-overload-thresh = <0x2f>;
				adi,gc-adc-large-overload-thresh = <0x3a>;
				adi,gc-lmt-overload-high-thresh = <0x320>;
				adi,gc-lmt-overload-low-thresh = <0x2c0>;
				adi,gc-dec-pow-measurement-duration = <0x2000>;
				adi,gc-low-power-thresh = <0x18>;
				adi,mgc-inc-gain-step = <0x2>;
				adi,mgc-dec-gain-step = <0x2>;
				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
				adi,agc-attack-delay-extra-margin-us = <0x1>;
				adi,agc-outer-thresh-high = <0x5>;
				adi,agc-outer-thresh-high-dec-steps = <0x2>;
				adi,agc-inner-thresh-high = <0xa>;
				adi,agc-inner-thresh-high-dec-steps = <0x1>;
				adi,agc-inner-thresh-low = <0xc>;
				adi,agc-inner-thresh-low-inc-steps = <0x1>;
				adi,agc-outer-thresh-low = <0x12>;
				adi,agc-outer-thresh-low-inc-steps = <0x2>;
				adi,agc-adc-small-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-inc-steps = <0x2>;
				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
				adi,agc-lmt-overload-large-inc-steps = <0x2>;
				adi,agc-gain-update-interval-us = <0x3e8>;
				adi,fagc-dec-pow-measurement-duration = <0x40>;
				adi,fagc-lp-thresh-increment-steps = <0x1>;
				adi,fagc-lp-thresh-increment-time = <0x5>;
				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
				adi,fagc-final-overrange-count = <0x3>;
				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
				adi,fagc-lmt-final-settling-steps = <0x1>;
				adi,fagc-lock-level = <0xa>;
				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
				adi,fagc-lock-level-lmt-gain-increase-enable;
				adi,fagc-lpf-final-settling-steps = <0x1>;
				adi,fagc-optimized-gain-offset = <0x5>;
				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
				adi,fagc-rst-gla-large-adc-overload-enable;
				adi,fagc-rst-gla-large-lmt-overload-enable;
				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
				adi,fagc-state-wait-time-ns = <0x104>;
				adi,fagc-use-last-lock-level-for-set-gain-enable;
				adi,rssi-restart-mode = <0x3>;
				adi,rssi-delay = <0x1>;
				adi,rssi-wait = <0x1>;
				adi,rssi-duration = <0x3e8>;
				adi,ctrl-outs-index = <0x0>;
				adi,ctrl-outs-enable-mask = <0xff>;
				adi,temp-sense-measurement-interval-ms = <0x3e8>;
				adi,temp-sense-offset-signed = <0xce>;
				adi,temp-sense-periodic-measurement-enable;
				adi,aux-dac-manual-mode-enable;
				adi,aux-dac1-default-value-mV = <0x0>;
				adi,aux-dac1-rx-delay-us = <0x0>;
				adi,aux-dac1-tx-delay-us = <0x0>;
				adi,aux-dac2-default-value-mV = <0x0>;
				adi,aux-dac2-rx-delay-us = <0x0>;
				adi,aux-dac2-tx-delay-us = <0x0>;
/*				en_agc-gpios = <0x45 0x62 0x0>;
				sync-gpios = <0x45 0x63 0x0>;
				reset-gpios = <0x45 0x64 0x0>;
				enable-gpios = <0x45 0x65 0x0>;
				txnrx-gpios = <0x45 0x66 0x0>;
*/				
				reset-gpios = <0x5 0x64 0x0>;
				sync-gpios = <0x5 0x63 0x0>;
				cal-sw1-gpios = <0x5 0x6b 0x0>;
				cal-sw2-gpios = <0x5 0x6c 0x0>;
				
				
				linux,phandle = <0x44>;
				phandle = <0x44>;
			};
			
			ad9361-phy-B@1 {
			    #address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				compatible = "adi,ad9361";
				reg = <0x1>;
				spi-cpha;
				spi-max-frequency = <0x989680>;
//				clocks = <0x42 0x0>;
				clocks = <0x42>;
				clock-names = "ad9361_ext_refclk";
				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
				adi,digital-interface-tune-skip-mode = <0x0>;
				adi,pp-tx-swap-enable;
				adi,pp-rx-swap-enable;
				adi,rx-frame-pulse-mode-enable;
				adi,lvds-mode-enable;
				adi,lvds-bias-mV = <0x96>;
				adi,lvds-rx-onchip-termination-enable;
				adi,rx-data-delay = <0x4>;
				adi,tx-fb-clock-delay = <0x7>;
				adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
				adi,2rx-2tx-mode-enable;
				adi,frequency-division-duplex-mode-enable;
				adi,rx-rf-port-input-select = <0x0>;
				adi,tx-rf-port-input-select = <0x0>;
				adi,tx-attenuation-mdB = <0x2710>;
				adi,tx-lo-powerdown-managed-enable;
				adi,rf-rx-bandwidth-hz = <0x112a880>;
				adi,rf-tx-bandwidth-hz = <0x112a880>;
				adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
				adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
				adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
				adi,gc-rx1-mode = <0x2>;
				adi,gc-rx2-mode = <0x2>;
				adi,gc-adc-ovr-sample-size = <0x4>;
				adi,gc-adc-small-overload-thresh = <0x2f>;
				adi,gc-adc-large-overload-thresh = <0x3a>;
				adi,gc-lmt-overload-high-thresh = <0x320>;
				adi,gc-lmt-overload-low-thresh = <0x2c0>;
				adi,gc-dec-pow-measurement-duration = <0x2000>;
				adi,gc-low-power-thresh = <0x18>;
				adi,mgc-inc-gain-step = <0x2>;
				adi,mgc-dec-gain-step = <0x2>;
				adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
				adi,agc-attack-delay-extra-margin-us = <0x1>;
				adi,agc-outer-thresh-high = <0x5>;
				adi,agc-outer-thresh-high-dec-steps = <0x2>;
				adi,agc-inner-thresh-high = <0xa>;
				adi,agc-inner-thresh-high-dec-steps = <0x1>;
				adi,agc-inner-thresh-low = <0xc>;
				adi,agc-inner-thresh-low-inc-steps = <0x1>;
				adi,agc-outer-thresh-low = <0x12>;
				adi,agc-outer-thresh-low-inc-steps = <0x2>;
				adi,agc-adc-small-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-exceed-counter = <0xa>;
				adi,agc-adc-large-overload-inc-steps = <0x2>;
				adi,agc-lmt-overload-large-exceed-counter = <0xa>;
				adi,agc-lmt-overload-small-exceed-counter = <0xa>;
				adi,agc-lmt-overload-large-inc-steps = <0x2>;
				adi,agc-gain-update-interval-us = <0x3e8>;
				adi,fagc-dec-pow-measurement-duration = <0x40>;
				adi,fagc-lp-thresh-increment-steps = <0x1>;
				adi,fagc-lp-thresh-increment-time = <0x5>;
				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
				adi,fagc-final-overrange-count = <0x3>;
				adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
				adi,fagc-lmt-final-settling-steps = <0x1>;
				adi,fagc-lock-level = <0xa>;
				adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
				adi,fagc-lock-level-lmt-gain-increase-enable;
				adi,fagc-lpf-final-settling-steps = <0x1>;
				adi,fagc-optimized-gain-offset = <0x5>;
				adi,fagc-power-measurement-duration-in-state5 = <0x40>;
				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
				adi,fagc-rst-gla-large-adc-overload-enable;
				adi,fagc-rst-gla-large-lmt-overload-enable;
				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
				adi,fagc-state-wait-time-ns = <0x104>;
				adi,fagc-use-last-lock-level-for-set-gain-enable;
				adi,rssi-restart-mode = <0x3>;
				adi,rssi-delay = <0x1>;
				adi,rssi-wait = <0x1>;
				adi,rssi-duration = <0x3e8>;
				adi,ctrl-outs-index = <0x0>;
				adi,ctrl-outs-enable-mask = <0xff>;
				adi,temp-sense-measurement-interval-ms = <0x3e8>;
				adi,temp-sense-offset-signed = <0xce>;
				adi,temp-sense-periodic-measurement-enable;
				adi,aux-dac-manual-mode-enable;
				adi,aux-dac1-default-value-mV = <0x0>;
				adi,aux-dac1-rx-delay-us = <0x0>;
				adi,aux-dac1-tx-delay-us = <0x0>;
				adi,aux-dac2-default-value-mV = <0x0>;
				adi,aux-dac2-rx-delay-us = <0x0>;
				adi,aux-dac2-tx-delay-us = <0x0>;
//				en_agc-gpios = <0x45 0x62 0x0>;
				reset-gpios = <0x45 0x71 0x0>;
//				enable-gpios = <0x45 0x65 0x0>;
//				txnrx-gpios = <0x45 0x66 0x0>;
				linux,phandle = <0x46>;
				phandle = <0x46>;
			};
		};

		// ADF45 on PMOD, not enabled in this hardware
		spi@e0007000 {
			compatible = "xlnx,zynq-spi-r1p6";
			reg = <0xe0007000 0x1000>;
			status = "disabled";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x31 0x4>;
			clocks = <0x1 0x1a 0x1 0x23>;
			clock-names = "ref_clk", "pclk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;

/*
                        adf4351-udc-tx-pmod@0 {
                                compatible = "adi,adf4351";
                                reg = <0x0>;
                                spi-max-frequency = <0x989680>;
                                clocks = <0x43>;
                                clock-names = "clkin";
                                adi,channel-spacing = <0xf4240>;
                                adi,power-up-frequency = <0x160dc080>;
                                adi,phase-detector-polarity-positive-enable;
                                adi,charge-pump-current = <0x9c4>;
                                adi,output-power = <0x3>;
                                adi,mute-till-lock-enable;
                                adi,muxout-select = <0x6>;
                                gpios = <0x45 0x68 0x0>;
                        };

                        adf4351-udc-rx-pmod@1 {
                                compatible = "adi,adf4351";
                                reg = <0x1>;
                                spi-max-frequency = <0x989680>;
                                clocks = <0x43>;
                                clock-names = "clkin";
                                adi,channel-spacing = <0xf4240>;
                                adi,power-up-frequency = <0x1443fd00>;
                                adi,phase-detector-polarity-positive-enable;
                                adi,charge-pump-current = <0x9c4>;
                                adi,output-power = <0x3>;
                                adi,mute-till-lock-enable;
                                adi,muxout-select = <0x6>;
                                gpios = <0x45 0x67 0x0>;
                        };
*/
		};

		// Programming Flash
		spi@e000d000 {
			clock-names = "ref_clk", "pclk";
			clocks = <0x1 0xa 0x1 0x2b>;
			compatible = "xlnx,zynq-qspi-1.0";
			status = "okay";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x13 0x4>;
			reg = <0xe000d000 0x1000>;
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			is-dual = <0x0>;
			num-cs = <0x1>;
			spi-rx-bus-width = <0x4>;
			spi-tx-bus-width = <0x4>;

			flash@0 {
				compatible = "n25q512a", "micron,m25p80";
				reg = <0x0>;
				#address-cells = <0x1>;
				#size-cells = <0x1>;
				spi-max-frequency = <0x2faf080>;

				partition@0x00000000 {
					label = "boot";
					reg = <0x0 0x500000>;
				};

				partition@0x00500000 {
					label = "bootenv";
					reg = <0x500000 0x20000>;
				};

				partition@0x00520000 {
					label = "kernel";
					reg = <0x520000 0xa80000>;
				};

				partition@0x00fa0000 {
					label = "spare";
					reg = <0xfa0000 0x0>;
				};
			};
		};

		// Ethernet output from PS
		ethernet@e000b000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000b000 0x1000>;
			status = "okay";
			interrupts = <0x0 0x16 0x4>;
			clocks = <0x1 0x1e 0x1 0x1e 0x1 0xd>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			phy-mode = "rgmii-id";
			xlnx,ptp-enet-clock = <0x69f6bcb>;
			local-mac-address = [00 0a 35 00 1e 53];
		};

		ethernet@e000c000 {
			compatible = "cdns,zynq-gem", "cdns,gem";
			reg = <0xe000c000 0x1000>;
			status = "disabled";
			interrupts = <0x0 0x2d 0x4>;
			clocks = <0x1 0x1f 0x1 0x1f 0x1 0xe>;
			clock-names = "pclk", "hclk", "tx_clk";
			#address-cells = <0x1>;
			#size-cells = <0x0>;
		};

		// SD Card 0
		sdhci@e0100000 {
			compatible = "arasan,sdhci-8.9a";
			status = "okay";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <0x1 0x15 0x1 0x20>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x18 0x4>;
			reg = <0xe0100000 0x1000>;
			xlnx,has-cd = <0x0>;
			xlnx,has-power = <0x0>;
			xlnx,has-wp = <0x0>;
		};

		// SD Card 1
		sdhci@e0101000 {
			compatible = "arasan,sdhci-8.9a";
			status = "disabled";
			clock-names = "clk_xin", "clk_ahb";
			clocks = <0x1 0x16 0x1 0x21>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x2f 0x4>;
			reg = <0xe0101000 0x1000>;
			xlnx,has-cd = <0x0>;
			xlnx,has-power = <0x0>;
			xlnx,has-wp = <0x0>;
		};

		// System controller
		slcr@f8000000 {
			u-boot,dm-pre-reloc;
			#address-cells = <0x1>;
			#size-cells = <0x1>;
			compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
			reg = <0xf8000000 0x1000>;
			ranges;
			linux,phandle = <0x5>;
			phandle = <0x5>;

			clkc@100 {
				u-boot,dm-pre-reloc;
				#clock-cells = <0x1>;
				compatible = "xlnx,ps7-clkc";
				fclk-enable = <0x3>;
				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci", "lqspi", "smc", "pcap", "gem0", "gem1", "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", "dma", "usb0_aper", "usb1_aper", "gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper", "swdt", "dbg_trc", "dbg_apb";
				reg = <0x100 0x100>;
				ps-clk-frequency = <0x1fca055>;
				linux,phandle = <0x1>;
				phandle = <0x1>;
			};

			rstc@200 {
				compatible = "xlnx,zynq-reset";
				reg = <0x200 0x48>;
				#reset-cells = <0x1>;
				syscon = <0x5>;
			};

			pinctrl@700 {
				compatible = "xlnx,pinctrl-zynq";
				reg = <0x700 0x200>;
				syscon = <0x5>;
			};
		};

		dmac@f8003000 {
			compatible = "arm,pl330", "arm,primecell";
			reg = <0xf8003000 0x1000>;
			interrupt-parent = <0x4>;
			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", "dma4", "dma5", "dma6", "dma7";
			interrupts = <0x0 0xd 0x4 0x0 0xe 0x4 0x0 0xf 0x4 0x0 0x10 0x4 0x0 0x11 0x4 0x0 0x28 0x4 0x0 0x29 0x4 0x0 0x2a 0x4 0x0 0x2b 0x4>;
			#dma-cells = <0x1>;
			#dma-channels = <0x8>;
			#dma-requests = <0x4>;
			clocks = <0x1 0x1b>;
			clock-names = "apb_pclk";
		};

		devcfg@f8007000 {
			compatible = "xlnx,zynq-devcfg-1.0";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x8 0x4>;
			reg = <0xf8007000 0x100>;
			clocks = <0x1 0xc 0x1 0xf 0x1 0x10 0x1 0x11 0x1 0x12>;
			clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
			syscon = <0x5>;
			linux,phandle = <0x3>;
			phandle = <0x3>;
		};

		efuse@f800d000 {
			compatible = "xlnx,zynq-efuse";
			reg = <0xf800d000 0x20>;
		};

		timer@f8f00200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0xf8f00200 0x20>;
			interrupts = <0x1 0xb 0x301>;
			interrupt-parent = <0x4>;
			clocks = <0x1 0x4>;
		};

		timer@f8001000 {
			interrupt-parent = <0x4>;
			interrupts = <0x0 0xa 0x4 0x0 0xb 0x4 0x0 0xc 0x4>;
			compatible = "cdns,ttc";
			clocks = <0x1 0x6>;
			reg = <0xf8001000 0x1000>;
		};

		timer@f8002000 {
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x25 0x4 0x0 0x26 0x4 0x0 0x27 0x4>;
			compatible = "cdns,ttc";
			clocks = <0x1 0x6>;
			reg = <0xf8002000 0x1000>;
		};

		timer@f8f00600 {
			interrupt-parent = <0x4>;
			interrupts = <0x1 0xd 0x301>;
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xf8f00600 0x20>;
			clocks = <0x1 0x4>;
		};

		usb@e0002000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <0x1 0x1c>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x15 0x4>;
			reg = <0xe0002000 0x1000>;
			phy_type = "ulpi";
		};

		usb@e0003000 {
			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
			status = "disabled";
			clocks = <0x1 0x1d>;
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x2c 0x4>;
			reg = <0xe0003000 0x1000>;
			phy_type = "ulpi";
		};

		watchdog@f8005000 {
			clocks = <0x1 0x2d>;
			compatible = "cdns,wdt-r1p2";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x9 0x1>;
			reg = <0xf8005000 0x1000>;
			timeout-sec = <0xa>;
		};
	};

	// AXI Bus
	amba_pl {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "simple-bus";
		ranges;

		// ADI Control - RX Channel
		cf-ad9361-A@79020000 {
			compatible = "adi,axi-ad9361-6.00.a";
			reg = <0x79020000 0x6000>;
			dmas = <0x72 0x0>;
			dma-names = "rx";
			spibus-connected = <0x44>;
			slavecore-reg = <0x79040000 0x6000>;
//			phandle = <0x70>;
//			linux,phandle = <0x70>;
		};

		// ADI Control - TX Channel
		cf-ad9361-dds-core-lpc@79024000 {
			compatible = "adi,axi-ad9361x2-dds-6.00.a";
			reg = <0x79024000 0x1000>;
			clocks = <0x44 0xd>; // FIXME Second #?
			clock-names = "sampl_clk";
			dmas = <0x73 0x0>;
			dma-names = "tx";
			slavecore-reg = <0x79044000 0x1000>;
		};
		
		cf-ad9361-B@79040000 {
			compatible = "adi,axi-ad9361-6.00.a";
			reg = <0x79040000 0x6000>;
			spibus-connected = <0x46>;
		};
		
		cf-ad9361-dds-core-B@79044000 {
			compatible = "adi,axi-ad9361x2-dds-6.00.a";
			reg = <0x79044000 0x1000>;
			clocks = <0x46 0xd>;
			clock-names = "sampl_clk";
			mastercore-reg = <0x79024000 0x1000>;
		};






        dma@7c400000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x7c400000 0x10000>;
			#dma-cells = <0x1>;
			interrupts = <0x0 0x39 0x0>;
			clocks = <0x1 0x10>;
			linux,phandle = <0x72>;
			phandle = <0x72>;

			dma-channel {
				adi,buswidth = <0x40>;
				adi,type = <0x0>;
			};
		};

		dma@7c420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x7c420000 0x10000>;
			#dma-cells = <0x1>;
			interrupts = <0x0 0x38 0x0>;
			clocks = <0x2 0x10>;
			linux,phandle = <0x73>;
			phandle = <0x73>;

			dma-channel {
				adi,buswidth = <0x40>;
				adi,type = <0x1>;
				adi,cyclic;
			};
		};



/*

		// RX DMA Channel
		axi_dmac@7c400000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x7c400000 0x10000>;
			#dma-cells = <0x1>;
			interrupts = <0x0 0x39 0x4>;
			clocks = <0x1 0x10>;
			linux,phandle = <0x72>;
			phandle = <0x72>;

			adi,channels {
				#size-cells = <0x0>;
				#address-cells = <0x1>;

				dma-channel@0 {
					reg = <0x0>;
					adi,source-bus-width = <0x40>;
					adi,source-bus-type = <0x2>;
					adi,destination-bus-width = <0x40>;
					adi,destination-bus-type = <0x0>;
				};
			};
		};

		// TX DMA Channel
		axi_dmac@7c420000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x7c420000 0x10000>;
			#dma-cells = <0x1>;
			interrupts = <0x0 0x20 0x4>;
			clocks = <0x1 0x10>;
			linux,phandle = <0x73>;
			phandle = <0x73>;

			adi,channels {
                                #size-cells = <0x0>;
                                #address-cells = <0x1>;

                                dma-channel@0 {
                                        reg = <0x0>;
                                        adi,source-bus-width = <0x40>;
                                        adi,source-bus-type = <0x0>;
                                        adi,destination-bus-width = <0x40>;
                                        adi,destination-bus-type = <0x2>;
                                };
                        };
		};
*/

		// FMC I2C Devices
		i2c@41620000 {
			#address-cells = <0x1>;
			#size-cells = <0x0>;
			clock-names = "s_axi_aclk";
			clocks = <0x1 0xf>;
			compatible = "xlnx,xps-iic-2.00.a";
			interrupt-names = "iic2intc_irpt";
			interrupt-parent = <0x4>;
			interrupts = <0x0 0x21 0x4>;
			reg = <0x41620000 0x10000>;

			ad7291@2f {
                                compatible = "adi,ad7291";
                                reg = <0x2f>;
                        };

                        eeprom@50 {
                                compatible = "at24,24c02";
                                reg = <0x50>;
                        };
		};
	};

	chosen {
		// We boot from the SD Card, Partition #2, from an ext4 filesystem
		bootargs = "console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait";
		// Select UART0 as the stdout
		stdout-path = "serial0:115200n8";
	};

	aliases {
		ethernet0 = "/amba/ethernet@e000b000";
		i2c0 = "/amba_pl/i2c@41620000";
		i2c1 = "/amba_pl/i2c@41600000";
		i2c2 = "/amba/i2c@e0005000";
		serial0 = "/amba/serial@e0000000";
		serial1 = "/amba/serial@e0001000";
		spi0 = "/amba/spi@e000d000";
		spi1 = "/amba/spi@e0006000";
		spi2 = "/amba/spi@e0007000";
	};

	// 1GB of memory
	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	clocks {
		// FCLK0 - 100MHz
		clock@0 {
			compatible = "fixed-clock";
			clock-frequency = <80000000>;
			clock-output-names = "ad9361_ext_refclk";
			#clock-cells = <0x0>;
			linux,phandle = <0x42>;
			phandle = <0x42>;
		};
/*
		// FCLK1 - 250MHz
		clock@1 {
			compatible = "fixed-clock";
			clock-frequency = <0x17d7840>;
			clock-output-names = "refclk";
			#clock-cells = <0x0>;
			linux,phandle = <0x43>;
			phandle = <0x43>;
		};     
*/
	};
};
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
						
				
						
				
				
		
		
        
			
		
        
	
        

        

        • 

	

      • 
	
        



	
			
		
	



        
	
        
		
        
							
					
        
		
        
			
													+1
							
			
				
									
							        
			
			
			
          
            
						
                            
            
            				
            
                on Jun 25, 2019 2:42 PM
            
            
					
          
	
          

		
		
          
					
          I did not properly update the spi connections in the system_top.v file. Once I modified the spi connections to look like those in the fmcomms5/zc702 project everything worked out.
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
				
						
						
				
				
		
		
          
			
		
          
	
          

          

          • 

	

        • 
	
          



	
		
	
	



          
	
          
		
          
							
					
          
		
          
			
													0
							
			
				
									
							        
			
			
			
            
            
						
                            
            
            				
            
                on Mar 2, 2023 9:32 AM
            
            
												
						in reply to gpaden
					
									
            
	
            

		
		
            
					
            Hi friend can you elaborate the changes you have made in the system_top.v file of zcu102. 
            

            Thanks alot,
            

            Potato
            
			
            

		
			
	      

		
		
	
            
	
            
		
            
			
		
            
	
            
	
            
		
						
						
				
						
				
				
		
		
            
			
		
            
	
            

            

            •