Whether External clock i/p level of 1.8V is acceptable range for SOM(AD9361) in picozed

In picozed schematic, it is mentioned that AD9361_CLK must be 1.3 Vpp max, but the internal reference clock signal to ADG772(U5) is at 1.8V,

Will it not affect XTALN pin level requirement of AD9361. The capacitive voltage divider may not do voltage division since, C165  is DNI in the circuit.

Whether i can feed 1.8V clock signal to ADG772 input(pin1)

Top Replies

    •  Analog Employees 
    May 10, 2019 +1 verified
    hematic, it is mentioned that AD9361_CLK must be 1.3 Vpp max, but the internal reference clock signal to

    C165 is not needed because the capacitance of the XTALN pin is enough