ad9361 devicetree

Hi, 

I'm trying to get a custom FMCOMMS3 like daughterboard to work with a ZynqMP.

Our Vivado project was updated to include all the IP cores from the ZCU102 + FMCOMMS2 project (here)

Most of the project seems to be working, the AD9361 spi node, the DMAs and the cf-ad9361-dds-core-lpc are probed with no apparent error but Linux fails to initialize the cf-ad9361-lpc core.

here is a sample of our bootlog showing the error: 

[root@zynqmp ~]$ dmesg | grep -i ad9361                                                                                                                 
[    1.708884] ad9361 spi2.0: ad9361_probe : enter (ad9361)                                                                                                   
[    1.934319] ad9361 spi2.0: ad9361_probe : AD936x Rev 2 successfully initialized                                                                            
[    1.958005] cf_axi_dds 80004000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x80004000 mapped to 0xffffff8008ff5000, probed DDS
 AD9361                                                                                                                                                       
[    2.479485] ad9361 spi2.0: Failed to set BB ref clock rate (-22)                                                                                           
[    3.428878] ad9361 spi2.0: Calibration TIMEOUT (0x5E, 0x80)                                                                                                
[    3.455354] ad9361 spi2.0: Failed to set BB ref clock rate (-22)                                                                                           
[    3.607736] ad9361 spi2.0: ad9361_dig_tune_delay: Tuning RX FAILED!                                                                                        
[    3.614246] cf_axi_adc: probe of 80000000.cf-ad9361-lpc failed with error -5                                                                               

here is a section of our devicetree based on this file.

cf_ad9361_adc_core_0: cf-ad9361-lpc@80000000 {         
        compatible = "adi,axi-ad9361-6.00.a";          
        reg = < 0x00 0x80000000 0x00 0x6000 >;         
        dmas = <&rx_dma 0>;                            
        dma-names = "rx";                              
        spibus-connected = <&adc0_ad9361>;             
};                                                     
                                                       
cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@80004000 {
        compatible = "adi,axi-ad9361-dds-6.00.a";      
        reg = < 0x00 0x80004000 0x00 0x1000 >;         
        clocks = <&adc0_ad9361 13>;                    
        clock-names = "sampl_clk";                     
        dmas = <&tx_dma 0>;                            
        dma-names = "tx";                              
};                                                     

the base address of the axi_ad9361 core is 0x80000000.

I couldn't find information on how to deduce the reg parameters for these two nodes. Am I missing something in the dts?

Where is this BB ref clock setup, is it a parameter in Vivado? 

Thanks for your help, 

Liam 

  • Hi, 

    I didn't make any changes to those values. 

    How can I find the information needed to set these frequencies?

    Thanks,

    Liam

  • 0
    •  Analog Employees 
    on Mar 26, 2019 4:32 PM over 1 year ago in reply to lvb

    You must not alter these frequencies. 

    Can you provide your entire dmesg?

    and please read /sys/kernel/debug/clk/clk summary as well.

    Also provide your complete device tree.

    -Michael

  • I just leaned that we are using the external oscillator on our board. I set the 'adi,xo-disable-use-ext-refclk-enable' but I'm still having the same issues with the BB ref clock.

    here is our complete dmesg:

    [    0.000000] Booting Linux on physical CPU 0x0
    [    0.000000] Linux version 4.14.0 (lvb@pepper.xiphos.ca) (gcc version 8.1.1 20180626 (Red Hat Cross 8.1.1-3) (GCC)) #8 SMP Tue Mar 26 14:09:22 EDT 2019
    [    0.000000] Boot CPU: AArch64 Processor [410fd034]
    [    0.000000] Machine model: Xiphos Q8 RevA
    [    0.000000] earlycon: cdns0 at MMIO 0x00000000ff000000 (options '115200n8')
    [    0.000000] bootconsole [cdns0] enabled
    [    0.000000] cma: Reserved 256 MiB at 0x000000006dc00000
    [    0.000000] On node 0 totalpages: 524288
    [    0.000000]   DMA zone: 7168 pages used for memmap
    [    0.000000]   DMA zone: 0 pages reserved
    [    0.000000]   DMA zone: 524288 pages, LIFO batch:31
    [    0.000000] psci: probing for conduit method from DT.
    [    0.000000] psci: PSCIv1.1 detected in firmware.
    [    0.000000] psci: Using standard PSCI v0.2 function IDs
    [    0.000000] psci: MIGRATE_INFO_TYPE not supported.
    [    0.000000] random: fast init done
    [    0.000000] percpu: Embedded 20 pages/cpu @ffffffc07ff6d000 s44440 r8192 d29288 u81920
    [    0.000000] pcpu-alloc: s44440 r8192 d29288 u81920 alloc=20*4096
    [    0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 
    [    0.000000] Detected VIPT I-cache on CPU0
    [    0.000000] CPU features: enabling workaround for ARM erratum 845719
    [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 517120
    [    0.000000] Kernel command line: console=ttyPS0,115200 earlycon clk_ignore_unused serial=1013 rootwait=1 rw rootfstype=ubifs ubi.mtd=qspi0-nom-rootfs root=ubi0:q8-reva-rootfs
    [    0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.000000] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes)
    [    0.000000] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes)
    [    0.000000] Memory: 1787948K/2097152K available (7422K kernel code, 560K rwdata, 4120K rodata, 384K init, 2100K bss, 47060K reserved, 262144K cma-reserved)
    [    0.000000] Virtual kernel memory layout:
    [    0.000000]     modules : 0xffffff8000000000 - 0xffffff8008000000   (   128 MB)
    [    0.000000]     vmalloc : 0xffffff8008000000 - 0xffffffbebfff0000   (   250 GB)
    [    0.000000]       .text : 0xffffff8008080000 - 0xffffff80087c0000   (  7424 KB)
    [    0.000000]     .rodata : 0xffffff80087c0000 - 0xffffff8008bd0000   (  4160 KB)
    [    0.000000]       .init : 0xffffff8008bd0000 - 0xffffff8008c30000   (   384 KB)
    [    0.000000]       .data : 0xffffff8008c30000 - 0xffffff8008cbc008   (   561 KB)
    [    0.000000]        .bss : 0xffffff8008cbc008 - 0xffffff8008ec9030   (  2101 KB)
    [    0.000000]     fixed   : 0xffffffbefe7fd000 - 0xffffffbefec00000   (  4108 KB)
    [    0.000000]     PCI I/O : 0xffffffbefee00000 - 0xffffffbeffe00000   (    16 MB)
    [    0.000000]     vmemmap : 0xffffffbf00000000 - 0xffffffc000000000   (     4 GB maximum)
    [    0.000000]               0xffffffbf00000000 - 0xffffffbf01c00000   (    28 MB actual)
    [    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc080000000   (  2048 MB)
    [    0.000000] Hierarchical RCU implementation.
    [    0.000000] 	RCU event tracing is enabled.
    [    0.000000] 	RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
    [    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
    [    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
    [    0.000000] GIC: Adjusting CPU interface base to 0x00000000f902f000
    [    0.000000] GIC: Using split EOI/Deactivate mode
    [    0.000000] arch_timer: cp15 timer(s) running at 33.33MHz (phys).
    [    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x7b0074340, max_idle_ns: 440795202884 ns
    [    0.000004] sched_clock: 56 bits at 33MHz, resolution 30ns, wraps every 2199023255543ns
    [    0.008225] Console: colour dummy device 80x25
    [    0.012495] Calibrating delay loop (skipped), value calculated using timer frequency.. 66.66 BogoMIPS (lpj=133332)
    [    0.022771] pid_max: default: 32768 minimum: 301
    [    0.027468] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.034025] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes)
    [    0.041850] ASID allocator initialised with 65536 entries
    [    0.047111] Hierarchical SRCU implementation.
    [    0.051790] zynqmp_plat_init Platform Management API v1.0
    [    0.057002] zynqmp_plat_init Trustzone version v1.0
    [    0.061948] smp: Bringing up secondary CPUs ...
    [    0.066625] Detected VIPT I-cache on CPU1
    [    0.066666] CPU1: Booted secondary processor [410fd034]
    [    0.066970] Detected VIPT I-cache on CPU2
    [    0.066988] CPU2: Booted secondary processor [410fd034]
    [    0.067271] Detected VIPT I-cache on CPU3
    [    0.067289] CPU3: Booted secondary processor [410fd034]
    [    0.067330] smp: Brought up 1 node, 4 CPUs
    [    0.098743] SMP: Total of 4 processors activated.
    [    0.103417] CPU features: detected feature: 32-bit EL0 Support
    [    0.109215] CPU: All CPU(s) started at EL2
    [    0.113288] alternatives: patching kernel code
    [    0.118758] devtmpfs: initialized
    [    0.127252] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
    [    0.136804] futex hash table entries: 1024 (order: 5, 131072 bytes)
    [    0.149536] pinctrl core: initialized pinctrl subsystem
    [    0.155273] NET: Registered protocol family 16
    [    0.160326] cpuidle: using governor menu
    [    0.164799] vdso: 2 pages (1 code @ ffffff80087c6000, 1 data @ ffffff8008c34000)
    [    0.172003] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
    [    0.179356] DMA: preallocated 256 KiB pool for atomic allocations
    [    0.215912] ARM CCI_400_r1 PMU driver probed
    [    0.220427] zynqmp-pinctrl ff180000.pinctrl: zynqmp pinctrl initialized
    [    0.235152] reset_zynqmp reset-controller: Xilinx zynqmp reset driver probed
    [    0.247970] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
    [    0.255505] GPIO IRQ not connected
    [    0.258730] XGpio: /amba_pl@0/gpio@80012000: registered, base is 508, ngpio is 4
    [    0.266356] XGpio: /amba_pl@0/gpio@80013000: registered, base is 506, ngpio is 2
    [    0.273638] xilinx-gpio a0001000.gpio: names 14 do not match number of GPIOs 5
    [    0.280938] GPIO IRQ not connected
    [    0.284153] XGpio: /amba_pl@0/gpio@a0001000: registered, base is 501, ngpio is 5
    [    0.291715] GPIO IRQ not connected
    [    0.294925] XGpio: /amba_pl@0/gpio@a0002000: registered, base is 499, ngpio is 2
    [    0.302459] GPIO IRQ not connected
    [    0.305675] XGpio: /amba_pl@0/gpio@a0005000: registered, base is 497, ngpio is 2
    [    0.313216] GPIO IRQ not connected
    [    0.316427] XGpio: /amba_pl@0/gpio@a0006000: registered, base is 496, ngpio is 1
    [    0.323962] GPIO IRQ not connected
    [    0.327170] XGpio: /amba_pl@0/gpio@a0007000: registered, base is 495, ngpio is 1
    [    0.334763] GPIO IRQ not connected
    [    0.337975] XGpio: /amba_pl@0/xsc_q8_zynq_pa3_bridge_axi@a2000000/pa3_crp@a2000000: registered, base is 486, ngpio is 9
    [    0.348722] GPIO IRQ not connected
    [    0.352199] PLL: shutdown
    [    0.354741] PLL: enable
    [    0.357229] XGpio: setting gpio2-line-names
    [    0.361255] XGpio: /amba_pl@0/xsc_q8_zynq_pa3_bridge_axi@a2000000/pa3_crp@a2000000: dual channel registered, base is 477
    [    0.373332] SCSI subsystem initialized
    [    0.376940] libata version 3.00 loaded.
    [    0.377110] usbcore: registered new interface driver usbfs
    [    0.382430] usbcore: registered new interface driver hub
    [    0.387722] usbcore: registered new device driver usb
    [    0.392767] pps_core: LinuxPPS API ver. 1 registered
    [    0.397623] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    [    0.406717] PTP clock support registered
    [    0.410616] EDAC MC: Ver: 3.0.0
    [    0.413878] PLL: shutdown
    [    0.416676] zynqmp-ipi ff9905c0.mailbox: Probed ZynqMP IPI Mailbox driver.
    [    0.423464] FPGA manager framework
    [    0.426898] fpga-region fpga-full: FPGA Region probed
    [    0.432510] clocksource: Switched to clocksource arch_sys_counter
    [    0.438514] VFS: Disk quotas dquot_6.6.0
    [    0.442349] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
    [    0.453716] NET: Registered protocol family 2
    [    0.458258] TCP established hash table entries: 16384 (order: 5, 131072 bytes)
    [    0.465388] TCP bind hash table entries: 16384 (order: 6, 262144 bytes)
    [    0.472212] TCP: Hash tables configured (established 16384 bind 16384)
    [    0.478644] UDP hash table entries: 1024 (order: 3, 32768 bytes)
    [    0.484549] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes)
    [    0.491049] NET: Registered protocol family 1
    [    0.495467] RPC: Registered named UNIX socket transport module.
    [    0.501196] RPC: Registered udp transport module.
    [    0.505862] RPC: Registered tcp transport module.
    [    0.510532] RPC: Registered tcp NFSv4.1 backchannel transport module.
    [    0.516940] PCI: CLS 0 bytes, default 128
    [    0.517952] hw perfevents: no interrupt-affinity property for /pmu, guessing.
    [    0.525271] hw perfevents: enabled with armv8_pmuv3 PMU driver, 7 counters available
    [    0.533417] audit: initializing netlink subsys (disabled)
    [    0.538702] audit: type=2000 audit(0.371:1): state=initialized audit_enabled=0 res=1
    [    0.539043] workingset: timestamp_bits=62 max_order=19 bucket_order=0
    [    0.553219] NFS: Registering the id_resolver key type
    [    0.558111] Key type id_resolver registered
    [    0.562234] Key type id_legacy registered
    [    0.566220] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
    [    0.599351] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
    [    0.606566] io scheduler noop registered
    [    0.610442] io scheduler deadline registered
    [    0.614696] io scheduler cfq registered (default)
    [    0.619351] io scheduler mq-deadline registered
    [    0.623848] io scheduler kyber registered
    [    0.629218] PLL: enable
    [    0.632349] xilinx-zynqmp-dma fd500000.dma: ZynqMP DMA driver Probe success
    [    0.639284] xilinx-zynqmp-dma fd510000.dma: ZynqMP DMA driver Probe success
    [    0.646195] xilinx-zynqmp-dma fd520000.dma: ZynqMP DMA driver Probe success
    [    0.653116] xilinx-zynqmp-dma fd530000.dma: ZynqMP DMA driver Probe success
    [    0.660031] xilinx-zynqmp-dma fd540000.dma: ZynqMP DMA driver Probe success
    [    0.666956] xilinx-zynqmp-dma fd550000.dma: ZynqMP DMA driver Probe success
    [    0.673871] xilinx-zynqmp-dma fd560000.dma: ZynqMP DMA driver Probe success
    [    0.680797] xilinx-zynqmp-dma fd570000.dma: ZynqMP DMA driver Probe success
    [    0.687787] xilinx-zynqmp-dma ffa80000.dma: ZynqMP DMA driver Probe success
    [    0.694703] xilinx-zynqmp-dma ffa90000.dma: ZynqMP DMA driver Probe success
    [    0.701623] xilinx-zynqmp-dma ffaa0000.dma: ZynqMP DMA driver Probe success
    [    0.708546] xilinx-zynqmp-dma ffab0000.dma: ZynqMP DMA driver Probe success
    [    0.715466] xilinx-zynqmp-dma ffac0000.dma: ZynqMP DMA driver Probe success
    [    0.722386] xilinx-zynqmp-dma ffad0000.dma: ZynqMP DMA driver Probe success
    [    0.729303] xilinx-zynqmp-dma ffae0000.dma: ZynqMP DMA driver Probe success
    [    0.736224] xilinx-zynqmp-dma ffaf0000.dma: ZynqMP DMA driver Probe success
    [    0.773416] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
    [    0.782169] 80030000.serial: ttyS2 at MMIO 0x80031000 (irq = 46, base_baud = 6249937) is a 16550A
    [    0.791924] 80040000.serial: ttyS3 at MMIO 0x80041000 (irq = 47, base_baud = 6249937) is a 16550A
    [    0.801339] a0010000.serial: ttyS0 at MMIO 0xa0011000 (irq = 48, base_baud = 6249937) is a 16550A
    [    0.813481] cacheinfo: Unable to detect cache hierarchy for CPU 0
    [    0.824233] brd: module loaded
    [    0.831313] loop: module loaded
    [    0.835484] mtdoops: mtd device (mtddev=name/number) must be supplied
    [    0.843928] m25p80 spi0.0: SPI-NOR-UniqueID 104400fa2b94000af6ff1d0049bf644a12
    [    0.851352] m25p80 spi0.0: n25q00a (262144 Kbytes)
    [    0.856003] 18 ofpart partitions found on MTD device spi0.0
    [    0.861492] Creating 18 MTD partitions on "spi0.0":
    [    0.866339] 0x000004000000-0x000004a00000 : "qspi0-gold-fw"
    [    0.872402] 0x000004a20000-0x000008000000 : "qspi0-gold-rootfs"
    [    0.878560] 0x000004a00000-0x000004a20000 : "qspi0-gold-xscinfo"
    [    0.884786] 0x000004000000-0x000008000000 : "qspi0-gold"
    [    0.890320] 0x000000000000-0x000000a00000 : "qspi0-nom-fw"
    [    0.896033] 0x000000a20000-0x000004000000 : "qspi0-nom-rootfs"
    [    0.902075] 0x000000a00000-0x000000a20000 : "qspi0-nom-xscinfo"
    [    0.908223] 0x000000000000-0x000004000000 : "qspi0-nom"
    [    0.913667] 0x000000000000-0x000008000000 : "qspi0"
    [    0.918778] 0x00000c000000-0x00000ca00000 : "qspi1-gold-fw"
    [    0.924585] 0x00000ca20000-0x000010000000 : "qspi1-gold-rootfs"
    [    0.930727] 0x00000ca00000-0x00000ca20000 : "qspi1-gold-xscinfo"
    [    0.936961] 0x00000c000000-0x000010000000 : "qspi1-gold"
    [    0.942482] 0x000008000000-0x000008a00000 : "qspi1-nom-fw"
    [    0.948201] 0x000008a20000-0x00000c000000 : "qspi1-nom-rootfs"
    [    0.954242] 0x000008a00000-0x000008a20000 : "qspi1-nom-xscinfo"
    [    0.960387] 0x000008000000-0x00000c000000 : "qspi1-nom"
    [    0.965841] 0x000008000000-0x000010000000 : "qspi1"
    [    0.972166] libphy: Fixed MDIO Bus: probed
    [    0.977193] tun: Universal TUN/TAP device driver, 1.6
    [    0.982214] CAN device driver interface
    [    0.987833] macb ff0e0000.ethernet: Not enabling partial store and forward
    [    0.994953] libphy: MACB_mii_bus: probed
    [    1.068743] macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 26 (00:1b:c5:03:c1:33)
    [    1.078366] Marvell 88E1510 ff0e0000.ethernet-ffffffff:01: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=ff0e0000.ethernet-ffffffff:01, irq=POLL)
    [    1.093141] usbcore: registered new interface driver asix
    [    1.098400] usbcore: registered new interface driver ax88179_178a
    [    1.104426] usbcore: registered new interface driver cdc_ether
    [    1.110221] usbcore: registered new interface driver net1080
    [    1.115843] usbcore: registered new interface driver cdc_subset
    [    1.121726] usbcore: registered new interface driver zaurus
    [    1.127276] usbcore: registered new interface driver cdc_ncm
    [    1.133175] xilinx-axipmon ffa00000.perf-monitor: Probed Xilinx APM
    [    1.140112] usbcore: registered new interface driver uas
    [    1.145265] usbcore: registered new interface driver usb-storage
    [    1.151877] rtc_zynqmp ffa60000.rtc: rtc core: registered ffa60000.rtc as rtc0
    [    1.158977] i2c /dev entries driver
    [    1.164038] rtc-pcf2127-i2c 0-0051: oscillator stop detected, date/time is not reliable
    [    1.171924] rtc-pcf2127-i2c 0-0051: rtc core: registered rtc-pcf2127-i2c as rtc1
    [    1.179222] cdns-i2c ff020000.i2c: 400 kHz mmio ff020000 irq 29
    [    1.185736] at24 1-0050: 256 byte 24c02 EEPROM, writable, 1 bytes/write
    [    1.192178] cdns-i2c ff030000.i2c: 400 kHz mmio ff030000 irq 30
    [    1.198278] Driver for 1-wire Dallas network protocol.
    [    1.233771] w1_master_driver w1_bus_master1: Attaching one wire slave 28.000000b54d1f crc 74
    [    1.243399] EDAC MC0: Giving out device to module 1 controller synps_ddr_controller: DEV synps_edac (INTERRUPT)
    [    1.253634] EDAC DEVICE0: Giving out device to module zynqmp-ocm-edac controller zynqmp_ocm: DEV ff960000.memory-controller (INTERRUPT)
    [    1.266757] sdhci: Secure Digital Host Controller Interface driver
    [    1.272744] sdhci: Copyright(c) Pierre Ossman
    [    1.277067] sdhci-pltfm: SDHCI platform and OF driver helper
    [    1.328523] mmc0: SDHCI controller on ff160000.sdhci [ff160000.sdhci] using ADMA 64-bit
    [    1.384517] mmc1: SDHCI controller on ff170000.sdhci [ff170000.sdhci] using ADMA 64-bit
    [    1.398583] ledtrig-cpu: registered to indicate activity on CPUs
    [    1.404566] usbcore: registered new interface driver usbhid
    [    1.409942] usbhid: USB HID core driver
    [    1.417634] ad9361 spi2.0: ad9361_probe : enter (ad9361)
    [    1.423979] mmc0: new HS200 MMC card at address 0001
    [    1.425543] ad9361 spi2.0: ad9361_reset: by GPIO
    [    1.427615] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [    1.427767] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [    1.427901] ad9361 spi2.0: ad9361_clk_mux_get_parent: index 0
    [    1.428004] ad9361 spi2.0: ad9361_clk_mux_get_parent: index 0
    [    1.428117] ad9361 spi2.0: ad9361_setup
    [    1.428120] ad9361 spi2.0: ad9361_auxdac_setup
    [    1.428124] ad9361 spi2.0: ad9361_auxdac_set DAC1 = 0 mV
    [    1.428190] ad9361 spi2.0: ad9361_auxdac_set DAC2 = 0 mV
    [    1.428372] ad9361 spi2.0: ad9361_gpo_setup
    [    1.428589] ad9361 spi2.0: ad9361_set_dcxo_tune : coarse 8 fine 5920
    [    1.428769] ad9361 spi2.0: ad9361_set_trx_clock_chain
    [    1.428775] ad9361 spi2.0: ad9361_set_trx_clock_chain: 983040000 245760000 122880000 61440000 30720000 30720000
    [    1.428780] ad9361 spi2.0: ad9361_set_trx_clock_chain: 983040000 122880000 122880000 61440000 30720000 30720000
    [    1.429003] ad9361 spi2.0: ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz
    [    1.429007] mmcblk0: mmc0:0001 R1J57L 29.1 GiB 
    [    1.429542] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 983040000 Hz
    [    1.429605] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz
    [    1.429667] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.429729] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.429791] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 15360000 Hz Parent Rate 30720000 Hz
    [    1.429852] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 3840000 Hz Parent Rate 15360000 Hz
    [    1.429914] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.429976] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.430037] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 15360000 Hz Parent Rate 30720000 Hz
    [    1.430098] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 3840000 Hz Parent Rate 15360000 Hz
    [    1.430347] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 983040000 Hz
    [    1.430409] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 245760000 Hz Parent Rate 245760000 Hz
    [    1.430470] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 245760000 Hz
    [    1.430532] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.430593] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.430655] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 30720000 Hz
    [    1.430716] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 245760000 Hz
    [    1.430777] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.430839] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.430900] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 30720000 Hz
    [    1.431045] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 245760000 Hz
    [    1.431106] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.431168] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.431229] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 15360000 Hz Parent Rate 30720000 Hz
    [    1.431290] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 15360000 Hz Parent Rate 15360000 Hz
    [    1.431415] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 122880000 Hz Parent Rate 122880000 Hz
    [    1.431476] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 61440000 Hz Parent Rate 122880000 Hz
    [    1.431537] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 61440000 Hz
    [    1.431598] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 30720000 Hz Parent Rate 30720000 Hz
    [    1.432035] ad9361 spi2.0: ad9361_rssi_setup
    [    1.432423] ad9361 spi2.0: ad9361_auxadc_setup
    [    1.432595] ad9361 spi2.0: ad9361_rf_port_setup : INPUT_SELECT 0x3
    [    1.432614] ad9361 spi2.0: ad9361_pp_port_setup
    [    1.432967] ad9361 spi2.0: ad9361_auxadc_setup
    [    1.433058] ad9361 spi2.0: ad9361_ctrl_outs_setup
    [    1.433093] ad9361 spi2.0: ad9361_set_ref_clk_cycles : ref_clk_hz 40000000
    [    1.433214] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.433267] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 40000000 Hz
    [    1.433388] ad9361 spi2.0: ad9361_rfpll_set_rate: RX Rate 0 Hz Parent Rate 80000000 Hz
    [    1.433394] ad9361 spi2.0: ad9361_fastlock_prepare: RX Profile 0: Un-Prepare
    [    1.433398] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.433446] mmcblk0boot0: mmc0:0001 R1J57L partition 1 8.00 MiB
    [    1.433453] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.433507] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 40000000 Hz
    [    1.433568] ad9361 spi2.0: ad9361_rfpll_set_rate: TX Rate 0 Hz Parent Rate 80000000 Hz
    [    1.433572] ad9361 spi2.0: ad9361_fastlock_prepare: TX Profile 0: Un-Prepare
    [    1.433576] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.433630] ad9361 spi2.0: ad9361_txrx_synth_cp_calib : ref_clk_hz 80000000 : is_tx 0
    [    1.434159] ad9361 spi2.0: ad9361_txrx_synth_cp_calib : ref_clk_hz 80000000 : is_tx 1
    [    1.434652] ad9361 spi2.0: ad9361_rfpll_determine_rate: Rate 1200000000 Hz
    [    1.434656] ad9361 spi2.0: ad9361_rfpll_determine_rate: Rate 1200000000 Hz
    [    1.434663] ad9361 spi2.0: ad9361_rfpll_set_rate: RX Rate 1200000000 Hz Parent Rate 80000000 Hz
    [    1.434667] ad9361 spi2.0: ad9361_fastlock_prepare: RX Profile 0: Un-Prepare
    [    1.434672] ad9361 spi2.0: ad9361_rfpll_vco_init : vco_freq 9600000000 : ref_clk 80000000 : range 2
    [    1.434677] ad9361 spi2.0: ad9361_rfpll_vco_init : freq 9445 MHz : index 12
    [    1.435127] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.435181] ad9361 spi2.0: ad9361_rx_rfpll_rate_change: rate 2400000000 Hz
    [    1.435185] ad9361 spi2.0: ad9361_load_gt: frequency 2400000000
    [    1.435190] ad9361 spi2.0: ad9361_load_gt: frequency 2400000000 (band 1)
    [    1.439342] mmcblk0boot1: mmc0:0001 R1J57L partition 2 8.00 MiB
    [    1.443247] ad9361 spi2.0: ad9361_rfpll_determine_rate: Rate 1225000000 Hz
    [    1.443251] ad9361 spi2.0: ad9361_rfpll_determine_rate: Rate 1225000000 Hz
    [    1.443257] ad9361 spi2.0: ad9361_rfpll_set_rate: TX Rate 1225000000 Hz Parent Rate 80000000 Hz
    [    1.443260] ad9361 spi2.0: ad9361_fastlock_prepare: TX Profile 0: Un-Prepare
    [    1.443264] ad9361 spi2.0: ad9361_rfpll_vco_init : vco_freq 9800000000 : ref_clk 80000000 : range 2
    [    1.443267] ad9361 spi2.0: ad9361_rfpll_vco_init : freq 9631 MHz : index 11
    [    1.443716] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 80000000 Hz
    [    1.443770] ad9361 spi2.0: ad9361_tx_rfpll_rate_change: rate 2450000000 Hz
    [    1.443775] ad9361 spi2.0: ad9361_load_mixer_gm_subtable
    [    1.445204] mmcblk0rpmb: mmc0:0001 R1J57L partition 3 4.00 MiB
    [    1.445476] ad9361 spi2.0: ad9361_gc_setup
    [    1.447276] ad9361 spi2.0: ad9361_rx_bb_analog_filter_calib : rx_bb_bw 9000000 bbpll_freq 983040000
    [    1.447432] ad9361 spi2.0: ad9361_run_calibration: CAL Mask 0x80
    [    1.447488] ad9361 spi2.0: ad9361_tx_bb_analog_filter_calib : tx_bb_bw 9000000 bbpll_freq 983040000
    [    1.447571] ad9361 spi2.0: ad9361_run_calibration: CAL Mask 0x40
    [    1.447674] ad9361 spi2.0: ad9361_rx_tia_calib : bb_bw_Hz 9000000
    [    1.447752] ad9361 spi2.0: ad9361_tx_bb_second_filter_calib : tx_bb_bw 9000000
    [    1.448070] ad9361 spi2.0: ad9361_rx_adc_setup : BBBW 8606895 : ADCfreq 245760000
    [    1.448075] ad9361 spi2.0: c3_msb 0x0 : c3_lsb 0x36 : r2346 0x1 : 
    [    1.448081] ad9361 spi2.0: invrc_tconst_1e6 942136, sqrt_inv_rc_tconst_1e3 970
    [    1.448084] ad9361 spi2.0: scaled_adc_clk_1e6 384000, inv_scaled_adc_clk_1e3 2604
    [    1.448088] ad9361 spi2.0: tmp_1e3 1000, sqrt_term_1e3 619, min_sqrt_term_1e3 1000
    [    1.448689] ad9361 spi2.0: ad9361_bb_dc_offset_calib
    [    1.448752] ad9361 spi2.0: ad9361_run_calibration: CAL Mask 0x1
    [    1.452839]  mmcblk0: p1
    [    1.462276] ad9361 spi2.0: ad9361_rf_dc_offset_calib : rx_freq 2400000000
    [    1.462383] ad9361 spi2.0: ad9361_run_calibration: CAL Mask 0x2
    [    1.502626] mmc1: new HS200 MMC card at address 0001
    [    1.507600] mmcblk1: mmc1:0001 R1J57L 29.1 GiB 
    [    1.512039] mmcblk1boot0: mmc1:0001 R1J57L partition 1 8.00 MiB
    [    1.517914] mmcblk1boot1: mmc1:0001 R1J57L partition 2 8.00 MiB
    [    1.523789] mmcblk1rpmb: mmc1:0001 R1J57L partition 3 4.00 MiB
    [    1.530270]  mmcblk1: p1
    [    1.633112] ad9361 spi2.0: ad9361_tx_quad_calib : bw_tx 9000000 clkrf 30720000 clktf 30720000
    [    1.633117] ad9361 spi2.0: Tx NCO frequency: 1920000 (BW/4: 2250000) txnco_word 1
    [    1.633360] ad9361 spi2.0: ad9361_run_calibration: CAL Mask 0x10
    [    1.639548] ad9361 spi2.0: LO leakage: 1 Quadrature Calibration: 1 : rx_phase 26
    [    1.639554] ad9361 spi2.0: ad9361_tracking_control : bbdc_track=1, rfdc_track=1, rxquad_track=1
    [    1.639662] ad9361 spi2.0: ad9361_pp_port_setup
    [    1.639772] ad9361 spi2.0: ad9361_set_tx_atten : attenuation 10000 mdB tx1=1 tx2=1
    [    1.639883] ad9361 spi2.0: ad9361_rssi_setup
    [    1.640093] ad9361 spi2.0: ad9361_txmon_setup
    [    1.640268] ad9361 spi2.0: Device is in 5 state, moving to a
    [    1.641451] ad9361 spi2.0: ad9361_probe : AD936x Rev 2 successfully initialized
    [    1.665788] cf_axi_dds 99024000.cf-ad9361-dds-core-lpc: Analog Devices CF_AXI_DDS_DDS MASTER (9.00.b) at 0x99024000 mapped to 0xffffff8008ff5000, probed DDS AD9361
    [    1.680698] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
    [    1.687215] pktgen: Packet Generator for packet performance testing. Version: 2.75
    [    1.694784] Netfilter messages via NETLINK v0.30.
    [    1.699437] ip_tables: (C) 2000-2006 Netfilter Core Team
    [    1.704707] Initializing XFRM netlink socket
    [    1.708888] NET: Registered protocol family 10
    [    1.713731] Segment Routing with IPv6
    [    1.717259] ip6_tables: (C) 2000-2006 Netfilter Core Team
    [    1.722689] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    [    1.728827] NET: Registered protocol family 17
    [    1.733094] NET: Registered protocol family 15
    [    1.737509] bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
    [    1.750384] Ebtables v2.0 registered
    [    1.754020] can: controller area network core (rev 20170425 abi 9)
    [    1.760106] NET: Registered protocol family 29
    [    1.764511] can: raw protocol (rev 20170425)
    [    1.768721] can: broadcast manager protocol (rev 20170425 t)
    [    1.774347] can: netlink gateway (rev 20170425) max_hops=1
    [    1.779935] 9pnet: Installing 9P2000 support
    [    1.784050] Key type dns_resolver registered
    [    1.789030] registered taskstats version 1
    [    1.800840] ff000000.serial: ttyPS0 at MMIO 0xff000000 (irq = 38, base_baud = 6249999) is a xuartps
    [    1.809786] console [ttyPS0] enabled
    [    1.816748] bootconsole [cdns0] disabled
    [    1.825405] ff010000.serial: ttyPS1 at MMIO 0xff010000 (irq = 39, base_baud = 6249999) is a xuartps
    [    1.836855] xilinx-psgtr fd400000.zynqmp_phy: Lane:2 type:0 protocol:3 pll_locked:yes
    [    1.846834] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [    1.852251] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
    [    1.860098] xhci-hcd xhci-hcd.0.auto: hcc params 0x0238f625 hci version 0x100 quirks 0x22010010
    [    1.868743] xhci-hcd xhci-hcd.0.auto: irq 56, io mem 0xfe200000
    [    1.874739] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
    [    1.881446] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [    1.888646] usb usb1: Product: xHCI Host Controller
    [    1.893506] usb usb1: Manufacturer: Linux 4.14.0 xhci-hcd
    [    1.898887] usb usb1: SerialNumber: xhci-hcd.0.auto
    [    1.904068] hub 1-0:1.0: USB hub found
    [    1.907755] hub 1-0:1.0: 1 port detected
    [    1.911826] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
    [    1.917238] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
    [    1.924929] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
    [    1.933011] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
    [    1.939712] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
    [    1.946915] usb usb2: Product: xHCI Host Controller
    [    1.951775] usb usb2: Manufacturer: Linux 4.14.0 xhci-hcd
    [    1.957156] usb usb2: SerialNumber: xhci-hcd.0.auto
    [    1.962259] hub 2-0:1.0: USB hub found
    [    1.965940] hub 2-0:1.0: 1 port detected
    [    1.992022] ad9361 spi2.0: ad9361_set_tx_atten : attenuation 89750 mdB tx1=1 tx2=1
    [    1.992195] ad9361 spi2.0: ad9361_bist_loopback: mode 0
    [    1.992249] ad9361 spi2.0: ad9361_bist_prbs: mode 2
    [    1.992277] ad9361 spi2.0: ad9361_calculate_rf_clock_chain: requested rate 25000000 TXFIR int 1 RXFIR dec 1 mode Nominal
    [    1.992283] ad9361 spi2.0: ad9361_set_trx_clock_chain
    [    1.992288] ad9361 spi2.0: ad9361_set_trx_clock_chain: 800000000 200000000 100000000 50000000 25000000 25000000
    [    1.992293] ad9361 spi2.0: ad9361_set_trx_clock_chain: 800000000 200000000 100000000 50000000 25000000 25000000
    [    1.992587] ad9361 spi2.0: ad9361_bbpll_set_rate: Rate 800000000 Hz Parent Rate 40000000 Hz
    [    1.993201] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 200000000 Hz Parent Rate 800000000 Hz
    [    1.993278] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 100000000 Hz Parent Rate 200000000 Hz
    [    1.993353] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 100000000 Hz Parent Rate 100000000 Hz
    [    1.993429] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 50000000 Hz Parent Rate 100000000 Hz
    [    1.993506] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 50000000 Hz
    [    1.993581] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 25000000 Hz
    [    2.003665] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 100000000 Hz Parent Rate 200000000 Hz
    [    2.003736] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 50000000 Hz Parent Rate 100000000 Hz
    [    2.003805] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 50000000 Hz
    [    2.003874] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 25000000 Hz
    [    2.004035] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 200000000 Hz Parent Rate 200000000 Hz
    [    2.004104] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 200000000 Hz Parent Rate 200000000 Hz
    [    2.004172] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 100000000 Hz Parent Rate 200000000 Hz
    [    2.004240] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 50000000 Hz Parent Rate 100000000 Hz
    [    2.004308] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 50000000 Hz Parent Rate 50000000 Hz
    [    2.014498] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 100000000 Hz Parent Rate 200000000 Hz
    [    2.014574] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 50000000 Hz Parent Rate 100000000 Hz
    [    2.014649] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 50000000 Hz
    [    2.014723] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 25000000 Hz Parent Rate 25000000 Hz
    [    2.025273] ad9361 spi2.0: ad9361_rssi_setup
    [    2.025754] ad9361 spi2.0: ad9361_auxadc_setup
    [    2.025897] ad9361 spi2.0: Device is in f state, forcing to 5
    [    2.026011] ad9361 spi2.0: Device is in f state, forcing to a
    [    2.090491] ad9361 spi2.0: Device is in 0 state, forcing to 5
    [    2.090603] ad9361 spi2.0: Device is in 0 state, forcing to a
    [    2.155233] ad9361 spi2.0: ad9361_calculate_rf_clock_chain: requested rate 40000000 TXFIR int 1 RXFIR dec 1 mode Nominal
    [    2.155237] ad9361 spi2.0: ad9361_set_trx_clock_chain
    [    2.155242] ad9361 spi2.0: ad9361_set_trx_clock_chain: 1280000000 320000000 160000000 80000000 40000000 40000000
    [    2.155247] ad9361 spi2.0: ad9361_set_trx_clock_chain: 1280000000 320000000 160000000 80000000 40000000 40000000
    [    2.155509] ad9361 spi2.0: ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
    [    2.162024] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 10521254882 Hz
    [    2.162056] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 82197303 Hz
    [    2.162132] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 41098651 Hz
    [    2.162164] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 10274662 Hz
    [    2.162195] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 5137331 Hz
    [    2.162226] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 2568665 Hz
    [    2.162258] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 82197303 Hz
    [    2.162333] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 20549325 Hz
    [    2.162364] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 10274662 Hz
    [    2.162395] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 40000000 Hz Parent Rate 5137331 Hz
    [    2.162655] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 318825905 Hz Parent Rate 10521254882 Hz
    [    2.162731] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 159412952 Hz Parent Rate 82197303 Hz
    [    2.162762] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 39853238 Hz Parent Rate 41098651 Hz
    [    2.162837] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 19926619 Hz Parent Rate 10274662 Hz
    [    2.162869] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 9963309 Hz Parent Rate 5137331 Hz
    [    2.162900] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 2490827 Hz Parent Rate 2568665 Hz
    [    2.162974] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 79706476 Hz Parent Rate 82197303 Hz
    [    2.163050] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 39853238 Hz Parent Rate 20549325 Hz
    [    2.163081] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 19926619 Hz Parent Rate 10274662 Hz
    [    2.163112] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 4981654 Hz Parent Rate 5137331 Hz
    [    2.163188] ad9361 spi2.0: Failed to set BB ref clock rate (-22)
    [    2.169141] ad9361 spi2.0: Device is in 0 state, forcing to 5
    [    2.169253] ad9361 spi2.0: Device is in 0 state, forcing to a
    [    2.233697] ad9361 spi2.0: Device is in f state, forcing to 5
    [    2.233809] ad9361 spi2.0: Device is in f state, forcing to a
    [    2.253981] usb 1-1: new high-speed USB device number 2 using xhci-hcd
    [    2.304705] ad9361 spi2.0: ad9361_calculate_rf_clock_chain: requested rate 61440000 TXFIR int 1 RXFIR dec 1 mode Nominal
    [    2.304709] ad9361 spi2.0: ad9361_set_trx_clock_chain
    [    2.304714] ad9361 spi2.0: ad9361_set_trx_clock_chain: 983040000 491520000 245760000 122880000 61440000 61440000
    [    2.304719] ad9361 spi2.0: ad9361_set_trx_clock_chain: 983040000 245760000 122880000 61440000 61440000 61440000
    [    2.304982] ad9361 spi2.0: ad9361_bbpll_set_rate: Rate 983040000 Hz Parent Rate 40000000 Hz
    [    2.305290] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 7680000 Hz Parent Rate 10521254882 Hz
    [    2.305366] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 3840000 Hz Parent Rate 82197303 Hz
    [    2.305398] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 960000 Hz Parent Rate 41098651 Hz
    [    2.305429] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 480000 Hz Parent Rate 10274662 Hz
    [    2.305460] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 240000 Hz Parent Rate 5137331 Hz
    [    2.305491] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 60000 Hz Parent Rate 2568665 Hz
    [    2.305523] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 1920000 Hz Parent Rate 82197303 Hz
    [    2.305554] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 960000 Hz Parent Rate 20549325 Hz
    [    2.305586] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 480000 Hz Parent Rate 10274662 Hz
    [    2.305617] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 120000 Hz Parent Rate 5137331 Hz
    [    2.305877] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.305953] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.305984] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.306015] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.306046] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.306078] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.316117] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 10521254882 Hz
    [    2.316150] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 2630313720 Hz
    [    2.316182] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 1315156860 Hz
    [    2.316213] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 501012137 Hz Parent Rate 657578430 Hz
    [    2.316290] ad9361 spi2.0: Failed to set BB ref clock rate (-22)
    [    2.322235] ad9361 spi2.0: Device is in 0 state, forcing to 5
    [    2.322337] ad9361 spi2.0: Device is in 0 state, forcing to a
    [    2.386774] ad9361 spi2.0: Device is in 0 state, forcing to 5
    [    2.386878] ad9361 spi2.0: Device is in 0 state, forcing to a
    [    2.451381] SAMPL CLK: 657578430 tuning: RX
    [    2.455492]   0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
    [    2.459907] 0:# # # # # # # # # # # # # # # # 
    [    2.464333] 1:# # # # # # # # # # # # # # # # 
    [    2.468762] ad9361 spi2.0: ad9361_dig_tune_delay: Tuning RX FAILED!
    [    2.475012] ad9361 spi2.0: ad9361_bist_loopback: mode 0
    [    2.475106] usb 1-1: New USB device found, idVendor=13b1, idProduct=0041
    [    2.481725] usb 1-1: New USB device strings: Mfr=1, Product=2, SerialNumber=6
    [    2.488839] usb 1-1: Product: Linksys USB3GIGV1
    [    2.493352] usb 1-1: Manufacturer: Linksys
    [    2.497432] usb 1-1: SerialNumber: 000001000000
    [    2.502071] ad9361 spi2.0: Device is in f state, forcing to 5
    [    2.502306] ad9361 spi2.0: ad9361_set_tx_atten : attenuation 10000 mdB tx1=1 tx2=1
    [    2.502468] cf_axi_adc: probe of 99020000.cf-ad9361-lpc failed with error -5
    [    2.510574] ubi0: attaching mtd5
    [    2.518867] cdc_ether 1-1:2.0 eth1: register 'cdc_ether' at usb-xhci-hcd.0.auto-1, CDC Ethernet Device, 58:ef:68:b5:34:29
    [    2.730137] random: crng init done
    [    2.856209] ubi0: scanning is finished
    [    2.865312] ubi0: attached mtd5 (name "qspi0-nom-rootfs", size 53 MiB)
    [    2.871755] ubi0: PEB size: 65536 bytes (64 KiB), LEB size: 65408 bytes
    [    2.878348] ubi0: min./max. I/O unit sizes: 1/256, sub-page size 1
    [    2.884511] ubi0: VID header offset: 64 (aligned 64), data offset: 128
    [    2.891020] ubi0: good PEBs: 862, bad PEBs: 0, corrupted PEBs: 0
    [    2.897010] ubi0: user volume: 1, internal volumes: 1, max. volumes count: 128
    [    2.904215] ubi0: max/mean erase counter: 16/10, WL threshold: 4096, image sequence number: 1108712413
    [    2.913502] ubi0: available PEBs: 0, total reserved PEBs: 862, PEBs reserved for bad PEB handling: 0
    [    2.922681] ubi0: background thread "ubi_bgt0d" started, PID 1754
    [    2.928697] rtc_zynqmp ffa60000.rtc: setting system clock to 2103-10-23 18:12:02 UTC (4222606322)
    [    2.937688] clk: Not disabling unused clocks
    [    2.943366] UBIFS (ubi0:0): background thread "ubifs_bgt0_0" started, PID 1757
    [    3.107083] UBIFS (ubi0:0): UBIFS: mounted UBI device 0, volume 0, name "q8-reva-rootfs"
    [    3.115093] UBIFS (ubi0:0): LEB size: 65408 bytes (63 KiB), min./max. I/O unit sizes: 8 bytes/256 bytes
    [    3.124464] UBIFS (ubi0:0): FS size: 54027008 bytes (51 MiB, 826 LEBs), journal size 8650240 bytes (8 MiB, 133 LEBs)
    [    3.134964] UBIFS (ubi0:0): reserved for root: 0 bytes (0 KiB)
    [    3.140783] UBIFS (ubi0:0): media format: w4/r0 (latest is w5/r0), UUID 3F4F8761-6F49-44C9-86BE-43C8F10D9AF8, big LPT model
    [    3.223485] VFS: Mounted root (ubifs filesystem) on device 0:15.
    [    3.230025] devtmpfs: mounted
    [    3.233070] Freeing unused kernel memory: 384K
    [    3.498252] systemd[1]: systemd 237 running in system mode. (-PAM -AUDIT -SELINUX -IMA -APPARMOR -SMACK +SYSVINIT -UTMP -LIBCRYPTSETUP -GCRYPT -GNUTLS +ACL +XZ -LZ4 -SECCOMP +BLKID -ELFUTILS +KMOD -IDN2 -IDN -PCRE2 default-hierarchy=hybrid)
    [    3.520560] systemd[1]: Detected architecture arm64.
    [    3.546124] systemd[1]: No hostname configured.
    [    3.550592] systemd[1]: Set hostname to <localhost>.
    [    3.723309] systemd[1]: File /lib/systemd/system/systemd-journald.service:35 configures an IP firewall (IPAddressDeny=any), but the local system does not support BPF/cgroup based firewalling.
    [    3.740275] systemd[1]: Proceeding WITHOUT firewalling in effect! (This warning is only shown for the first loaded unit using IP firewalling.)
    [    3.857558] systemd[1]: Reached target Swap.
    [    3.872638] systemd[1]: Reached target Paths.
    [    3.889777] systemd[1]: Created slice User and Session Slice.
    [    3.904580] systemd[1]: Reached target Remote File Systems.
    [    4.068072] UBIFS (ubi0:0): background thread "ubifs_bgt0_0" stops
    [    4.582283] systemd-journald[1778]: Received request to flush runtime journal from PID 1
    [    6.119852] cdc_ether 1-1:2.0 eth1: kevent 12 may have been dropped
    [    6.131908] pps pps0: new PPS source ptp0
    [    6.135928] macb ff0e0000.ethernet: gem-ptp-timer ptp clock registered.
    [    6.142597] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
    [    6.150865] cdc_ether 1-1:2.0 eth1: kevent 12 may have been dropped
    [  832.678426] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.678486] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.678561] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.678615] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.680202] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.680254] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.680325] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.680377] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.682092] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.682143] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.682213] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.682264] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.684113] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.684180] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 20000000 Hz
    [  832.684263] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    [  832.684320] ad9361 spi2.0: ad9361_rfpll_recalc_rate: Parent Rate 40000000 Hz
    

    here is our devicetree (the axi_ad9361 core was moved to the same base address as the reference project: 0x99020000):

    /dts-v1/;
    
    / {
    	#address-cells = < 0x02 >;
    	#size-cells = < 0x02 >;
    	compatible = "xiphos,q8", "xlnx,zynqmp";
    	model = "Xiphos Q8 RevA";
    
    	aliases {
    		ethernet0 = "/amba/ethernet@ff0e0000";
    		i2c0 = "/amba/i2c@ff020000";
    		i2c1 = "/amba/i2c@ff030000";
    		serial0 = "/amba/serial@ff000000";
    		serial1 = "/amba/serial@ff010000";
    		serial2 = "/amba_pl@0/serial@80030000";
    		serial3 = "/amba_pl@0/serial@80040000";
    		serial4 = "/amba_pl@0/serial@a0010000";
    		spi0 = "/amba/spi@ff0f0000";
    		spi1 = "/amba/spi@ff040000";
    		spi2 = "/amba/spi@ff050000";
    	};
    
    	amba: amba {
    		#address-cells = < 0x02 >;
    		#size-cells = < 0x02 >;
    		compatible = "simple-bus";
    		ranges;
    		u-boot,dm-pre-reloc;
    
    		sata: ahci@fd0c0000 {
    			#stream-id-cells = < 0x04 >;
    			clocks = < 0x03 0x16 >;
    			compatible = "ceva,ahci-1v84";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x85 0x04 >;
    			iommus = < 0x09 0x4c0 >, < 0x09 0x4c1 >, < 0x09 0x4c2 >, < 0x09 0x4c3 >;
    			power-domains = < 0x1d >;
    			reg = < 0x00 0xfd0c0000 0x00 0x2000 >;
    			status = "disabled";
    		};
    
    		xilinx_ams: ams@ffa50000 {
    			#address-cells = < 0x02 >;
    			#io-channel-cells = < 0x01 >;
    			#size-cells = < 0x02 >;
    			clocks = < 0x03 0x46 >;
    			compatible = "xlnx,zynqmp-ams";
    			interrupt-names = "ams-irq";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x38 0x04 >;
    			phandle = < 0x3e >;
    			ranges;
    			reg = < 0x00 0xffa50000 0x00 0x800 >;
    			reg-names = "ams-base";
    			status = "okay";
    
    			ams_pl: ams_pl@ffa50c00 {
    				compatible = "xlnx,zynqmp-ams-pl";
    				reg = < 0x00 0xffa50c00 0x00 0x400 >;
    				status = "okay";
    			};
    
    			ams_ps: ams_ps@ffa50800 {
    				compatible = "xlnx,zynqmp-ams-ps";
    				reg = < 0x00 0xffa50800 0x00 0x400 >;
    				status = "okay";
    			};
    		};
    
    		can0: can@ff060000 {
    			clock-names = "can_clk", "pclk";
    			clocks = < 0x03 0x3f >, < 0x03 0x1f >;
    			compatible = "xlnx,zynq-can-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x17 0x04 >;
    			power-domains = < 0x07 >;
    			reg = < 0x00 0xff060000 0x00 0x1000 >;
    			rx-fifo-depth = < 0x40 >;
    			status = "okay";
    			tx-fifo-depth = < 0x40 >;
    		};
    
    		can1: can@ff070000 {
    			clock-names = "can_clk", "pclk";
    			clocks = < 0x03 0x40 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynq-can-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x18 0x04 >;
    			power-domains = < 0x08 >;
    			reg = < 0x00 0xff070000 0x00 0x1000 >;
    			rx-fifo-depth = < 0x40 >;
    			status = "okay";
    			tx-fifo-depth = < 0x40 >;
    		};
    
    		cci: cci@fd6e0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x01 >;
    			compatible = "arm,cci-400";
    			ranges = < 0x00 0x00 0xfd6e0000 0x10000 >;
    			reg = < 0x00 0xfd6e0000 0x00 0x9000 >;
    
    			pmu@9000 {
    				compatible = "arm,cci-400-pmu,r1";
    				interrupt-parent = < 0x04 >;
    				interrupts = < 0x00 0x7b 0x04 >, < 0x00 0x7b 0x04 >, < 0x00 0x7b 0x04 >, < 0x00 0x7b 0x04 >, < 0x00 0x7b 0x04 >;
    				reg = < 0x9000 0x5000 >;
    			};
    		};
    
    		xlnx_dpdma: dma@fd4c0000 {
    			#dma-cells = < 0x01 >;
    			clock-names = "axi_clk";
    			clocks = < 0x03 0x14 >;
    			compatible = "xlnx,dpdma";
    			dma-channels = < 0x06 >;
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x7a 0x04 >;
    			phandle = < 0x31 >;
    			power-domains = < 0x2f >;
    			reg = < 0x00 0xfd4c0000 0x00 0x1000 >;
    			status = "disabled";
    
    			dma-audio0channel {
    				compatible = "xlnx,audio0";
    			};
    
    			dma-audio1channel {
    				compatible = "xlnx,audio1";
    			};
    
    			dma-graphicschannel {
    				compatible = "xlnx,graphics";
    			};
    
    			dma-video0channel {
    				compatible = "xlnx,video0";
    			};
    
    			dma-video1channel {
    				compatible = "xlnx,video1";
    			};
    
    			dma-video2channel {
    				compatible = "xlnx,video2";
    			};
    		};
    
    		fpd_dma_chan1: dma@fd500000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x7c 0x04 >;
    			iommus = < 0x09 0x14e8 >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd500000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan2: dma@fd510000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x7d 0x04 >;
    			iommus = < 0x09 0x14e9 >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd510000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan3: dma@fd520000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x7e 0x04 >;
    			iommus = < 0x09 0x14ea >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd520000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan4: dma@fd530000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x7f 0x04 >;
    			iommus = < 0x09 0x14eb >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd530000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan5: dma@fd540000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x80 0x04 >;
    			iommus = < 0x09 0x14ec >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd540000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan6: dma@fd550000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x81 0x04 >;
    			iommus = < 0x09 0x14ed >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd550000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan7: dma@fd560000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x82 0x04 >;
    			iommus = < 0x09 0x14ee >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd560000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		fpd_dma_chan8: dma@fd570000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x13 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x83 0x04 >;
    			iommus = < 0x09 0x14ef >;
    			power-domains = < 0x0a >;
    			reg = < 0x00 0xfd570000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x80 >;
    		};
    
    		lpd_dma_chan1: dma@ffa80000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x4d 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffa80000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan2: dma@ffa90000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x4e 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffa90000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan3: dma@ffaa0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x4f 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffaa0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan4: dma@ffab0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x50 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffab0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan5: dma@ffac0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x51 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffac0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan6: dma@ffad0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x52 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffad0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan7: dma@ffae0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x53 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffae0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		lpd_dma_chan8: dma@ffaf0000 {
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_main", "clk_apb";
    			clocks = < 0x03 0x44 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-dma-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x54 0x04 >;
    			power-domains = < 0x0c >;
    			reg = < 0x00 0xffaf0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,bus-width = < 0x40 >;
    		};
    
    		gem0: ethernet@ff0b0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
    			clocks = < 0x03 0x1f >, < 0x03 0x31 >, < 0x03 0x2d >, < 0x03 0x31 >, < 0x03 0x2c >;
    			compatible = "cdns,zynqmp-gem", "cdns,gem";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x39 0x04 >, < 0x00 0x39 0x04 >;
    			iommus = < 0x09 0x874 >;
    			power-domains = < 0x0e >;
    			reg = < 0x00 0xff0b0000 0x00 0x1000 >;
    			status = "disabled";
    		};
    
    		gem1: ethernet@ff0c0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
    			clocks = < 0x03 0x1f >, < 0x03 0x32 >, < 0x03 0x2e >, < 0x03 0x32 >, < 0x03 0x2c >;
    			compatible = "cdns,zynqmp-gem", "cdns,gem";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x3b 0x04 >, < 0x00 0x3b 0x04 >;
    			iommus = < 0x09 0x875 >;
    			power-domains = < 0x0f >;
    			reg = < 0x00 0xff0c0000 0x00 0x1000 >;
    			status = "disabled";
    		};
    
    		gem2: ethernet@ff0d0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
    			clocks = < 0x03 0x1f >, < 0x03 0x33 >, < 0x03 0x2f >, < 0x03 0x33 >, < 0x03 0x2c >;
    			compatible = "cdns,zynqmp-gem", "cdns,gem";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x3d 0x04 >, < 0x00 0x3d 0x04 >;
    			iommus = < 0x09 0x876 >;
    			power-domains = < 0x10 >;
    			reg = < 0x00 0xff0d0000 0x00 0x1000 >;
    			status = "disabled";
    		};
    
    		gem3: ethernet@ff0e0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
    			clocks = < 0x03 0x1f >, < 0x03 0x34 >, < 0x03 0x30 >, < 0x03 0x34 >, < 0x03 0x2c >;
    			compatible = "cdns,zynqmp-gem", "cdns,gem";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x3f 0x04 >, < 0x00 0x3f 0x04 >;
    			iommus = < 0x09 0x877 >;
    			phy-handle = < 0x12 >;
    			phy-mode = "rgmii-id";
    			power-domains = < 0x11 >;
    			reg = < 0x00 0xff0e0000 0x00 0x1000 >;
    			status = "okay";
    			xlnx,ptp-enet-clock = < 0x00 >;
    
    			phy1: phy@1 {
    				phandle = < 0x12 >;
    				reg = < 0x01 >;
    				reset-gpios = < 0x13 0x2c 0x01 >;
    			};
    		};
    
    		gpio: gpio@ff0a0000 {
    			#gpio-cells = < 0x02 >;
    			#interrupt-cells = < 0x02 >;
    			clocks = < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-gpio-1.0";
    			emio-gpio-width = < 0x20 >;
    			gpio-controller;
    			gpio-line-names = "MIO0", "MIO1", "MIO2", "MIO3", "MIO4", "MIO5", "MIO6", "MIO7", "MIO8", "MIO9", "MIO10", "MIO11", "ps_pa3_done", "MIO13", "MIO14", "MIO15", "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21", "MIO22", "ps_emmc0_rst_n", "MIO24", "MIO25", "MIO26", "MIO27", "MIO28", "MIO29", "MIO30", "MIO31", "MIO32", "MIO33", "MIO34", "MIO35", "MIO36", "MIO37", "ps_pa3_misc1", "MIO39", "MIO40", "MIO41", "MIO42", "ps_emmc1_rst_n", "ps_eth_rst_n", "ps_usb2_rst_n", "MIO46", "MIO47", "MIO48", "MIO49", "MIO50", "MIO51", "MIO26", "MIO27", "MIO28", "MIO29", "MIO30", "MIO31", "MIO32", "MIO33", "MIO34", "MIO35", "MIO36", "MIO37", "MIO38", "MIO39", "MIO40", "MIO41", "MIO42", "MIO43", "MIO44", "MIO45", "MIO46", "MIO47", "MIO48", "MIO49", "MIO50", "MIO51", "EMIO0", "EMIO1", "EMIO2", "EMIO3", "EMIO4", "EMIO5", "EMIO6", "EMIO7", "EMIO8", "EMIO9", "EMIO10", "EMIO11", "EMIO12", "EMIO13", "EMIO14", "EMIO15", "EMIO16", "EMIO17", "EMIO18", "EMIO19", "EMIO20", "EMIO21", "EMIO22", "EMIO23", "EMIO24", "EMIO25", "EMIO26", "EMIO27", "EMIO28", "EMIO29", "EMIO30", "EMIO31", "EMIO32", "EMIO33", "EMIO34", "EMIO35", "EMIO36", "EMIO37", "EMIO38", "EMIO39", "EMIO40", "EMIO41", "EMIO42", "EMIO43", "EMIO44", "EMIO45", "EMIO46", "EMIO47", "EMIO48", "EMIO49", "EMIO50", "EMIO51", "EMIO52", "EMIO53", "EMIO54", "EMIO55", "EMIO56", "EMIO57", "EMIO58", "EMIO59", "EMIO60", "EMIO61", "EMIO62", "EMIO63", "EMIO64", "EMIO65", "EMIO66", "EMIO67", "EMIO68", "EMIO69", "EMIO70", "EMIO71", "EMIO72", "EMIO73", "EMIO74", "EMIO75", "EMIO76", "EMIO77", "EMIO78", "EMIO79", "EMIO80", "EMIO81", "EMIO82", "EMIO83", "EMIO84", "EMIO85", "EMIO86", "EMIO87", "EMIO88", "EMIO89", "EMIO90", "EMIO91", "EMIO92", "EMIO93", "EMIO94", "EMIO95";
    			gpio-mask-high = < 0x00 >;
    			gpio-mask-low = < 0x5600 >;
    			interrupt-controller;
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x10 0x04 >;
    			phandle = < 0x13 >;
    			power-domains = < 0x14 >;
    			reg = < 0x00 0xff0a0000 0x00 0x1000 >;
    			status = "okay";
    		};
    
    		gpu: gpu@fd4b0000 {
    			clock-names = "gpu", "gpu_pp0", "gpu_pp1";
    			clocks = < 0x03 0x18 >, < 0x03 0x19 >, < 0x03 0x1a >;
    			compatible = "arm,mali-400", "arm,mali-utgard";
    			interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x84 0x04 >, < 0x00 0x84 0x04 >, < 0x00 0x84 0x04 >, < 0x00 0x84 0x04 >, < 0x00 0x84 0x04 >, < 0x00 0x84 0x04 >;
    			power-domains = < 0x0b >;
    			reg = < 0x00 0xfd4b0000 0x00 0x10000 >;
    			status = "okay";
    		};
    
    		i2c0: i2c@ff020000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			clock-frequency = < 0x61a80 >;
    			clocks = < 0x03 0x3d >;
    			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x11 0x04 >;
    			power-domains = < 0x15 >;
    			reg = < 0x00 0xff020000 0x00 0x1000 >;
    			status = "okay";
    
    			adc0: adc@48 {
    				#address-cells = < 0x01 >;
    				#io-channel-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    				compatible = "ti,ads1015";
    				phandle = < 0x3f >;
    				reg = < 0x48 >;
    
    				adc0_channel0@0 {
    					reg = < 0x04 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc0_channel1@1 {
    					reg = < 0x05 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc0_channel2@2 {
    					reg = < 0x06 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc0_channel3@3 {
    					reg = < 0x07 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    			};
    
    			adc1: adc@49 {
    				#address-cells = < 0x01 >;
    				#io-channel-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    				compatible = "ti,ads1015";
    				phandle = < 0x40 >;
    				reg = < 0x49 >;
    
    				adc1_channel0@0 {
    					reg = < 0x04 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc1_channel1@1 {
    					reg = < 0x05 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc1_channel2@2 {
    					reg = < 0x06 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc1_channel3@3 {
    					reg = < 0x07 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    			};
    
    			adc2: adc@4b {
    				#address-cells = < 0x01 >;
    				#io-channel-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    				compatible = "ti,ads1015";
    				phandle = < 0x41 >;
    				reg = < 0x4b >;
    
    				adc2_channel0@0 {
    					reg = < 0x04 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc2_channel1@1 {
    					reg = < 0x05 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc2_channel2@2 {
    					reg = < 0x06 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    
    				adc2_channel3@3 {
    					reg = < 0x07 >;
    					ti,datarate = < 0x04 >;
    					ti,gain = < 0x02 >;
    				};
    			};
    
    			w1_bridge: ds2482@18 {
    				compatible = "maxim,ds2482";
    				reg = < 0x18 >;
    			};
    
    			rtc0: rtc@51 {
    				compatible = "nxp,pca2129";
    				reg = < 0x51 >;
    			};
    		};
    
    		i2c1: i2c@ff030000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			clock-frequency = < 0x61a80 >;
    			clocks = < 0x03 0x3e >;
    			compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x12 0x04 >;
    			power-domains = < 0x16 >;
    			reg = < 0x00 0xff030000 0x00 0x1000 >;
    			status = "okay";
    
    			ad7291@2f {
    				compatible = "adi,ad7291";
    				reg = < 0x2f >;
    			};
    
    			eeprom@50 {
    				compatible = "at24,24c02";
    				reg = < 0x50 >;
    			};
    		};
    
    		mc: memory-controller@fd070000 {
    			compatible = "xlnx,zynqmp-ddrc-2.40a";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x70 0x04 >;
    			reg = < 0x00 0xfd070000 0x00 0x30000 >;
    		};
    
    		ocm: memory-controller@ff960000 {
    			compatible = "xlnx,zynqmp-ocmc-1.0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x0a 0x04 >;
    			reg = < 0x00 0xff960000 0x00 0x1000 >;
    		};
    
    		nand0: nand@ff100000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "clk_sys", "clk_flash";
    			clocks = < 0x03 0x3c >, < 0x03 0x1f >;
    			compatible = "arasan,nfc-v3p10";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x0e 0x04 >;
    			iommus = < 0x09 0x872 >;
    			power-domains = < 0x0d >;
    			reg = < 0x00 0xff100000 0x00 0x1000 >;
    			status = "disabled";
    		};
    
    		pcie: pcie@fd0e0000 {
    			#address-cells = < 0x03 >;
    			#interrupt-cells = < 0x01 >;
    			#size-cells = < 0x02 >;
    			bus-range = < 0x00 0xff >;
    			clocks = < 0x03 0x17 >;
    			compatible = "xlnx,nwl-pcie-2.11";
    			device_type = "pci";
    			interrupt-map = < 0x00 0x00 0x00 0x01 0x18 0x01 >, < 0x00 0x00 0x00 0x02 0x18 0x02 >, < 0x00 0x00 0x00 0x03 0x18 0x03 >, < 0x00 0x00 0x00 0x04 0x18 0x04 >;
    			interrupt-map-mask = < 0x00 0x00 0x00 0x07 >;
    			interrupt-names = "misc", "dummy", "intx", "msi1", "msi0";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x76 0x04 >, < 0x00 0x75 0x04 >, < 0x00 0x74 0x04 >, < 0x00 0x73 0x04 >, < 0x00 0x72 0x04 >;
    			msi-controller;
    			msi-parent = < 0x17 >;
    			phandle = < 0x17 >;
    			power-domains = < 0x19 >;
    			ranges = < 0x2000000 0x00 0xe0000000 0x00 0xe0000000 0x00 0x10000000 0x43000000 0x06 0x00 0x06 0x00 0x02 0x00 >;
    			reg = < 0x00 0xfd0e0000 0x00 0x1000 >, < 0x00 0xfd480000 0x00 0x1000 >, < 0x80 0x00 0x00 0x1000000 >;
    			reg-names = "breg", "pcireg", "cfg";
    			status = "disabled";
    
    			pcie_intc: legacy-interrupt-controller {
    				#address-cells = < 0x00 >;
    				#interrupt-cells = < 0x01 >;
    				interrupt-controller;
    				phandle = < 0x18 >;
    			};
    		};
    
    		perf_monitor_ocm: perf-monitor@ffa00000 {
    			clocks = < 0x03 0x1f >;
    			compatible = "xlnx,axi-perf-monitor";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x19 0x04 >;
    			reg = < 0x00 0xffa00000 0x00 0x10000 >;
    			xlnx,enable-32bit-filter-id = < 0x01 >;
    			xlnx,enable-advanced = < 0x01 >;
    			xlnx,enable-event-count = < 0x01 >;
    			xlnx,enable-event-log = < 0x00 >;
    			xlnx,enable-profile = < 0x00 >;
    			xlnx,enable-trace = < 0x00 >;
    			xlnx,fifo-axis-depth = < 0x20 >;
    			xlnx,fifo-axis-tdata-width = < 0x38 >;
    			xlnx,fifo-axis-tid-width = < 0x01 >;
    			xlnx,global-count-width = < 0x20 >;
    			xlnx,have-sampled-metric-cnt = < 0x01 >;
    			xlnx,metric-count-scale = < 0x01 >;
    			xlnx,metric-count-width = < 0x20 >;
    			xlnx,metrics-sample-count-width = < 0x20 >;
    			xlnx,num-monitor-slots = < 0x01 >;
    			xlnx,num-of-counters = < 0x03 >;
    		};
    
    		pinctrl0: pinctrl@ff180000 {
    			compatible = "xlnx,zynqmp-pinctrl";
    			reg = < 0x00 0xff180000 0x00 0x1000 >;
    			status = "okay";
    		};
    
    		rtc: rtc@ffa60000 {
    			calibration = < 0x8000 >;
    			compatible = "xlnx,zynqmp-rtc";
    			interrupt-names = "alarm", "sec";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x1a 0x04 >, < 0x00 0x1b 0x04 >;
    			reg = < 0x00 0xffa60000 0x00 0x100 >;
    			status = "okay";
    		};
    
    		sdhci0: sdhci@ff160000 {
    			#stream-id-cells = < 0x01 >;
    			clock-frequency = < 0xbebba30 >;
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = < 0x03 0x36 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x30 0x04 >;
    			iommus = < 0x09 0x870 >;
    			power-domains = < 0x1e >;
    			reg = < 0x00 0xff160000 0x00 0x1000 >;
    			status = "okay";
    			u-boot,dm-pre-reloc;
    			xlnx,device_id = < 0x00 >;
    			xlnx,mio_bank = < 0x00 >;
    		};
    
    		sdhci1: sdhci@ff170000 {
    			#stream-id-cells = < 0x01 >;
    			clock-frequency = < 0xbebba30 >;
    			clock-names = "clk_xin", "clk_ahb";
    			clocks = < 0x03 0x37 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x31 0x04 >;
    			iommus = < 0x09 0x871 >;
    			power-domains = < 0x1f >;
    			reg = < 0x00 0xff170000 0x00 0x1000 >;
    			status = "okay";
    			u-boot,dm-pre-reloc;
    			xlnx,device_id = < 0x01 >;
    			xlnx,mio_bank = < 0x01 >;
    		};
    
    		uart0: serial@ff000000 {
    			clock-names = "uart_clk", "pclk";
    			clocks = < 0x03 0x38 >, < 0x03 0x1f >;
    			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
    			device_type = "serial";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x15 0x04 >;
    			port-number = < 0x04 >;
    			power-domains = < 0x2a >;
    			reg = < 0x00 0xff000000 0x00 0x1000 >;
    			status = "okay";
    			u-boot,dm-pre-reloc;
    		};
    
    		uart1: serial@ff010000 {
    			clock-names = "uart_clk", "pclk";
    			clocks = < 0x03 0x39 >, < 0x03 0x1f >;
    			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
    			device_type = "serial";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x16 0x04 >;
    			port-number = < 0x05 >;
    			power-domains = < 0x2b >;
    			reg = < 0x00 0xff010000 0x00 0x1000 >;
    			status = "okay";
    			u-boot,dm-pre-reloc;
    		};
    
    		smmu: smmu@fd800000 {
    			#global-interrupts = < 0x01 >;
    			#iommu-cells = < 0x01 >;
    			compatible = "arm,mmu-500";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >, < 0x00 0x9b 0x04 >;
    			phandle = < 0x09 >;
    			reg = < 0x00 0xfd800000 0x00 0x20000 >;
    			status = "disabled";
    		};
    
    		spi0: spi@ff040000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			clock-names = "ref_clk", "pclk";
    			clocks = < 0x03 0x3a >, < 0x03 0x1f >;
    			compatible = "cdns,spi-r1p6";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x13 0x04 >;
    			is-decoded-cs = < 0x00 >;
    			num-cs = < 0x01 >;
    			power-domains = < 0x20 >;
    			reg = < 0x00 0xff040000 0x00 0x1000 >;
    			status = "okay";
    
    			pim_adc: pim_adc@0 {
    				#io-channel-cells = < 0x01 >;
    				compatible = "ti,ads7951";
    				phandle = < 0x42 >;
    				reg = < 0x00 >;
    				spi-max-frequency = < 0x989680 >;
    				vref-supply = < 0x21 >;
    			};
    		};
    
    		spi1: spi@ff050000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			clock-names = "ref_clk", "pclk";
    			clocks = < 0x03 0x3b >, < 0x03 0x1f >;
    			compatible = "cdns,spi-r1p6";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x14 0x04 >;
    			is-decoded-cs = < 0x00 >;
    			num-cs = < 0x01 >;
    			power-domains = < 0x22 >;
    			reg = < 0x00 0xff050000 0x00 0x1000 >;
    			status = "okay";
    
    			adc0_ad9361: ad9361-phy@0 {
    				#clock-cells = < 0x01 >;
    				adi,2rx-2tx-mode-enable;
    				adi,agc-adc-large-overload-exceed-counter = < 0x0a >;
    				adi,agc-adc-large-overload-inc-steps = < 0x02 >;
    				adi,agc-adc-small-overload-exceed-counter = < 0x0a >;
    				adi,agc-attack-delay-extra-margin-us = < 0x01 >;
    				adi,agc-gain-update-interval-us = < 0x3e8 >;
    				adi,agc-inner-thresh-high = < 0x0a >;
    				adi,agc-inner-thresh-high-dec-steps = < 0x01 >;
    				adi,agc-inner-thresh-low = < 0x0c >;
    				adi,agc-inner-thresh-low-inc-steps = < 0x01 >;
    				adi,agc-lmt-overload-large-exceed-counter = < 0x0a >;
    				adi,agc-lmt-overload-large-inc-steps = < 0x02 >;
    				adi,agc-lmt-overload-small-exceed-counter = < 0x0a >;
    				adi,agc-outer-thresh-high = < 0x05 >;
    				adi,agc-outer-thresh-high-dec-steps = < 0x02 >;
    				adi,agc-outer-thresh-low = < 0x12 >;
    				adi,agc-outer-thresh-low-inc-steps = < 0x02 >;
    				adi,aux-dac-manual-mode-enable;
    				adi,aux-dac1-default-value-mV = < 0x00 >;
    				adi,aux-dac1-rx-delay-us = < 0x00 >;
    				adi,aux-dac1-tx-delay-us = < 0x00 >;
    				adi,aux-dac2-default-value-mV = < 0x00 >;
    				adi,aux-dac2-rx-delay-us = < 0x00 >;
    				adi,aux-dac2-tx-delay-us = < 0x00 >;
    				adi,ctrl-outs-enable-mask = < 0xff >;
    				adi,ctrl-outs-index = < 0x00 >;
    				adi,dcxo-coarse-and-fine-tune = < 0x08 0x1720 >;
    				adi,digital-interface-tune-skip-mode = < 0x00 >;
    				adi,fagc-dec-pow-measurement-duration = < 0x40 >;
    				adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = < 0x08 >;
    				adi,fagc-final-overrange-count = < 0x03 >;
    				adi,fagc-gain-index-type-after-exit-rx-mode = < 0x00 >;
    				adi,fagc-lmt-final-settling-steps = < 0x01 >;
    				adi,fagc-lock-level = < 0x0a >;
    				adi,fagc-lock-level-gain-increase-upper-limit = < 0x05 >;
    				adi,fagc-lock-level-lmt-gain-increase-enable;
    				adi,fagc-lp-thresh-increment-steps = < 0x01 >;
    				adi,fagc-lp-thresh-increment-time = < 0x05 >;
    				adi,fagc-lpf-final-settling-steps = < 0x01 >;
    				adi,fagc-optimized-gain-offset = < 0x05 >;
    				adi,fagc-power-measurement-duration-in-state5 = < 0x40 >;
    				adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = < 0x0a >;
    				adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
    				adi,fagc-rst-gla-if-en-agc-pulled-high-mode = < 0x00 >;
    				adi,fagc-rst-gla-large-adc-overload-enable;
    				adi,fagc-rst-gla-large-lmt-overload-enable;
    				adi,fagc-rst-gla-stronger-sig-thresh-above-ll = < 0x0a >;
    				adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
    				adi,fagc-state-wait-time-ns = < 0x104 >;
    				adi,fagc-use-last-lock-level-for-set-gain-enable;
    				adi,frequency-division-duplex-mode-enable;
    				adi,gc-adc-large-overload-thresh = < 0x3a >;
    				adi,gc-adc-ovr-sample-size = < 0x04 >;
    				adi,gc-adc-small-overload-thresh = < 0x2f >;
    				adi,gc-dec-pow-measurement-duration = < 0x2000 >;
    				adi,gc-lmt-overload-high-thresh = < 0x320 >;
    				adi,gc-lmt-overload-low-thresh = < 0x2c0 >;
    				adi,gc-low-power-thresh = < 0x18 >;
    				adi,gc-rx1-mode = < 0x02 >;
    				adi,gc-rx2-mode = < 0x02 >;
    				adi,lvds-bias-mV = < 0x96 >;
    				adi,lvds-mode-enable;
    				adi,lvds-rx-onchip-termination-enable;
    				adi,mgc-dec-gain-step = < 0x02 >;
    				adi,mgc-inc-gain-step = < 0x02 >;
    				adi,mgc-split-table-ctrl-inp-gain-mode = < 0x00 >;
    				adi,pp-rx-swap-enable;
    				adi,pp-tx-swap-enable;
    				adi,rf-rx-bandwidth-hz = < 0x112a880 >;
    				adi,rf-tx-bandwidth-hz = < 0x112a880 >;
    				adi,rssi-delay = < 0x01 >;
    				adi,rssi-duration = < 0x3e8 >;
    				adi,rssi-restart-mode = < 0x03 >;
    				adi,rssi-wait = < 0x01 >;
    				adi,rx-data-delay = < 0x04 >;
    				adi,rx-frame-pulse-mode-enable;
    				adi,rx-path-clock-frequencies = < 0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000 >;
    				adi,rx-rf-port-input-select = < 0x00 >;
    				adi,rx-synthesizer-frequency-hz = /bits/ 64 < 0x8f0d1800 >;
    				adi,temp-sense-measurement-interval-ms = < 0x3e8 >;
    				adi,temp-sense-offset-signed = < 0xce >;
    				adi,temp-sense-periodic-measurement-enable;
    				adi,tx-attenuation-mdB = < 0x2710 >;
    				adi,tx-fb-clock-delay = < 0x07 >;
    				adi,tx-lo-powerdown-managed-enable;
    				adi,tx-path-clock-frequencies = < 0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000 >;
    				adi,tx-rf-port-input-select = < 0x00 >;
    				adi,tx-synthesizer-frequency-hz = /bits/ 64 < 0x92080880 >;
    				adi,xo-disable-use-ext-refclk-enable;
    				clock-names = "ad9361_ext_refclk";
    				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
    				clocks = < 0x23 >;
    				compatible = "adi,ad9361";
    				en_agc-gpios = < 0x24 0x01 0x00 0x00 >;
    				enable-gpios = < 0x25 0x00 0x00 0x00 >;
    				phandle = < 0x3b >;
    				reg = < 0x00 >;
    				reset-gpios = < 0x24 0x00 0x00 0x00 >;
    				spi-cpha;
    				spi-max-frequency = < 0x989680 >;
    				txnrx-gpios = < 0x25 0x01 0x00 0x00 >;
    			};
    		};
    
    		qspi: spi@ff0f0000 {
    			#address-cells = < 0x01 >;
    			#size-cells = < 0x00 >;
    			#stream-id-cells = < 0x01 >;
    			clock-names = "ref_clk", "pclk";
    			clocks = < 0x03 0x35 >, < 0x03 0x1f >;
    			compatible = "xlnx,zynqmp-qspi-1.0";
    			has-io-mode = < 0x01 >;
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x0f 0x04 >;
    			iommus = < 0x09 0x873 >;
    			is-dual = < 0x00 >;
    			is-stacked = < 0x01 >;
    			num-cs = < 0x01 >;
    			power-domains = < 0x1a >;
    			reg = < 0x00 0xff0f0000 0x00 0x1000 >, < 0x00 0xc0000000 0x00 0x8000000 >;
    			spi-rx-bus-width = < 0x04 >;
    			spi-tx-bus-width = < 0x04 >;
    			status = "okay";
    			u-boot,dm-pre-reloc;
    
    			flash: flash@0 {
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x01 >;
    				compatible = "micron,n25q00a", "jedec,spi-nor";
    				reg = < 0x00 >;
    				spi-max-frequency = < 0x2faf080 >;
    				spi-rx-bus-width = < 0x04 >;
    				spi-tx-bus-width = < 0x01 >;
    				use-advanced-sector-protection;
    
    				qspi0-gold-fw@6 {
    					reg = < 0x4000000 0xa00000 >;
    				};
    
    				qspi0-gold-rootfs@8 {
    					reg = < 0x4a20000 0x35e0000 >;
    				};
    
    				qspi0-gold-xscinfo@7 {
    					reg = < 0x4a00000 0x20000 >;
    				};
    
    				qspi0-gold@5 {
    					reg = < 0x4000000 0x4000000 >;
    				};
    
    				qspi0-nom-fw@2 {
    					reg = < 0x00 0xa00000 >;
    				};
    
    				qspi0-nom-rootfs@4 {
    					reg = < 0xa20000 0x35e0000 >;
    				};
    
    				qspi0-nom-xscinfo@3 {
    					reg = < 0xa00000 0x20000 >;
    				};
    
    				qspi0-nom@1 {
    					reg = < 0x00 0x4000000 >;
    				};
    
    				qspi0@0 {
    					reg = < 0x00 0x8000000 >;
    				};
    
    				qspi1-gold-fw@15 {
    					reg = < 0xc000000 0xa00000 >;
    				};
    
    				qspi1-gold-rootfs@17 {
    					reg = < 0xca20000 0x35e0000 >;
    				};
    
    				qspi1-gold-xscinfo@16 {
    					reg = < 0xca00000 0x20000 >;
    				};
    
    				qspi1-gold@14 {
    					reg = < 0xc000000 0x4000000 >;
    				};
    
    				qspi1-nom-fw@11 {
    					reg = < 0x8000000 0xa00000 >;
    				};
    
    				qspi1-nom-rootfs@13 {
    					reg = < 0x8a20000 0x35e0000 >;
    				};
    
    				qspi1-nom-xscinfo@12 {
    					reg = < 0x8a00000 0x20000 >;
    				};
    
    				qspi1-nom@10 {
    					reg = < 0x8000000 0x4000000 >;
    				};
    
    				qspi1@9 {
    					reg = < 0x8000000 0x8000000 >;
    				};
    			};
    		};
    
    		ttc0: timer@ff110000 {
    			clocks = < 0x03 0x1f >;
    			compatible = "cdns,ttc";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x24 0x04 >, < 0x00 0x25 0x04 >, < 0x00 0x26 0x04 >;
    			power-domains = < 0x26 >;
    			reg = < 0x00 0xff110000 0x00 0x1000 >;
    			status = "disabled";
    			timer-width = < 0x20 >;
    		};
    
    		ttc1: timer@ff120000 {
    			clocks = < 0x03 0x1f >;
    			compatible = "cdns,ttc";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x27 0x04 >, < 0x00 0x28 0x04 >, < 0x00 0x29 0x04 >;
    			power-domains = < 0x27 >;
    			reg = < 0x00 0xff120000 0x00 0x1000 >;
    			status = "disabled";
    			timer-width = < 0x20 >;
    		};
    
    		ttc2: timer@ff130000 {
    			clocks = < 0x03 0x1f >;
    			compatible = "cdns,ttc";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x2a 0x04 >, < 0x00 0x2b 0x04 >, < 0x00 0x2c 0x04 >;
    			power-domains = < 0x28 >;
    			reg = < 0x00 0xff130000 0x00 0x1000 >;
    			status = "disabled";
    			timer-width = < 0x20 >;
    		};
    
    		ttc3: timer@ff140000 {
    			clocks = < 0x03 0x1f >;
    			compatible = "cdns,ttc";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x2d 0x04 >, < 0x00 0x2e 0x04 >, < 0x00 0x2f 0x04 >;
    			power-domains = < 0x29 >;
    			reg = < 0x00 0xff140000 0x00 0x1000 >;
    			status = "disabled";
    			timer-width = < 0x20 >;
    		};
    
    		usb0: usb0@ff9d0000 {
    			#address-cells = < 0x02 >;
    			#size-cells = < 0x02 >;
    			clock-names = "bus_clk", "ref_clk";
    			clocks = < 0x03 0x20 >, < 0x03 0x22 >;
    			compatible = "xlnx,zynqmp-dwc3";
    			nvmem-cell-names = "soc_revision";
    			nvmem-cells = < 0x1b >;
    			power-domains = < 0x2c >;
    			ranges;
    			reg = < 0x00 0xff9d0000 0x00 0x100 >;
    			status = "okay";
    			xlnx,usb-reset = < 0x2faf080 >;
    
    			dwc3_0: dwc3@fe200000 {
    				#stream-id-cells = < 0x01 >;
    				compatible = "snps,dwc3";
    				dr_mode = "host";
    				interrupt-parent = < 0x04 >;
    				interrupts = < 0x00 0x41 0x04 >, < 0x00 0x45 0x04 >, < 0x00 0x4b 0x04 >;
    				iommus = < 0x09 0x860 >;
    				phy-names = "usb3-phy";
    				phys = < 0x2d 0x04 0x00 0x02 0x5f5e100 >;
    				reg = < 0x00 0xfe200000 0x00 0x40000 >;
    				snps,enable_guctl1_ipd_quirk;
    				snps,enable_guctl1_resume_quirk;
    				snps,quirk-frame-length-adjustment = < 0x20 >;
    				snps,refclk_fladj;
    				snps,xhci-stream-quirk;
    				status = "okay";
    			};
    		};
    
    		usb1: usb1@ff9e0000 {
    			#address-cells = < 0x02 >;
    			#size-cells = < 0x02 >;
    			clock-names = "bus_clk", "ref_clk";
    			clocks = < 0x03 0x21 >, < 0x03 0x22 >;
    			compatible = "xlnx,zynqmp-dwc3";
    			nvmem-cell-names = "soc_revision";
    			nvmem-cells = < 0x1b >;
    			power-domains = < 0x2e >;
    			ranges;
    			reg = < 0x00 0xff9e0000 0x00 0x100 >;
    			status = "disabled";
    
    			dwc3_1: dwc3@fe300000 {
    				#stream-id-cells = < 0x01 >;
    				compatible = "snps,dwc3";
    				interrupt-parent = < 0x04 >;
    				interrupts = < 0x00 0x46 0x04 >, < 0x00 0x4a 0x04 >, < 0x00 0x4c 0x04 >;
    				iommus = < 0x09 0x861 >;
    				reg = < 0x00 0xfe300000 0x00 0x40000 >;
    				snps,enable_guctl1_ipd_quirk;
    				snps,enable_guctl1_resume_quirk;
    				snps,quirk-frame-length-adjustment = < 0x20 >;
    				snps,refclk_fladj;
    				snps,xhci-stream-quirk;
    				status = "disabled";
    			};
    		};
    
    		watchdog0: watchdog@fd4d0000 {
    			clocks = < 0x03 0x4b >;
    			compatible = "cdns,wdt-r1p2";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x71 0x01 >;
    			reg = < 0x00 0xfd4d0000 0x00 0x1000 >;
    			status = "disabled";
    			timeout-sec = < 0x0a >;
    		};
    
    		zynqmp_dpsub: zynqmp-display@fd4a0000 {
    			clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
    			clocks = < 0x30 >, < 0x03 0x11 >, < 0x03 0x10 >;
    			compatible = "xlnx,zynqmp-dpsub-1.7";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x77 0x04 >;
    			power-domains = < 0x2f >;
    			reg = < 0x00 0xfd4a0000 0x00 0x1000 >, < 0x00 0xfd4aa000 0x00 0x1000 >, < 0x00 0xfd4ab000 0x00 0x1000 >, < 0x00 0xfd4ac000 0x00 0x1000 >;
    			reg-names = "dp", "blend", "av_buf", "aud";
    			status = "disabled";
    
    			gfx-layer {
    				dma-names = "gfx0";
    				dmas = < 0x31 0x03 >;
    			};
    
    			i2c-bus {
    			};
    
    			vid-layer {
    				dma-names = "vid0", "vid1", "vid2";
    				dmas = < 0x31 0x00 >, < 0x31 0x01 >, < 0x31 0x02 >;
    			};
    
    			zynqmp_dp_snd_card0: zynqmp_dp_snd_card {
    				compatible = "xlnx,dp-snd-card";
    				xlnx,dp-snd-codec = < 0x34 >;
    				xlnx,dp-snd-pcm = < 0x32 >, < 0x33 >;
    			};
    
    			zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 {
    				clock-names = "aud_clk";
    				clocks = < 0x03 0x11 >;
    				compatible = "xlnx,dp-snd-codec";
    				phandle = < 0x34 >;
    			};
    
    			zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 {
    				compatible = "xlnx,dp-snd-pcm";
    				dma-names = "tx";
    				dmas = < 0x31 0x04 >;
    				phandle = < 0x32 >;
    			};
    
    			zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 {
    				compatible = "xlnx,dp-snd-pcm";
    				dma-names = "tx";
    				dmas = < 0x31 0x05 >;
    				phandle = < 0x33 >;
    			};
    		};
    
    		serdes: zynqmp_phy@fd400000 {
    			compatible = "xlnx,zynqmp-psgtr-v1.1";
    			nvmem-cell-names = "soc_revision";
    			nvmem-cells = < 0x1b >;
    			reg = < 0x00 0xfd400000 0x00 0x40000 >, < 0x00 0xfd3d0000 0x00 0x1000 >;
    			reg-names = "serdes", "siou";
    			reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", "gem1_rst", "gem2_rst", "gem3_rst";
    			resets = < 0x1c 0x10 >, < 0x1c 0x3b >, < 0x1c 0x3c >, < 0x1c 0x3d >, < 0x1c 0x3e >, < 0x1c 0x3f >, < 0x1c 0x40 >, < 0x1c 0x03 >, < 0x1c 0x1d >, < 0x1c 0x1e >, < 0x1c 0x1f >, < 0x1c 0x20 >;
    			status = "okay";
    
    			lane0: lane0 {
    				#phy-cells = < 0x04 >;
    			};
    
    			lane1: lane1 {
    				#phy-cells = < 0x04 >;
    			};
    
    			lane2: lane2 {
    				#phy-cells = < 0x04 >;
    				phandle = < 0x2d >;
    			};
    
    			lane3: lane3 {
    				#phy-cells = < 0x04 >;
    			};
    		};
    	};
    
    	amba_apu: amba_apu@0 {
    		#address-cells = < 0x02 >;
    		#size-cells = < 0x01 >;
    		compatible = "simple-bus";
    		ranges = < 0x00 0x00 0x00 0x00 0xffffffff >;
    
    		gic: interrupt-controller@f9010000 {
    			#interrupt-cells = < 0x03 >;
    			compatible = "arm,gic-400", "arm,cortex-a15-gic";
    			interrupt-controller;
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x01 0x09 0xf04 >;
    			phandle = < 0x04 >;
    			reg = < 0x00 0xf9010000 0x10000 >, < 0x00 0xf9020000 0x20000 >, < 0x00 0xf9040000 0x20000 >, < 0x00 0xf9060000 0x20000 >;
    		};
    	};
    
    	amba_pl: amba_pl@0 {
    		#address-cells = < 0x02 >;
    		#size-cells = < 0x02 >;
    		compatible = "simple-bus";
    		ranges;
    
    		psu_ctrl_ipi: PERIPHERAL@ff380000 {
    			compatible = "xlnx,PERIPHERAL-1.0";
    			reg = < 0x00 0xff380000 0x00 0x80000 >;
    		};
    
    		psu_message_buffers: PERIPHERAL@ff990000 {
    			compatible = "xlnx,PERIPHERAL-1.0";
    			reg = < 0x00 0xff990000 0x00 0x10000 >;
    		};
    
    		cf_ad9361_dac_core_0: cf-ad9361-dds-core-lpc@99024000 {
    			clock-names = "sampl_clk";
    			clocks = < 0x3b 0x0d >;
    			compatible = "adi,axi-ad9361-dds-6.00.a";
    			dma-names = "tx";
    			dmas = < 0x3c 0x00 >;
    			reg = < 0x00 0x99024000 0x00 0x1000 >;
    		};
    
    		cf_ad9361_adc_core_0: cf-ad9361-lpc@99020000 {
    			compatible = "adi,axi-ad9361-6.00.a";
    			dma-names = "rx";
    			dmas = < 0x3a 0x00 >;
    			reg = < 0x00 0x99020000 0x00 0x6000 >;
    			spibus-connected = < 0x3b >;
    		};
    
    		rx_dma: dma@80010000 {
    			#clock-cells = < 0x00 >;
    			#dma-cells = < 0x01 >;
    			clocks = < 0x03 0x47 >;
    			compatible = "adi,axi-dmac-1.00.a";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x6e 0x00 >;
    			phandle = < 0x3a >;
    			reg = < 0x00 0x80010000 0x00 0x1000 >;
    
    			adi,channels {
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    
    				dma-channel@0 {
    					adi,destination-bus-type = < 0x00 >;
    					adi,destination-bus-width = < 0x40 >;
    					adi,source-bus-type = < 0x02 >;
    					adi,source-bus-width = < 0x40 >;
    					reg = < 0x00 >;
    				};
    			};
    		};
    
    		tx_dma: dma@80011000 {
    			#clock-cells = < 0x00 >;
    			#dma-cells = < 0x01 >;
    			clocks = < 0x03 0x47 >;
    			compatible = "adi,axi-dmac-1.00.a";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x6d 0x00 >;
    			phandle = < 0x3c >;
    			reg = < 0x00 0x80011000 0x00 0x1000 >;
    
    			adi,channels {
    				#address-cells = < 0x01 >;
    				#size-cells = < 0x00 >;
    
    				dma-channel@0 {
    					adi,destination-bus-type = < 0x02 >;
    					adi,destination-bus-width = < 0x40 >;
    					adi,source-bus-type = < 0x00 >;
    					adi,source-bus-width = < 0x40 >;
    					reg = < 0x00 >;
    				};
    			};
    		};
    
    		axi_gpio_tr600_misc: gpio@80012000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "resetb", "en_agc", "pg_fmc", "adc_pd";
    			phandle = < 0x24 >;
    			reg = < 0x00 0x80012000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x00 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x0f >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x04 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0x00 >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_0: gpio@80013000 {
    			#gpio-cells = < 0x03 >;
    			#interrupt-cells = < 0x02 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "pps", "adc_irq";
    			interrupt-controller;
    			interrupt-names = "ip2intc_irpt";
    			interrupt-parent = < 0x04 >;
    			interrupts = < 0x00 0x5a 0x04 >;
    			phandle = < 0x43 >;
    			reg = < 0x00 0x80013000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x01 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x00 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x00 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x02 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x01 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0xffffffff >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_1v8: gpio@a0001000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "zynq_gpio_1v8_0_se", "zynq_gpio_1v8_1_se", "zynq_gpio_1v8_2_se", "zynq_gpio_1v8_3_se", "zynq_gpio_1v8_4_se", "zynq_gpio_1v8_5_se", "zynq_gpio_1v8_6_se", "zynq_gpio_1v8_7_se", "zynq_gpio_1v8_8_se", "zynq_gpio_1v8_9_se", "zynq_gpio_1v8_10_se", "zynq_gpio_1v8_11_se", "zynq_gpio_1v8_12_se", "zynq_gpio_1v8_13_se";
    			gpio2-line-names = "zynq_pa3_gpio_1v8_0", "pa3_zynq_emmc0_pwr_en_n", "pa3_zynq_emmc1_pwr_en_n", "pa3_zynq_usb_fault", "zynq_pa3_usb_en";
    			reg = < 0x00 0xa0001000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x00 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x00 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x05 >;
    			xlnx,gpio2-width = < 0x05 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0xffffffff >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_ad9361_misc: gpio@a0002000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "up_enable", "up_txnrx";
    			phandle = < 0x25 >;
    			reg = < 0x00 0xa0002000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x01 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x00 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x02 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0x00 >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_LEDs_3v3: gpio@a0005000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "zynq_pim_led0_3v3", "zynq_pim_led1_3v3";
    			reg = < 0x00 0xa0005000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x01 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x00 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x02 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0xffffffff >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_can_term: gpio@a0006000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "can_term";
    			reg = < 0x00 0xa0006000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x01 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x00 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x01 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0xffffffff >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    
    		axi_gpio_gtrefclk_usb_en: gpio@a0007000 {
    			#gpio-cells = < 0x03 >;
    			clock-names = "s_axi_aclk";
    			clocks = < 0x03 0x47 >;
    			compatible = "xlnx,xps-gpio-1.00.a";
    			gpio-controller;
    			gpio-line-names = "ps_gtrefclk_usb_1v8_en";
    			reg = < 0x00 0xa0007000 0x00 0x1000 >;
    			xlnx,all-inputs = < 0x00 >;
    			xlnx,all-inputs-2 = < 0x00 >;
    			xlnx,all-outputs = < 0x01 >;
    			xlnx,all-outputs-2 = < 0x00 >;
    			xlnx,dout-default = < 0x01 >;
    			xlnx,dout-default-2 = < 0x00 >;
    			xlnx,gpio-width = < 0x01 >;
    			xlnx,gpio2-width = < 0x20 >;
    			xlnx,interrupt-present = < 0x00 >;
    			xlnx,is-dual = < 0x00 >;
    			xlnx,tri-default = < 0xffffffff >;
    			xlnx,tri-default-2 = < 0xffffffff >;
    		};
    	};
    
    	aux_ref_clk: aux_ref_clk {
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0x19bfcc0 >;
    		compatible = "fixed-clock";
    		phandle = < 0x38 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	chosen {
    		bootargs = "earlycon clk_ignore_unused";
    		stdout-path = "serial0:115200n8";
    	};
    
    	clk: clk {
    		#clock-cells = < 0x01 >;
    		clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", "aux_ref_clk", "gt_crx_ref_clk";
    		clocks = < 0x35 >, < 0x36 >, < 0x37 >, < 0x38 >, < 0x39 >;
    		compatible = "xlnx,zynqmp-clk";
    		phandle = < 0x03 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	clocks {
    
    		ad9361_clkin: clock@0 {
    			#clock-cells = < 0x00 >;
    			clock-frequency = < 0x2625a00 >;
    			clock-output-names = "ad9361_ext_refclk";
    			compatible = "fixed-clock";
    			phandle = < 0x23 >;
    		};
    	};
    
    	cpu_opp_table: cpu_opp_table {
    		compatible = "operating-points-v2";
    		opp-shared;
    		phandle = < 0x01 >;
    
    		opp00 {
    			clock-latency-ns = < 0x7a120 >;
    			opp-hz = /bits/ 64 < 0x47868bf4 >;
    			opp-microvolt = < 0xf4240 >;
    		};
    
    		opp01 {
    			clock-latency-ns = < 0x7a120 >;
    			opp-hz = /bits/ 64 < 0x23c345fa >;
    			opp-microvolt = < 0xf4240 >;
    		};
    
    		opp02 {
    			clock-latency-ns = < 0x7a120 >;
    			opp-hz = /bits/ 64 < 0x17d783fc >;
    			opp-microvolt = < 0xf4240 >;
    		};
    
    		opp03 {
    			clock-latency-ns = < 0x7a120 >;
    			opp-hz = /bits/ 64 < 0x11e1a2fd >;
    			opp-microvolt = < 0xf4240 >;
    		};
    	};
    
    	cpus {
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x00 >;
    
    		cpu0: cpu@0 {
    			clocks = < 0x03 0x0a >;
    			compatible = "arm,cortex-a53", "arm,armv8";
    			cpu-idle-states = < 0x02 >;
    			device_type = "cpu";
    			enable-method = "psci";
    			operating-points-v2 = < 0x01 >;
    			reg = < 0x00 >;
    		};
    
    		cpu1: cpu@1 {
    			compatible = "arm,cortex-a53", "arm,armv8";
    			cpu-idle-states = < 0x02 >;
    			device_type = "cpu";
    			enable-method = "psci";
    			operating-points-v2 = < 0x01 >;
    			reg = < 0x01 >;
    		};
    
    		cpu2: cpu@2 {
    			compatible = "arm,cortex-a53", "arm,armv8";
    			cpu-idle-states = < 0x02 >;
    			device_type = "cpu";
    			enable-method = "psci";
    			operating-points-v2 = < 0x01 >;
    			reg = < 0x02 >;
    		};
    
    		cpu3: cpu@3 {
    			compatible = "arm,cortex-a53", "arm,armv8";
    			cpu-idle-states = < 0x02 >;
    			device_type = "cpu";
    			enable-method = "psci";
    			operating-points-v2 = < 0x01 >;
    			reg = < 0x03 >;
    		};
    
    		idle-states {
    			entry-method = "arm,psci";
    
    			CPU_SLEEP_0: cpu-sleep-0 {
    				arm,psci-suspend-param = < 0x40000000 >;
    				compatible = "arm,idle-state";
    				entry-latency-us = < 0x12c >;
    				exit-latency-us = < 0x258 >;
    				local-timer-stop;
    				min-residency-us = < 0x2710 >;
    				phandle = < 0x02 >;
    			};
    		};
    	};
    
    	dcc: dcc {
    		compatible = "arm,dcc";
    		status = "disabled";
    		u-boot,dm-pre-reloc;
    	};
    
    	dp_aclk: dp_aclk {
    		#clock-cells = < 0x00 >;
    		clock-accuracy = < 0x64 >;
    		clock-frequency = < 0x5f5e100 >;
    		compatible = "fixed-clock";
    		phandle = < 0x30 >;
    	};
    
    	edac {
    		compatible = "arm,cortex-a53-edac";
    	};
    
    	fclk0: fclk0 {
    		clocks = < 0x03 0x47 >;
    		compatible = "xlnx,fclk";
    		status = "disabled";
    	};
    
    	fclk1: fclk1 {
    		clocks = < 0x03 0x48 >;
    		compatible = "xlnx,fclk";
    		status = "disabled";
    	};
    
    	fclk2: fclk2 {
    		clocks = < 0x03 0x49 >;
    		compatible = "xlnx,fclk";
    		status = "disabled";
    	};
    
    	fclk3: fclk3 {
    		clocks = < 0x03 0x4a >;
    		compatible = "xlnx,fclk";
    		status = "disabled";
    	};
    
    	firmware {
    
    		zynqmp_firmware: zynqmp-firmware {
    			compatible = "xlnx,zynqmp-firmware";
    			method = "smc";
    		};
    	};
    
    	vref_pim_adc: fixed-regulator@0 {
    		compatible = "regulator-fixed";
    		phandle = < 0x21 >;
    		regulator-always-on;
    		regulator-max-microvolt = < 0x2625a0 >;
    		regulator-min-microvolt = < 0x2625a0 >;
    		regulator-name = "vref_pim_adc";
    	};
    
    	fpga_full: fpga-full {
    		#address-cells = < 0x02 >;
    		#size-cells = < 0x02 >;
    		compatible = "fpga-region";
    		fpga-mgr = < 0x06 >;
    	};
    
    	gpio-poweroff {
    		compatible = "gpio-poweroff";
    		gpios = < 0x3d 0x00 0x00 >;
    	};
    
    	gpio-restart {
    		active-delay = < 0x64 >;
    		compatible = "gpio-restart";
    		gpios = < 0x3d 0x08 0x00 >;
    		inactive-delay = < 0x64 >;
    		priority = < 0xff >;
    		wait-delay = < 0x3e8 >;
    	};
    
    	gt_crx_ref_clk: gt_crx_ref_clk {
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0x66ff300 >;
    		compatible = "fixed-clock";
    		phandle = < 0x39 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	iio_hwmon_adc0 {
    		compatible = "iio-hwmon";
    		io-channel-names = "cur_vcc_in", "vcc_in", "vcc_3v3", "vcc_5v0";
    		io-channels = < 0x3f 0x04 >, < 0x3f 0x05 >, < 0x3f 0x06 >, < 0x3f 0x07 >;
    	};
    
    	iio_hwmon_adc1 {
    		compatible = "iio-hwmon";
    		io-channel-names = "emmc0_icc", "emmc0_iccq", "emmc1_icc", "emmc1_iccq";
    		io-channels = < 0x40 0x04 >, < 0x40 0x05 >, < 0x40 0x06 >, < 0x40 0x07 >;
    	};
    
    	iio_hwmon_adc2 {
    		compatible = "iio-hwmon";
    		io-channel-names = "cur_vcc_1v8", "vcc_0v85", "vcc_1v1", "vcc_1v8";
    		io-channels = < 0x41 0x04 >, < 0x41 0x05 >, < 0x41 0x06 >, < 0x41 0x07 >;
    	};
    
    	iio_hwmon_ams_ctrl {
    		compatible = "iio-hwmon";
    		io-channel-names = "vcc_pspll0", "vcc_psbatt", "vccint", "vccbram", "vccaux", "vcc_psddrpll", "vccpsintfpddr", "ps_temp", "remote_temp", "vccpsintlp", "vccpsintfp", "vccpsaux", "vccpsddr", "vccpsio3", "vccpsio0", "vccpsio1", "vccpsio2", "psmgtravcc", "psmgtravtt", "vccams", "pl_temp", "vccint", "vccaux", "vccvrefp", "vccvrefn", "vccbram", "vccplintlp", "vccplintfp", "vccplaux", "vccams";
    		io-channels = < 0x3e 0x00 >, < 0x3e 0x01 >, < 0x3e 0x02 >, < 0x3e 0x03 >, < 0x3e 0x04 >, < 0x3e 0x05 >, < 0x3e 0x06 >, < 0x3e 0x07 >, < 0x3e 0x08 >, < 0x3e 0x09 >, < 0x3e 0x0a >, < 0x3e 0x0b >, < 0x3e 0x0c >, < 0x3e 0x0d >, < 0x3e 0x0e >, < 0x3e 0x0f >, < 0x3e 0x10 >, < 0x3e 0x11 >, < 0x3e 0x12 >, < 0x3e 0x13 >, < 0x3e 0x14 >, < 0x3e 0x15 >, < 0x3e 0x16 >, < 0x3e 0x17 >, < 0x3e 0x18 >, < 0x3e 0x19 >, < 0x3e 0x1a >, < 0x3e 0x1b >, < 0x3e 0x1c >, < 0x3e 0x1d >;
    	};
    
    	iio_hwmon_pim_adc {
    		compatible = "iio-hwmon";
    		io-channels = < 0x42 0x00 >, < 0x42 0x01 >, < 0x42 0x02 >, < 0x42 0x03 >, < 0x42 0x04 >, < 0x42 0x05 >, < 0x42 0x06 >, < 0x42 0x07 >;
    	};
    
    	ipi_mailbox_pmu1: mailbox@ff990400 {
    		#mbox-cells = < 0x01 >;
    		compatible = "xlnx,zynqmp-ipi-mailbox";
    		interrupt-parent = < 0x04 >;
    		interrupts = < 0x00 0x23 0x04 >;
    		phandle = < 0x05 >;
    		reg = < 0x00 0xff9905c0 0x00 0x20 >, < 0x00 0xff9905e0 0x00 0x20 >, < 0x00 0xff990e80 0x00 0x20 >, < 0x00 0xff990ea0 0x00 0x20 >;
    		reg-names = "local_request_region", "local_response_region", "remote_request_region", "remote_response_region";
    		xlnx,ipi-ids = < 0x00 0x04 >;
    	};
    
    	memory@0 {
    		device_type = "memory";
    		reg = < 0x00 0x00 0x00 0x80000000 >;
    	};
    
    	nvmem_firmware {
    		#address-cells = < 0x01 >;
    		#size-cells = < 0x01 >;
    		compatible = "xlnx,zynqmp-nvmem-fw";
    
    		soc_revision: soc_revision@0 {
    			phandle = < 0x1b >;
    			reg = < 0x00 0x04 >;
    		};
    	};
    
    	pcap: pcap {
    		compatible = "xlnx,zynqmp-pcap-fpga";
    		phandle = < 0x06 >;
    	};
    
    	pmu {
    		compatible = "arm,armv8-pmuv3";
    		interrupt-parent = < 0x04 >;
    		interrupts = < 0x00 0x8f 0x04 >, < 0x00 0x90 0x04 >, < 0x00 0x91 0x04 >, < 0x00 0x92 0x04 >;
    	};
    
    	power-domains {
    		compatible = "xlnx,zynqmp-genpd";
    
    		pd_adma: pd-adma {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2b >;
    			phandle = < 0x0c >;
    		};
    
    		pd_can0: pd-can0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2f >;
    			phandle = < 0x07 >;
    		};
    
    		pd_can1: pd-can1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x30 >;
    			phandle = < 0x08 >;
    		};
    
    		pd_dp: pd-dp {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x29 >;
    			phandle = < 0x2f >;
    		};
    
    		pd_eth0: pd-eth0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1d >;
    			phandle = < 0x0e >;
    		};
    
    		pd_eth1: pd-eth1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1e >;
    			phandle = < 0x0f >;
    		};
    
    		pd_eth2: pd-eth2 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1f >;
    			phandle = < 0x10 >;
    		};
    
    		pd_eth3: pd-eth3 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x20 >;
    			phandle = < 0x11 >;
    		};
    
    		pd_gdma: pd-gdma {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2a >;
    			phandle = < 0x0a >;
    		};
    
    		pd_gpio: pd-gpio {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2e >;
    			phandle = < 0x14 >;
    		};
    
    		pd_gpu: pd-gpu {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x3a 0x14 0x15 >;
    			phandle = < 0x0b >;
    		};
    
    		pd_i2c0: pd-i2c0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x25 >;
    			phandle = < 0x15 >;
    		};
    
    		pd_i2c1: pd-i2c1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x26 >;
    			phandle = < 0x16 >;
    		};
    
    		pd_nand: pd-nand {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2c >;
    			phandle = < 0x0d >;
    		};
    
    		pd_pcie: pd-pcie {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x3b >;
    			phandle = < 0x19 >;
    		};
    
    		pd_qspi: pd-qspi {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x2d >;
    			phandle = < 0x1a >;
    		};
    
    		pd_sata: pd-sata {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1c >;
    			phandle = < 0x1d >;
    		};
    
    		pd_sd0: pd-sd0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x27 >;
    			phandle = < 0x1e >;
    		};
    
    		pd_sd1: pd-sd1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x28 >;
    			phandle = < 0x1f >;
    		};
    
    		pd_spi0: pd-spi0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x23 >;
    			phandle = < 0x20 >;
    		};
    
    		pd_spi1: pd-spi1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x24 >;
    			phandle = < 0x22 >;
    		};
    
    		pd_ttc0: pd-ttc0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x18 >;
    			phandle = < 0x26 >;
    		};
    
    		pd_ttc1: pd-ttc1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x19 >;
    			phandle = < 0x27 >;
    		};
    
    		pd_ttc2: pd-ttc2 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1a >;
    			phandle = < 0x28 >;
    		};
    
    		pd_ttc3: pd-ttc3 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x1b >;
    			phandle = < 0x29 >;
    		};
    
    		pd_uart0: pd-uart0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x21 >;
    			phandle = < 0x2a >;
    		};
    
    		pd_uart1: pd-uart1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x22 >;
    			phandle = < 0x2b >;
    		};
    
    		pd_usb0: pd-usb0 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x16 >;
    			phandle = < 0x2c >;
    		};
    
    		pd_usb1: pd-usb1 {
    			#power-domain-cells = < 0x00 >;
    			pd-id = < 0x17 >;
    			phandle = < 0x2e >;
    		};
    	};
    
    	pps {
    		compatible = "pps-gpio";
    		gpios = < 0x43 0x00 0x00 0x00 >;
    		status = "okay";
    	};
    
    	psci {
    		compatible = "arm,psci-0.2";
    		method = "smc";
    	};
    
    	pss_alt_ref_clk: pss_alt_ref_clk {
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0x00 >;
    		compatible = "fixed-clock";
    		phandle = < 0x37 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	pss_ref_clk: pss_ref_clk {
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0x1fca055 >;
    		compatible = "fixed-clock";
    		phandle = < 0x35 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	rst: reset-controller {
    		#reset-cells = < 0x01 >;
    		compatible = "xlnx,zynqmp-reset";
    		phandle = < 0x1c >;
    	};
    
    	xlnx_keccak_384: sha384 {
    		compatible = "xlnx,zynqmp-keccak-384";
    	};
    
    	timer {
    		compatible = "arm,armv8-timer";
    		interrupt-parent = < 0x04 >;
    		interrupts = < 0x01 0x0d 0xf08 >, < 0x01 0x0e 0xf08 >, < 0x01 0x0b 0xf08 >, < 0x01 0x0a 0xf08 >;
    	};
    
    	video_clk: video_clk {
    		#clock-cells = < 0x00 >;
    		clock-frequency = < 0x19bfcc0 >;
    		compatible = "fixed-clock";
    		phandle = < 0x36 >;
    		u-boot,dm-pre-reloc;
    	};
    
    	zynqmp_power: zynqmp-power {
    		compatible = "xlnx,zynqmp-power";
    		mbox-names = "tx", "rx";
    		mboxes = < 0x05 0x00 >, < 0x05 0x01 >;
    	};
    
    	xlnx_rsa: zynqmp_rsa {
    		compatible = "xlnx,zynqmp-rsa";
    	};
    };
    

    clock summary:

       clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
    ----------------------------------------------------------------------------------------
     spi2.0-tx_lo_dummy                       0            0  1225000000          0 0  
     spi2.0-rx_lo_dummy                       0            0  1200000000          0 0  
     video_clk                                0            0    27000000          0 0  
     pss_ref_clk                              4            4    33333333          0 0  
        vpll_post_src                         0            0    33333333          0 0  
        vpll_pre_src                          0            0    33333333          0 0  
           vpll_int                           0            0  2133333312          0 0  
              vpll_half                       0            0  1066666656          0 0  
                 vpll_int_mux                 0            0  1066666656          0 0  
                    vpll                      0            0  1066666656          0 0  
                       topsw_main_mux           0            0  1066666656          0 0  
                          topsw_main_div1           0            0   533333328          0 0  
                             topsw_main           0            0   533333328          0 0  
                       dp_stc_ref_mux           0            0  1066666656          0 0  
                          dp_stc_ref_div1           0            0    21333334          0 0  
                             dp_stc_ref_div2           0            0      666667          0 0  
                                dp_stc_ref           0            0      666667          0 0  
                       dp_audio_ref_mux           0            0  1066666656          0 0  
                          dp_audio_ref_div1           0            0    30476191          0 0  
                             dp_audio_ref_div2           0            0    10158731          0 0  
                                dp_audio_ref           0            0    10158731          0 0  
                       vpll_to_lpd            0            0   533333328          0 0  
        dpll_post_src                         0            0    33333333          0 0  
        dpll_pre_src                          1            1    33333333          0 0  
           dpll_int                           1            1  2399999976          0 0  
              dpll_half                       1            1  1199999988          0 0  
                 dpll_int_mux                 1            1  1199999988          0 0  
                    dpll                      1            1  1199999988          0 0  
                       gpu_ref_mux            0            0  1199999988          0 0  
                          gpu_ref_div1           0            0   599999994          0 0  
                             gpu_ref           0            0   599999994          0 0  
                                gpu_pp1_ref           0            0   599999994          0 0  
                                gpu_pp0_ref           0            0   599999994          0 0  
                       pcie_ref_mux           0            0  1199999988          0 0  
                          pcie_ref_div1           0            0    99999999          0 0  
                             pcie_ref           0            0    99999999          0 0  
                       sata_ref_mux           0            0  1199999988          0 0  
                          sata_ref_div1           0            0    99999999          0 0  
                             sata_ref           0            0    99999999          0 0  
                       ddr_ref_mux            1            1  1199999988          0 0  
                          ddr_ref             1            1   239999998          0 0  
                       dpdma_ref_mux           0            0  1199999988          0 0  
                          dpdma_ref_div1           0            0   599999994          0 0  
                             dpdma_ref           0            0   599999994          0 0  
                       gdma_ref_mux           0            0  1199999988          0 0  
                          gdma_ref_div1           0            0   599999994          0 0  
                             gdma_ref           0            0   599999994          0 0  
                       dp_video_ref_mux           0            0  1199999988          0 0  
                          dp_video_ref_div1           0            0   119999999          0 0  
                             dp_video_ref_div2           0            0   119999999          0 0  
                                dp_video_ref           0            0   119999999          0 0  
                       dpll_to_lpd            0            0   399999996          0 0  
        apll_post_src                         0            0    33333333          0 0  
        apll_pre_src                          1            1    33333333          0 0  
           apll_int                           1            1  2399999976          0 0  
              apll_half                       1            1  1199999988          0 0  
                 apll_int_mux                 1            1  1199999988          0 0  
                    apll                      1            1  1199999988          0 0  
                       acpu_mux               1            1  1199999988          0 0  
                          acpu_div1           1            1  1199999988          0 0  
                             acpu             1            1  1199999988          0 0  
                                acpu_half_ff           0            0   599999994          0 0  
                                   acpu_half           0            0   599999994          0 0  
                       apll_to_lpd            0            0   399999996          0 0  
        rpll_post_src                         0            0    33333333          0 0  
        rpll_pre_src                          1            1    33333333          0 0  
           rpll_int                           1            1  1599999984          0 0  
              rpll_half                       1            1   799999992          0 0  
                 rpll_int_mux                 1            1   799999992          0 0  
                    rpll                      4            4   799999992          0 0  
                       pl2_ref_mux            0            0   799999992          0 0  
                          pl2_ref_div1           0            0    16000000          0 0  
                             pl2_ref_div2           0            0     1000000          0 0  
                                pl2_ref           0            0     1000000          0 0  
                       pl1_ref_mux            0            0   799999992          0 0  
                          pl1_ref_div1           0            0   199999998          0 0  
                             pl1_ref_div2           0            0   199999998          0 0  
                                pl1_ref           0            0   199999998          0 0  
                       pl0_ref_mux            1            1   799999992          0 0  
                          pl0_ref_div1           1            1    99999999          0 0  
                             pl0_ref_div2           1            1    99999999          0 0  
                                pl0_ref           3           10    99999999          0 0  
                       spi1_ref_mux           1            1   799999992          0 0  
                          spi1_ref_div1           1            1   199999998          0 0  
                             spi1_ref_div2           1            1   199999998          0 0  
                                spi1_ref           1            1   199999998          0 0  
                       spi0_ref_mux           0            0   799999992          0 0  
                          spi0_ref_div1           0            0   199999998          0 0  
                             spi0_ref_div2           0            0   199999998          0 0  
                                spi0_ref           0            0   199999998          0 0  
                       sdio1_ref_mux           1            1   799999992          0 0  
                          sdio1_ref_div1           1            1   199999998          0 0  
                             sdio1_ref_div2           1            1   199999998          0 0  
                                sdio1_ref           1            1   199999998          0 0  
                       sdio0_ref_mux           1            1   799999992          0 0  
                          sdio0_ref_div1           1            1   199999998          0 0  
                             sdio0_ref_div2           1            1   199999998          0 0  
                                sdio0_ref           1            1   199999998          0 0  
                       iou_switch_mux           0            0   799999992          0 0  
                          iou_switch_div1           0            0   266666664          0 0  
                             iou_switch           0            0   266666664          0 0  
                       rpll_to_fpd            0            0   399999996          0 0  
        iopll_post_src                        0            0    33333333          0 0  
        iopll_pre_src                         1            1    33333333          0 0  
           iopll_int                          1            1  2999999970          0 0  
              iopll_half                      1            1  1499999985          0 0  
                 iopll_int_mux                1            1  1499999985          0 0  
                    iopll                     9           11  1499999985          0 0  
                       pl3_ref_mux            0            0  1499999985          0 0  
                          pl3_ref_div1           0            0    46875000          0 0  
                             pl3_ref_div2           0            0     9375000          0 0  
                                pl3_ref           0            0     9375000          0 0  
                       ams_ref_mux            1            1  1499999985          0 0  
                          ams_ref_div1           1            1    50000000          0 0  
                             ams_ref_div2           1            1    50000000          0 0  
                                ams_ref           1            1    50000000          0 0  
                       adma_ref_mux           0            0  1499999985          0 0  
                          adma_ref_div1           0            0   499999995          0 0  
                             adma_ref           0            0   499999995          0 0  
                       dll_ref                0            0  1499999985          0 0  
                       can1_ref_mux           0            0  1499999985          0 0  
                          can1_ref_div1           0            0    99999999          0 0  
                             can1_ref_div2           0            0    99999999          0 0  
                                can1_ref           0            0    99999999          0 0  
                                   can1           0            0    99999999          0 0  
                       can0_ref_mux           0            0  1499999985          0 0  
                          can0_ref_div1           0            0    99999999          0 0  
                             can0_ref_div2           0            0    99999999          0 0  
                                can0_ref           0            0    99999999          0 0  
                                   can0           0            0    99999999          0 0  
                       i2c1_ref_mux           0            1  1499999985          0 0  
                          i2c1_ref_div1           0            1    99999999          0 0  
                             i2c1_ref_div2           0            1    99999999          0 0  
                                i2c1_ref           0            1    99999999          0 0  
                       i2c0_ref_mux           0            1  1499999985          0 0  
                          i2c0_ref_div1           0            1    99999999          0 0  
                             i2c0_ref_div2           0            1    99999999          0 0  
                                i2c0_ref           0            1    99999999          0 0  
                       nand_ref_mux           0            0  1499999985          0 0  
                          nand_ref_div1           0            0    46875000          0 0  
                             nand_ref_div2           0            0     9375000          0 0  
                                nand_ref           0            0     9375000          0 0  
                       uart1_ref_mux           1            1  1499999985          0 0  
                          uart1_ref_div1           1            1    99999999          0 0  
                             uart1_ref_div2           1            1    99999999          0 0  
                                uart1_ref           1            1    99999999          0 0  
                       uart0_ref_mux           1            1  1499999985          0 0  
                          uart0_ref_div1           1            1    99999999          0 0  
                             uart0_ref_div2           1            1    99999999          0 0  
                                uart0_ref           1            1    99999999          0 0  
                       qspi_ref_mux           1            1  1499999985          0 0  
                          qspi_ref_div1           1            1   299999997          0 0  
                             qspi_ref_div2           1            1   299999997          0 0  
                                qspi_ref           1            1   299999997          0 0  
                       gem3_ref_mux           1            1  1499999985          0 0  
                          gem3_ref_div1           1            1   124999999          0 0  
                             gem3_ref_div2           1            1   124999999          0 0  
                                gem3_ref           2            2   124999999          0 0  
                                   gem3_tx_mux           1            1   124999999          0 0  
                                      gem3_tx           2            2   124999999          0 0  
                       gem2_ref_mux           0            0  1499999985          0 0  
                          gem2_ref_div1           0            0    62500000          0 0  
                             gem2_ref_div2           0            0    62500000          0 0  
                                gem2_ref           0            0    62500000          0 0  
                                   gem2_tx_mux           0            0    62500000          0 0  
                                      gem2_tx           0            0    62500000          0 0  
                       gem1_ref_mux           0            0  1499999985          0 0  
                          gem1_ref_div1           0            0    62500000          0 0  
                             gem1_ref_div2           0            0    62500000          0 0  
                                gem1_ref           0            0    62500000          0 0  
                                   gem1_tx_mux           0            0    62500000          0 0  
                                      gem1_tx           0            0    62500000          0 0  
                       gem0_ref_mux           0            0  1499999985          0 0  
                          gem0_ref_div1           0            0    62500000          0 0  
                             gem0_ref_div2           0            0    62500000          0 0  
                                gem0_ref           0            0    62500000          0 0  
                                   gem0_tx_mux           0            0    62500000          0 0  
                                      gem0_tx           0            0    62500000          0 0  
                       gem_tsu_ref_mux           1            1  1499999985          0 0  
                          gem_tsu_ref_div1           1            1   249999998          0 0  
                             gem_tsu_ref_div2           1            1   249999998          0 0  
                                gem_tsu_ref           1            1   249999998          0 0  
                                   gem_tsu           1            1   249999998          0 0  
                       pcap_mux               0            0  1499999985          0 0  
                          pcap_div1           0            0   187499999          0 0  
                             pcap             0            0   187499999          0 0  
                       csu_pll_mux            0            0  1499999985          0 0  
                          csu_pll_div1           0            0   187499999          0 0  
                             csu_pll           0            0   187499999          0 0  
                       cpu_r5_mux             0            0  1499999985          0 0  
                          cpu_r5_div1           0            0   499999995          0 0  
                             cpu_r5           0            0   499999995          0 0  
                                cpu_r5_core           0            0   499999995          0 0  
                       usb3_dual_ref_mux           1            1  1499999985          0 0  
                          usb3_dual_ref_div1           1            1    60000000          0 0  
                             usb3_dual_ref_div2           1            1    20000000          0 0  
                                usb3_dual_ref           1            1    20000000          0 0  
                       usb1_bus_ref_mux           0            0  1499999985          0 0  
                          usb1_bus_ref_div1           0            0   124999999          0 0  
                             usb1_bus_ref_div2           0            0   124999999          0 0  
                                usb1_bus_ref           0            0   124999999          0 0  
                       usb0_bus_ref_mux           1            1  1499999985          0 0  
                          usb0_bus_ref_div1           1            1   249999998          0 0  
                             usb0_bus_ref_div2           1            1   249999998          0 0  
                                usb0_bus_ref           1            1   249999998          0 0  
                       lpd_lsbus_mux           1            1  1499999985          0 0  
                          lpd_lsbus_div1           1            1    99999999          0 0  
                             lpd_lsbus           8            8    99999999          0 0  
                       lpd_switch_mux           0            0  1499999985          0 0  
                          lpd_switch_div1           0            0   499999995          0 0  
                             lpd_switch           0            0   499999995          0 0  
                       dbg_lpd_mux            0            0  1499999985          0 0  
                          dbg_lpd_div1           0            0   249999998          0 0  
                             dbg_lpd           0            0   249999998          0 0  
                       iopll_to_fpd           0            0   499999995          0 0  
                          gtgref0_ref_mux           0            0   499999995          0 0  
                             gtgref0_ref_div1           0            0    62500000          0 0  
                                gtgref0_ref           0            0    62500000          0 0  
                          topsw_lsbus_mux           0            0   499999995          0 0  
                             topsw_lsbus_div1           0            0    99999999          0 0  
                                topsw_lsbus           0            0    99999999          0 0  
                                   wdt           0            0    99999999          0 0  
                          dbg_tstmp_mux           0            0   499999995          0 0  
                             dbg_tstmp           0            0   249999998          0 0  
                          dbg_trace_mux           0            0   499999995          0 0  
                             dbg_trace_div1           0            0    13513514          0 0  
                                dbg_trace           0            0    13513514          0 0  
                          dbg_fpd_mux           0            0   499999995          0 0  
                             dbg_fpd_div1           0            0   249999998          0 0  
                                dbg_fpd           0            0   249999998          0 0  
        timestamp_ref_mux                     0            0    33333333          0 0  
           timestamp_ref_div1                 0            0    33333333          0 0  
              timestamp_ref                   0            0    33333333          0 0  
     pss_alt_ref_clk                          0            0           0          0 0  
     gt_crx_ref_clk                           0            0   108000000          0 0  
     dp_aclk                                  0            0   100000000        100 0  
     ad9361_ext_refclk                        4            4    40000000          0 0  
        spi2.0-bb_refclk                      1            1    40000000          0 0  
           spi2.0-bbpll_clk                   1            1           0          0 0  
              spi2.0-adc_clk                  1            1           0          0 0  
                 spi2.0-dac_clk               1            1           0          0 0  
                    spi2.0-t2_clk             1            1           0          0 0  
                       spi2.0-t1_clk           1            1           0          0 0  
                          spi2.0-clktf_clk           1            1           0          0 0  
                             spi2.0-tx_sampl_clk           1            1           0          0 0  
                 spi2.0-r2_clk                0            0           0          0 0  
                    spi2.0-r1_clk             0            0           0          0 0  
                       spi2.0-clkrf_clk           0            0           0          0 0  
                          spi2.0-rx_sampl_clk           0            0           0          0 0  
        spi2.0-rx_refclk                      1            1    20000000          0 0  
           spi2.0-rx_rfpll_int                1            1           0          0 0  
              spi2.0-rx_rfpll                 1            1           0          0 0  
        spi2.0-tx_refclk                      1            1    40000000          0 0  
           spi2.0-tx_rfpll_int                1            1           0          0 0  
              spi2.0-tx_rfpll                 1            1           0          0 0  
     aux_ref_clk                              0            0    27000000          0 0  
     can1_mio                                 0            0           0          0 0  
     can0_mio                                 0            0           0          0 0  
    

    Liam

  • 0
    •  Analog Employees 
    on Mar 27, 2019 8:06 AM over 1 year ago in reply to lvb

    Hmm - this is really strange - 

    On boot everything works:

    [    1.641451] ad9361 spi2.0: ad9361_probe : AD936x Rev 2 successfu

    however later on (I guess when you userspace starts) it fails badly -

    [ 2.155509] ad9361 spi2.0: ad9361_bbpll_set_rate: Rate 1280000000 Hz Parent Rate 40000000 Hz
    [ 2.162024] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rate 10521254882 Hz
    [ 2.162056] ad9361 spi2.0: ad9361_clk_factor_set_rate: Rate 80000000 Hz Parent Rat

    Can it be that OSC starts and has a bad profile?

    Can you try to delete /home/analog/.osc_profile and /root/.osc_profile ?

    -Michael