IIO AD9234 decimation setting?


I am using an AD9234 (equal to AD9680) with 5G JESD lane rate and 500MHz sample clock in order to get 2 channels 500 MS sampling rate.

Today I tried the performance with faster signals. Until I reach a Frequency over 125MHz ervything looks fine and as expected. But using higher frequency, below the maximum sampling frequency of 250 MHz I got curious signal (or a wrong understanding of course).

Here is a 230MHz applied sinus signal. The fat looks got  but also shows lower frequencies.

The time signal of the 230MHz looks like not reaching the sampling rate:

What am I doing wrong? Do I have a decimation inside The ADC or the FPGA? 



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