iio:device0: SPI Read Verify failed (0x0) problem on custom carrier and ad9234 evaluation board

Hi,

I am trying to build a custom  design for the ad9234 evaluation board on a custom zynq-7000 carrier board. While going through hdl design and building my custom linux and devicetree I am now working on the SPI communication.

When I do "dmesg | grep spi" ig got the following output : iio iio:device0: SPI Read Verify failed (0x0) what might causing  this message?

I think I have a proper SPI communication, the signals looking good and I fixed an error where my linux read 0xCE it handled it as wrong device (this was because of the wrong devicetree driver settings for the ADC) But no I got the IIO error.

Here are the main parts devicetree I am using right now:

#include <dt-bindings/iio/frequency/ad9528.h>

/ {
	clocks {

	};
};

&fmc_spi {

	adc0_ad9234: ad9234@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "adi,ad9234";
			reg = <0>;
			spi-max-frequency = <1000000>;
			spi-cpol;
			spi-cpha;
			//adi,master-slave-2x-quirk;
			clocks = <&axi_ad9680_jesd_rx_axi>, <&clk0_ad9528 13>, <&clk0_ad9528 12>;
			clock-names = "jesd_adc_clk", "adc_clk", "adc_sysref";
	};

	clk0_ad9528: ad9528-1@1 {
		#address-cells = <1>;
		#size-cells = <0>;
		#clock-cells = <1>;
		compatible = "ad9528";

		spi-cpol;
		spi-cpha;
		spi-max-frequency = <10000000>;
		adi,spi-3wire-enable;
		reg = <1>;

		clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
		adi,vcxo-freq = <122880000>;

		adi,refa-enable;
		adi,refa-diff-rcv-enable;
		adi,refa-r-div = <1>;
		adi,osc-in-cmos-neg-inp-enable;

		/* PLL1 config */
		adi,pll1-feedback-div = <4>;
		adi,pll1-charge-pump-current-nA = <5000>;


		/* PLL2 config */
		adi,pll2-vco-div-m1 = <3>; /* use 5 for 184320000 output device clock */
		adi,pll2-n2-div = <10>; /* N / M1 */
		adi,pll2-r1-div = <1>;
		adi,pll2-charge-pump-current-nA = <805000>;

		/* SYSREF config */
		adi,sysref-src = <SYSREF_SRC_INTERNAL>;
		adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
		adi,sysref-k-div = <512>;
		adi,sysref-request-enable;
		adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
		adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;

		adi,rpole2 = <RPOLE2_900_OHM>;
		adi,rzero = <RZERO_1850_OHM>;
		adi,cpole1 = <CPOLE1_16_PF>;

		adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
		adi,status-mon-pin1-function-select = <7>; /* REFA Correct */

		ad9528_0_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "DEV_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <10>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_0_c1: channel@1 {
			reg = <1>;
			adi,extended-name = "FMC_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <10>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_0_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "DEV_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <10>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};

		ad9528_0_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "FMC_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <10>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};
	};
};

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Thu Oct 11 09:51:08 2018
 */


/ {
	amba_pl: amba_pl {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges ;
		
		axi_ad9680_dma: axi_dmac@7c400000 {
			compatible = "adi,axi-dmac-1.00.a";
			reg = <0x7c400000 0x1000>;

			#dma-cells = <1>;
			interrupts = <0 57 0>;
			clocks = <&clkc 16>;

			dma-channel {
				adi,source-bus-width = <64>;
				adi,destination-bus-width = <64>;
				adi,type = <0>;
			};
		};

		axi_ad9680_core: axi_ad9680@44a10000 {
			compatible = "xlnx,axi-ad9234-1.00.a";
			reg = <0x44a10000 0x10000>;
			dmas = <&axi_ad9680_dma 0>;
			dma-names = "rx";
			spibus-connected = <&adc0_ad9234>;
		};
		
		axi_ad9680_jesd_rx_axi: axi_jesd204_rx@44aa0000 {
			compatible = "adi,axi-jesd204-rx-1.0";
			reg = <0x44aa0000 0x4000>;

			interrupt-names = "irq";
			interrupt-parent = <&intc>;
			interrupts = <0 59 4>;
			

			clocks = <&clkc 16>, <&axi_ad9680_xcvr 1>, <&axi_ad9680_xcvr 0>;
			clock-names = "s_axi_aclk", "device_clk", "lane_clk";

			adi,octets-per-frame = <1>;
			adi,frames-per-multiframe = <32>;
			adi,converter-resolution = <12>;
			adi,bits-per-sample = <16>;
			adi,converters-per-device = <1>;

			#clock-cells = <0>;
			clock-output-names = "jesd_adc_lane_clk";
		};
		axi_ad9680_xcvr: axi_adxcvr@44a50000 {
			compatible = "adi,axi-adxcvr-1.0";
			reg = <0x44a50000 0x10000>;

			clocks = <&clk0_ad9528 1>;
			clock-names = "conv";

			#clock-cells = <1>;
			clock-output-names = "adc_gt_clk", "rx_out_clk";

			adi,sys-clk-select = <0>;
			adi,out-clk-select = <8>;
			adi,use-lpm-enable;
			adi,use-cpll-enable;
		};
	};
};

Thanks,

Nils

  • For Information, this is the whole dmesg output after booting the system:

    Booting Linux on physical CPU 0x0
    Linux version 4.9.0-xilinx-g7cf8748-dirty (nils@parallels-vm) (gcc version 5.4.0 20160609 (Ubuntu/Linaro 5.4.0-6ubuntu1~16.04.9) ) #3 SMP PREEMPT Wed Oct 10 10:28:34 CEST 2018
    CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d
    CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
    OF: fdt:Machine model: xlnx,zynq-7000
    bootconsole [earlycon0] enabled
    cma: Reserved 16 MiB at 0x3f000000
    Memory policy: Data cache writealloc
    On node 0 totalpages: 262144
    free_area_init_node: node 0, pgdat c092f400, node_mem_map ef7f7000
      Normal zone: 1536 pages used for memmap
      Normal zone: 0 pages reserved
      Normal zone: 196608 pages, LIFO batch:31
      HighMem zone: 65536 pages, LIFO batch:15
    percpu: Embedded 14 pages/cpu @ef7d1000 s25932 r8192 d23220 u57344
    pcpu-alloc: s25932 r8192 d23220 u57344 alloc=14*4096
    pcpu-alloc: [0] 0 [0] 1 
    Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 260608
    Kernel command line: console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlyprintk rootfstype=ext4 rootwait
    PID hash table entries: 4096 (order: 2, 16384 bytes)
    Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
    Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
    Memory: 1009116K/1048576K available (5120K kernel code, 192K rwdata, 1356K rodata, 1024K init, 214K bss, 23076K reserved, 16384K cma-reserved, 245760K highmem)
    Virtual kernel memory layout:
        vector  : 0xffff0000 - 0xffff1000   (   4 kB)
        fixmap  : 0xffc00000 - 0xfff00000   (3072 kB)
        vmalloc : 0xf0800000 - 0xff800000   ( 240 MB)
        lowmem  : 0xc0000000 - 0xf0000000   ( 768 MB)
        pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
        modules : 0xbf000000 - 0xbfe00000   (  14 MB)
          .text : 0xc0008000 - 0xc0600000   (6112 kB)
          .init : 0xc0800000 - 0xc0900000   (1024 kB)
          .data : 0xc0900000 - 0xc0930000   ( 192 kB)
           .bss : 0xc0930000 - 0xc0965a38   ( 215 kB)
    Preemptible hierarchical RCU implementation.
    	Build-time adjustment of leaf fanout to 32.
    	RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2.
    RCU: Adjusting geometry for rcu_fanout_leaf=32, nr_cpu_ids=2
    NR_IRQS:16 nr_irqs:16 16
    efuse mapped to f0801000
    slcr mapped to f0803000
    L2C: platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C: DT/platform modifies aux control register: 0x72360000 -> 0x72760000
    L2C-310 erratum 769419 enabled
    L2C-310 enabling early BRESP for Cortex-A9
    L2C-310 full line of zeros enabled for Cortex-A9
    L2C-310 ID prefetch enabled, offset 1 lines
    L2C-310 dynamic clock gating enabled, standby mode enabled
    L2C-310 cache controller enabled, 8 ways, 512 kB
    L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76760001
    zynq_clock_init: clkc starts at f0803100
    Zynq clock init
    sched_clock: 64 bits at 333MHz, resolution 3ns, wraps every 4398046511103ns
    clocksource: arm_global_timer: mask: 0xffffffffffffffff max_cycles: 0x4ce07af025, max_idle_ns: 440795209040 ns
    Switching to timer-based delay loop, resolution 3ns
    clocksource: ttc_clocksource: mask: 0xffff max_cycles: 0xffff, max_idle_ns: 537538477 ns
    timer #0 at f080b000, irq=17
    Console: colour dummy device 80x30
    Calibrating delay loop (skipped), value calculated using timer frequency.. 666.66 BogoMIPS (lpj=3333333)
    pid_max: default: 32768 minimum: 301
    Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
    Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
    CPU: Testing write buffer coherency: ok
    CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
    Setting up static identity map for 0x100000 - 0x100058
    CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
    Brought up 2 CPUs
    SMP: Total of 2 processors activated (1333.33 BogoMIPS).
    CPU: All CPU(s) started in SVC mode.
    devtmpfs: initialized
    VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
    clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
    pinctrl core: initialized pinctrl subsystem
    NET: Registered protocol family 16
    DMA: preallocated 256 KiB pool for atomic coherent allocations
    cpuidle: using governor menu
    hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers.
    hw-breakpoint: maximum watchpoint size is 4 bytes.
    zynq-ocm f800c000.ocmc: ZYNQ OCM pool: 256 KiB @ 0xf0880000
    zynq-pinctrl 700.pinctrl: zynq pinctrl initialized
    vgaarb: loaded
    SCSI subsystem initialized
    usbcore: registered new interface driver usbfs
    usbcore: registered new interface driver hub
    usbcore: registered new device driver usb
    pps_core: LinuxPPS API ver. 1 registered
    pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
    PTP clock support registered
    EDAC MC: Ver: 3.0.0
    FPGA manager framework
    fpga-region fpga-full: FPGA Region probed
    clocksource: Switched to clocksource arm_global_timer
    NET: Registered protocol family 2
    TCP established hash table entries: 8192 (order: 3, 32768 bytes)
    TCP bind hash table entries: 8192 (order: 4, 65536 bytes)
    TCP: Hash tables configured (established 8192 bind 8192)
    UDP hash table entries: 512 (order: 2, 16384 bytes)
    UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
    NET: Registered protocol family 1
    RPC: Registered named UNIX socket transport module.
    RPC: Registered udp transport module.
    RPC: Registered tcp transport module.
    RPC: Registered tcp NFSv4.1 backchannel transport module.
    PCI: CLS 0 bytes, default 64
    Trying to unpack rootfs image as initramfs...
    Freeing initrd memory: 4788K (dfb53000 - e0000000)
    hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available
    futex hash table entries: 512 (order: 3, 32768 bytes)
    workingset: timestamp_bits=30 max_order=18 bucket_order=0
    jffs2: version 2.2. (NAND) (SUMMARY)  © 2001-2006 Red Hat, Inc.
    bounce: pool size: 64 pages
    io scheduler noop registered
    io scheduler deadline registered
    io scheduler cfq registered (default)
    dma-pl330 f8003000.dmac: Loaded driver for PL330 DMAC-241330
    dma-pl330 f8003000.dmac: 	DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16
    e0000000.serial: ttyPS0 at MMIO 0xe0000000 (irq = 25, base_baud = 6249999) is a xuartps
    console [ttyPS0] enabled
    bootconsole [earlycon0] disabled
    [drm] Initialized
    brd: module loaded
    loop: module loaded
    libphy: Fixed MDIO Bus: probed
    libphy: MACB_mii_bus: probed
    macb e000b000.ethernet eth0: Cadence GEM rev 0x00020118 at 0xe000b000 irq 28 (00:0a:35:00:01:22)
    Marvell 88E1510 e000b000.etherne:00: attached PHY driver [Marvell 88E1510] (mii_bus:phy_addr=e000b000.etherne:00, irq=-1)
    e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
    e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
    ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
    ehci-pci: EHCI PCI platform driver
    usbcore: registered new interface driver usb-storage
    e0002000.usb supply vbus not found, using dummy regulator
    ULPI transceiver vendor/product ID 0x0424/0x0007
    Found SMSC USB3320 ULPI transceiver.
    ULPI integrity check: passed.
    ci_hdrc ci_hdrc.0: EHCI Host Controller
    ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
    ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
    hub 1-0:1.0: USB hub found
    hub 1-0:1.0: 1 port detected
    mousedev: PS/2 mouse device common for all mice
    i2c /dev entries driver
    cdns-wdt f8005000.watchdog: Xilinx Watchdog Timer at f0990000 with timeout 10s
    EDAC MC: ECC not enabled
    Xilinx Zynq CpuIdle Driver started
    sdhci: Secure Digital Host Controller Interface driver
    sdhci: Copyright(c) Pierre Ossman
    sdhci-pltfm: SDHCI platform and OF driver helper
    mmc0: SDHCI controller on e0100000.sdhci [e0100000.sdhci] using ADMA
    ledtrig-cpu: registered to indicate activity on CPUs
    usbcore: registered new interface driver usbhid
    usbhid: USB HID core driver
    spi1.1 supply vcc not found, using dummy regulator
    iio iio:device0: SPI Read Verify failed (0x0)
    ad9528: probe of spi1.1 failed with error -5
    fpga_manager fpga0: Xilinx Zynq FPGA Manager registered
    NET: Registered protocol family 10
    sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
    NET: Registered protocol family 17
    Registering SWP/SWPB emulation handler
    of_cfs_init
    mmc0: new high speed SDHC card at address 0001
    of_cfs_init: OK
    mmcblk0: mmc0:0001 SD16G 14.6 GiB 
    Freeing unused kernel memory: 1024K (c0800000 - c0900000)
     mmcblk0: p1 p2
    usb 1-1: new high-speed USB device number 2 using ci_hdrc
    EXT4-fs (mmcblk0p2): recovery complete
    EXT4-fs (mmcblk0p2): mounted filesystem with ordered data mode. Opts: (null)
    hub 1-1:1.0: USB hub found
    hub 1-1:1.0: 4 ports detected
    FAT-fs (mmcblk0p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
    random: dd: uninitialized urandom read (512 bytes read)
    IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready
    macb e000b000.ethernet eth0: link up (1000/Full)
    IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
    random: dropbearkey: uninitialized urandom read (32 bytes read)
    random: dropbearkey: uninitialized urandom read (32 bytes read)
    random: dropbearkey: uninitialized urandom read (32 bytes read)
    random: dropbear: uninitialized urandom read (32 bytes read)
    random: tcf-agent: uninitialized urandom read (16 bytes read)
    random: dropbear: uninitialized urandom read (32 bytes read)
    random: dropbear: uninitialized urandom read (32 bytes read)

  • +1
    •  Analog Employees 
    on Oct 15, 2018 6:37 AM over 2 years ago in reply to NilsMinor

    iio iio:device0: SPI Read Verify failed (0x0)
    ad9528: probe of spi1.1 failed with error -5

    This is caused by erroneous SPI communication. The driver writes a register inside the AD9528 and then tries to read it back.

    If the read value doesn't match the write, it generates this failure. Please make sure your SPI signals including the ChipSelect is properly connected and declared. It's beneficial to probe these signals close to the DUT.

    -Michael 

  • Hi Michael,

    The ad9528 was not conneted in my setup. I control it via USB as clock source. I only added it to the devicetree as information for the AD9234 I want to read out.

    When unplugging my AD9234-Eval board I get an other error () when plug it on again the error message is not seen anymore but the iio error comes. I thought the iio error is for my AD9234 not for the AD9528.

    First I want to controll the AD9234 so should I clear the ad9528 information from my devicetree? Or how to handle this?

    Thanks,

    - Nils

  • 0
    •  Analog Employees 
    on Oct 15, 2018 7:09 AM over 2 years ago in reply to NilsMinor

    The way things are setup is that the ADC requires a clock from the parent clock provider (AD9528). If this clock is not present, the ADC driver will return probing with error.

    -Michael

  • So also when a valid clock is applied, the the driver will check the SPI communication to the AD9528 and if not present or valid the error message occurs?

    So I need to handle correct communication also to the AD9528 eval?