AD9371 noOS driver error

Hi,

Can you please use these sources instead: https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371 ?
The TPL addresses are defined in this version (https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/parameters.h#L137).

Thanks,
Dragos

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/README#L46, 

cp ../../drivers/xilinx_platform/platform_drivers.c devices/adi_hal/

and there are no reference definition in 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/README#L46-L50. 

#include "delay.h"
#include "error.h"
#include "gpio.h"
#include "i2c.h"
#include "spi.h"

and finally, there is no definition for "SUCCESS" in drivers.c such as (axi_adc_core.c, axi_dac_core.c, and etc,)

thanks 

H.A. Hou

https://github.com/analogdevicesinc/no-OS/tree/update_readme/projects/ad9371/src

Thank you,

Antoniu

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L40

spi.flag in 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L44 

2. the definition is missing in clk_axi_clkgen.c

https://github.com/analogdevicesinc/no-OS/blob/master/projects/drivers/clk_axi_clkgen/clk_axi_clkgen.c#L162 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/drivers/clk_axi_clkgen/clk_axi_clkgen.c#L174 

after fix the above error, the binary file is generated. 

B. when running the binary file on the ZYNQ platform, it hands on the following messages

Please wait...

1. after more investigation, the SPI structure are quite different between 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/drivers/xilinx_platform/xilinx_platform_drivers.h

and 

https://github.com/analogdevicesinc/no-OS/blob/master/include/spi.h

1.1. spi_init_param

typedef struct spi_init_param {
	uint32_t	max_speed_hz;
	uint8_t		chip_select;
	enum spi_mode	mode;
	void		*extra;
} spi_init_param;

typedef struct xil_spi_init_param {
	enum spi_type	type;
	uint32_t	id;
	uint32_t	flags;
} xil_spi_init_param;

1.2. spi_desc

typedef struct spi_desc {
	uint32_t	max_speed_hz;
	uint8_t		chip_select;
	enum spi_mode	mode;
	void		*extra;
} spi_desc;

typedef struct xil_spi_desc {
	enum spi_type	type;
	uint32_t		id;
	uint32_t		flags;
#ifdef _XPARAMETERS_PS_H_
	XSpiPs_Config	*config;
	XSpiPs			instance;
#else
	XSpi			instance;
#endif
} xil_spi_desc;

2. access the member without initialization 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/drivers/xilinx_platform/spi.c#L82 

try to access the xli_param->flag  but param->extra does not be initialized in 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L30-L49 

int32_t platform_init(void)
{
	struct spi_init_param spi_param;
	int32_t status = 0;

	status = gpio_get(&gpio_ad9371_resetb, AD9371_RESET_B);
	status = gpio_get(&gpio_ad9528_resetb, AD9528_RESET_B);
	status = gpio_get(&gpio_ad9528_sysref_req, AD9528_SYSREF_REQ);

	spi_param.id = SPI_DEVICE_ID;
	spi_param.mode = SPI_MODE_0;
	spi_param.chip_select = AD9371_CS;
#ifndef ALTERA_PLATFORM
	spi_param.flags = SPI_CS_DECODE;
#endif
	status |= spi_init(&spi_ad_desc, &spi_param);

	return status;
}

in addition, spi_init_param has no members of id and flag as mentioned in the above. 

If possible, would you mind testing the code roughly before commit ? 

thanks 

H. A. Hou 

github.com/.../no-Os

Let me know if you encounter any other difficulties in doing the setup.

Regards,

Antoniu

in github.com/.../spi.chttps://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L49 SS_DECODE attribute is set. 

so the SPI configuration for AD9528 and AD9371 should be modified 

https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/app/myk_ad9528init.c#L6

static spiSettings_t clockSpiSettings =
{
        // 1, //chip select Index
        7, //chip select Index
        0, //Write bit polarity
        1, //16bit instruction word
        1, //MSB first
        0, //Clock phase
        0, //Clock polarity
        0,//uint8_t enSpiStreaming;
        1,//uint8_t autoIncAddrUp;
        1 //uint8_t fourWireMode;
};

and https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/app/myk.c#L486

static spiSettings_t mykSpiSettings =
{
    // 2, /* chip select index - valid 1~8 */
    6, /* chip select index - valid 1~8 */
    0, /* the level of the write bit of a SPI write instruction word, value is inverted for SPI read operation */
    1, /* 1 = 16-bit instruction word, 0 = 8-bit instruction word */
    1, /* 1 = MSBFirst, 0 = LSBFirst */
    0, /* clock phase, sets which clock edge the data updates (valid 0 or 1) */
    0, /* clock polarity 0 = clock starts low, 1 = clock starts high */
    0, /* Not implemented in ADIs platform layer. SW feature to improve SPI throughput */
    1, /* Not implemented in ADIs platform layer. For SPI Streaming, set address increment direction. 1= next addr = addr+1, 0:addr=addr-1 */
    1  /* 1: Use 4-wire SPI, 0: 3-wire SPI (SDIO pin is bidirectional). NOTE: ADI's FPGA platform always uses 4-wire mode */
};

to make noOS driver works. Tx transmits signal, Rx need to be check. 

Second, the output logs shows the ORx still failed to work 

Please wait...
rx_clkgen: MMCM-PLL locked (122880000 Hz)
tx_clkgen: MMCM-PLL locked (122880000 Hz)
rx_os_clkgen: MMCM-PLL locked (122880000 Hz)
MCS successful
CLKPLL locked
AD9371 ARM version 5.2.2
PLLs locked
Calibrations completed successfully
tx_adxcvr: OK (4915200 kHz)
rx_adxcvr: OK (4915200 kHz)
rx_os_adxcvr: OK (4915200 kHz)
rx_jesd status:
        Link is enabled
        Measured Link Clock: 122.882 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_jesd lane 0 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 75 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x47, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_jesd lane 1 status:
Errors: 0
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 1 Multi-frames and 73 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 4
        K: 32, M: 4, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x48, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_jesd status:
        Link is enabled
        Measured Link Clock: 122.882 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        SYNC~: deasserted
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd status:
        Link is enabled
        Measured Link Clock: 122.882 MHz
        Reported Link Clock: 122.880 MHz
        Lane rate: 4915.200 MHz
        Lane rate / 40: 122.880 MHz
        Link status: DATA
        SYSREF captured: Yes
        SYSREF alignment error: No
rx_os_jesd lane 0 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 9 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 0, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x43, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
rx_os_jesd lane 1 status:
Errors: 1
        CGS state: DATA
        Initial Frame Synchronization: Yes
        Lane Latency: 2 Multi-frames and 10 Octets
        Initial Lane Alignment Sequence: Yes
        DID: 0, BID: 0, LID: 1, L: 2, SCR: 1, F: 2
        K: 32, M: 2, N: 16, CS: 0, N': 16, S: 1, HD: 0
        FCHK: 0x44, CF: 0
        ADJCNT: 0, PHADJ: 0, ADJDIR: 0, JESDV: 1, SUBCLASS: 1
        FC: 4915200 kHz
tx_dac: Successfully initialized (245764160 Hz)
rx_adc: Successfully initialized (122882080 Hz)
Done

please help to solve ORx issue. 

Thanks 

H.A. Hou

Having the chip selects set to 6 and 7 is incorrect. Have a look at the HDL project (https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9371x/zc706/system_top.v#L306-L307):
   .spi0_csn_0_o (spi_csn_ad9528),
   .spi0_csn_1_o (spi_csn_ad9371),
For the AD9371 Transceiver Evaluation Software, the valid values for the generated profiles are 1~8, so our software must subtract 1 from those values. This is done in the CMB_SPIWriteByte() (https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L123) and CMB_SPIReadByte() (https://github.com/analogdevicesinc/no-OS/blob/master/projects/ad9371/src/devices/adi_hal/common.c#L152) functions.

Why do you say that ORx doesn't work? Some errors may be detected during the initialization phase (Errors: 1 - in your log), but that's not an issue as long as that number doesn't increase during the run time.

I've done a quick test using the current version of the no-OS and hdl master branches, but I didn't see issues.

Thanks,
Dragos