My ZCU102 board version is 1.1. Therefore I changed the HDL reference design according to https://www.xilinx.com/support/answers/71961.html. Then I generated the "system_top.hdf" file. After I added the necessary libraries and their paths to my XSDK project, I built it. It seems success. I followed the steps in guide. After click the run, I get the Hello message. Then I get the error message attached below. What is the problem caused?
rx_clkgen: MMCM-PLL NOT locked (122880000 Hz)
error: rx_clkgen: axi_clkgen_set_rate() failed
Thank in advance