I am using the following configuration:
I updated my kernel to:Talise API version: 22.214.171.124, with following new features:
I made a build of the latest software version for libiio, iiod, iio-oscilloscope on march 11.
When I use board1 to transmit a signal, and the board2 to receive. Each new boot with one of the EVM boards there is a different phase offset between Tx board1 and Rx board2.
The questions I have :
1. Can you transmit from Tx1 of both boards and measure the phase difference using network analyzer as mentioned in the user guide?
2. It is tested with an old package. New API added an enhancement feature for RF LO Sync.
From the release notes:
Could someone explain me how it is possible that previous version (UG1295) already contains RF LO Sync, when it is clear in the release notes (API 126.96.36.199) that this wasn't working in older versions...
In the older version, there was a bug which prevented MCS functionality for a few RF frequencies which uses fractional PLL. In the latest version that is corrected.
Can you check if all the clocks(SYSREF and REFCLK) are aligned at the FPGA input?
Have you tried configuring the clocks as mentioned in the below post:
I have measured with an oscilloscope. And the rising edge are alligned (measurment accuracy 200ps). Measure points:
Configuration of the PLL on the Evaluation board AD9528 :
How does the ADRV9009 use the sysref pulse? Edge or level?
If I look at below picture, I have the impression that the ADRV9009 alignment is done at a high levels not on the rising edge.
I have checked the duration of the sysref pulses on the evaluation board. Those have a period of 8,3 us with a duty cycle of 50%. So the alignment could happen anywhere on this high level. What is the difference when i don't use pulses and put a constant high level on the sysref? Or is this a bad configuration of the AD9528?
From UG-1295: It seems the SYSREF rising edge is used. If this is true, I don't need setup and hold times. But I need to know in which window the rising edge needs to occur of the SYSREF compare to REF_CLK. Does it need the 2ns delay as well?
But then I have a invalid SYSREF signal. (figure 3 ADRV9009 datasheet
1. You need to meet the timing requirement as specified in the datasheet.
2. Rf Phase sync syncronises the LO with respect to reference clock. If you reboot one board , as long as same reference goes to multiple boards they will retain the phase relation.
3. Yes , as long as same reference clock is given as Dev_Clk to ADRV9009 .
Vinod said:Rf Phase sync syncronises the LO with respect to reference clock. If you reboot one board , as long as same reference goes to multiple boards they will retain the phase relation.
Can I use this setup? Without an external SYSREF generator, and use the SYSREF generator on the ADRV900-W/PCBZ.
If this is true,can I make the following setup as well? And reboot on of the ZCU102 boards, and still have fix phase relation?