AD9361 device initialization error in no os driver

How to set the value for "GPIO_RESET_PIN " in parameter.h of no OS driver. I have set the value as '0' as i thought it is the reset signal for the AD9361.We use zed board with FMCOMMS2 board. When we run in hardware, it gave the error as "un supported product ID" while executing the  "ad9361_init(&ad9361_phy, &default_init_param);" command in main.c.

I have attached below the error message snapshot. 

Also how we have to map the GPIO pins  given in the following code of no OS driver(xgpiops.h) with that of the device in the board used(like zed board, picozed board )

-------------------------------------------------------------------------------------- 

#define XGPIOPS_BANK0 0 /**< GPIO Bank 0 */
#define XGPIOPS_BANK1 1 /**< GPIO Bank 1 */
#define XGPIOPS_BANK2 2 /**< GPIO Bank 2 */
#define XGPIOPS_BANK3 3 /**< GPIO Bank 3 */

#define XGPIOPS_MAX_BANKS 4 /**< Max banks in a GPIO device */
#define XGPIOPS_BANK_MAX_PINS 32 /**< Max pins in a GPIO bank */

#define XGPIOPS_DEVICE_MAX_PIN_NUM 118 /*< Max pins in the GPIO device
* 0 - 31, Bank 0
* 32 - 53, Bank 1
* 54 - 85, Bank 2
* 86 - 117, Bank 3
*/

----------------------------------------------------------------------------------------------------------

In zed board-FMcomms2 board, Ad9361 reset pin is connected to bank 35(pin number A16).

Thank you

SDKerrormessage.docx
  • Hi,

    You can get the desired GPIO_NO from the system_top.v file of the HDL project, but 54 has to added to that number (Zynq has 4 banks of GPIOs (32-bit, 22-bit, 32-bit, 32-bit): banks 0 and 1 are for the MIO pins (54) and banks 2 and 3 are for the EMIO pins (64)).

    For example, the index of gpio[46] (gpio_resetb) from system_top.v will be 100.

    In parameters.h, it is actually defined like this:

       #define GPIO_RESET_PIN 100

    so it's a unclear why you want to redefine it.

    Dragos

  • Thank you

    Now we understood the pin number. Initially we wanted to run the SDR setup, then we faced that device was not identified.So we thought the reset pin may be a issue so we  raised the question. 

    Initially we worked with one no-OS driver, where the the reset pin is defined as below

    #define GPIO_DEVICE_ID 0
    #define GPIO_RESET_PIN 0
    #define SPI_DEVICE_ID 0

    ---------------------------------------------------

    Then it worked but resulted in TX and RX tuning failed error.

    Then based on your advice, we used 2016 r2 drivers. Here, the reset pin is defined as100.

    What we understand is as given in system_top.v, we need to take the GPIO pin numbers. 

    What is your advice in using the zed-FMCOMMS2 HW setup for making our own communication link. We have our communication baseband modules readily available with us, we need to plug our TX signal samples to DAC of AD9361 and pass AD9361 ADC data to our base band modules. 

    What are the references we need to be familiar and in what order -  to understand the no-OS and HDL driver and customize to our requirements fast. Initially we made our own analog chain and the data link is ready with IF stage. Now we want to use AD9361 for configurability and to tune for RF frequency range

    Thank you.

  • Hi,

    First, try to send our data: only enable XILINX_PLATFORM and DAC_DMA. Do you see any data on the TX port?

    Thanks,

    Dragos

  • Did you enable the CYCLIC flag for the TX DMA?

    Thanks,

    Dragos

  • We have gone through some of the documents in the wiki.

    Because the drivers are not having comments, it is difficult to understand.

    Please clarify the following

    1) We programmed the HDL and no-Os drivers given in the web site, The device was successfully initialized and no Rx/TX tuning failing. Then we thought of sending a sine signal to DAC and see the generated sine signal in the TX o/p port. We used the DAC_init and DAC_write functions to write sine LUT samples to DAC, But no signal is generated at TX o/p. How we can send our test signal 

    The code we used for sending sine signal to DAC  is given below

    -------------------------------------------------------------------

    dac_init(ad9361_phy, DATA_SEL_DMA, 1);

    while(1)
     {
    for(i3=1; i3<129;i3++)
    {
    i4 = sine_lut1[i3];
    i1 = i3;
    i2 = i4;
    dac_write(ad9361_phy, i1, i2);
    } //for loop end

    } //for while loop

    ---------------------------------------------------------------------------

    Please clarify how we can give test signal to DAC

    Since the HDL and no-OS drivers are not having comments, it is very difficult to understand

    the code flow and to select which functions/codes are appropriate  to us.

    2. Kindly guide us the flow for sending test signal to DAC  and read the RXD signal ADC

    Thank you

  • We did the setting as you suggested. No data at the TX o/p of FMCOMMS2

    we defined the DAC_DMA in main.c as given below(it is not defined anywhere in the .h or .c files)

    -------------------------------------------

    #define DAC_DMA  1

    -------------------------------------------

    We changed the RX & TX synthesizer freq to 70MHz instead of 2.4GHz so that  we can view the signal in oscilloscope.

    What other settings are required.

    What way you suggest for our work.

    In HDL driver side, whether we can customize to our requirement your drivers or writing our own code for AD9361 which will be better for our work(since our baseband(HDL) modules are ready for both TXR and RXR). We have to configure the AD9361 and interface our TX and RX modules  with AD9361.

    For customizing HDL drivers we are not clear on how to remove many other modules like HDMI, audio etc

    Thank you

  • dac_dma_read/write() can be used only for accessing the DMA registers. Take dac_init() as an example: no-OS/dac_core.c at master · analogdevicesinc/no-OS · GitHub - the data should be written in memory directly using Xil_Out().

    Dragos

  • Please do a test using our latest master branches for HDL and no-OS. On the software side, only enable XILINX_PLATFORM and DAC_DMA in config.h - it's something that works on our side.

    Dragos