Zynq-7010(ZYBO board), (SSM2603 + i2s-axi + pl330 DMA), recording issues.

Dear community,

I trying to implement linux sound device driver for Diligent ZYBO rev. B3 board based on Zynq-7010 + SSM2603 codec (connected to PL as slave, scheme is shown in system.pdf, I've only added 1 bit in CTRL reg for MUTE signal, other logic is the same as at Analog Devices github).

Adopted driver succesfully probed & bound:

zybo-ssm2603-snd zybo_ssm2603_snd: ssm2602-hifi <-> 43c00000.axi-i2s mapping ok

Source code (rewritten from Zed board) and patch on top of xcomm_zynq branch is provided (zybo_ssm2603.c attached separatly).

Playback works fine, but capture behave strange, instead of sound I heard only short beep (sound like after jack insertion in mic port) then digital silince (ssm2603_441kHz_cap.wav):

#arecord -D default:CARD=SSM2603 -r 44100 ssm2603_441kHz_cap.wav --dump-hw

Recording WAVE '/mnt/sdcard/ssm2603_cap.wav' : Unsigned 8 bit, Rate 44100 Hz, Mono

HW Params of device "default:CARD=SSM2603":

-------------------setsysclk ret: 0-

ACCESS:  MMAP_INTERLEAVED MMAP_NONINTERLEAVED MMAP_COMPLEX RW_INTERLEAVED RW_NONINTERLEAVED

FORMAT:  S8 U8 S16_LE S16_BE U16_LE U16_BE S24_LE S24_BE U24_LE U24_BE S32_LE S32_BE U32_LE U32_BE MU_LAW A_LAW I

MA_ADPCM S24_3LE S24_3BE U24_3LE U24_3BE S20_3LE S20_3BE U20_3LE U20_3BE S18_3LE S18_3BE U18_3LE U18_3BE

SUBFORMAT:  STD

SAMPLE_BITS: [4 32]

FRAME_BITS: [4 320000]

CHANNELS: [1 10000]

RATE: [4000 4294967295)

PERIOD_TIME: (666 4096000]

PERIOD_SIZE: (2 4294967295)

PERIOD_BYTES: (1 4294967295)

PERIODS: (0 2147483647)

BUFFER_TIME: [1 4294967295]

BUFFER_SIZE: [5 4294967294]

BUFFER_BYTES: [3 4294967295]

TICK_TIME: ALL

--------------------

^CAborted by signal Interrupt...

arecord: pcm_read:2032: read error: Interrupted system call

I have tried different setups of alsamixers, check reg dump and compare with working ~baremetall~ program, everything look like codec driver works fine.

Q:

1) What should I check to make capture channel work?

Previously I tried to do the same on Xilinx kernel and got unstable work look like because of DMA.

2) Why in zybo_ssm2603_hw_params routine I recive only capable with 12.288 Mhz frequences, while I am asking `arecord` or `aplay` for 44.1kHz

Any suggestions are welcom,

Thansk in advance.

attachments.zip
  • Hi,

    1) The general setup looks good. Can you have a look at the SDATA_I line, either using a scope on the physical traces of the board or chipscope inside the FPGA, and see whether it matches the data in the wav file or not. This should help to narrow down the issue.

    2) The rates are derived from the reference clock. If that is e.g. 12.288 MHz in your case your samplerates will be based on that. You could try to change the driver to automatically change the reference clock when a 44.1kHz based samplerate is selected.

    - Lars