I am trying to understand the effects of the bit fields in registers 6 and 7 for the AD9361 device. In other words, the reference manual says that when both of these bit fields are equal the data and clock signals are lined up. What is the purpose of providing 2 bit fields for this? Why not just have 1 bit field with a delay 0-15?
Another thing I have considered is that the combination [0,M] provide a delay with magnitude M and [M,0] provides a delay with magnitude -M? If this were the case why not just have 1 bit field with twice the range (i.e. a 5 bit, 2's complement bit field).
My questions stem from the digital tuning function in the no-os software and why it only loops over the clk delay while keeping data delay constant and vice versa. Why not consider all permutations, or consider a 32 result vector in the case of the idea expressed in the 2nd paragraph).
Maybe I would understand better if someone could give me the total delay based on the situations in the chart below.
I have been meaning to add some more documentation to:
I will start with the mode you are using. Which is it? (LVDS)?
Which CMOS mode?
I added more information here: