AD7768-1 register access works but ADC data acquisition not working using Zedboard, hdl & linux drivers

I have a hardware setup using an EVAL-AD7768-1FMCZ on a Zedboard carrier, that I am trying to use to acquire ADC data from the AD7768-1 device.  For the SD card image I built the following items and assembled them together in the relevant location on the boot partition:

  • Used the 2019_R1-2019_12_20.img from the wiki
  • from the hdl_2019_r1 branch on the hdl repo, I build the system_top.hdf/bit stream files from the ad77681evb/zed project.
  • Built the boot.bin file from the hdl outputs, using the uboot.elf from the 2019_R1-2019_12_20.img boot partition using the build boot script
  • created a zynq-zed-adv7511-ad77681.dts (should be attached to issue) and compiled to a dtb, based on the AD7768-1 bindings and other devices that use the spi engine present in the HDL image

When I boot the board I'm able to see the AD7768-1 device, channels, attributes etc in the output from iio_info, but there is a timeout error (-110) for reading the raw value. 

        iio:device0: ad7768-1 (buffer capable)

                1 channels found:

                        voltage0:  (input, index: 0, format: be:u24/32>>8)

                        2 channel-specific attributes found:

                                attr  0: raw ERROR: Connection timed out (-110)

.....

Current trigger: trigger0(ad7768-1-dev0)

The ad7768-1-dev0 trigger is shown as assigned to the AD7768-1, but later in the iio_info output, the trigger is shown as having no channels - not sure if this is correct or not, no additional configuration of the trigger is mentioned on the ad7768-1 linux wiki page.

...snip...

        trigger0: ad7768-1-dev0

                0 channels found:

I am able to read/write the registers over the SPI interface using the register access feature in IIO Scope.  I can also see a pulse train from the AD7768-1 DRDYB signal at the default sample rate of 32000, but when I try to acquire samples in IIO Scope, I do not get any data back or displayed, and don't see any SPI reads in response to the DRDYB signal.

I've checked the HDL project, and it looks like the FPGA to eval board FMC to AD7768-1 pin mapping for DRDY is correct, so the signal should be getting to the FPGA and into the trigger of the spi_engine. 

- Is there some additional configuration at IIO level or devicetree setup required to properly enable the acquisition of samples for the AD7768-1?

I've also noticed that i can changed the sample rate attribute in IIO scope, to one of the menu values, and for the first couple of times, the DRDYB pulse frequency changes to match the sample rate that is set.  However, after writing a new sampling_frequency a few times, the DRDYB pulses stop, and don't restart until I set SPI_STARTB (bit 7) in the SYNC_RESETB register to '0' to software initiate a SYNC_OUTB pulse that drives the SYNC_INB pin. A pulse on SYNC_INB is required after device configuration changes.  Looking at the Linux driver, the ad7768_set_freq(..) doesn't write the AD7768_REG_SYNC_RESET register, which suggests that the hardware SYNC_OUTB has stopped at some point as well.

- Is writing to the SYNC_RESETB register something the driver should do after a config change, or is there something that needs to be enabled in the HDL/device tree to avoid this issue?

Thanks now,

Michael.

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