I'm currently adapting a design to a different FPGA carrier platform which uses the AD9467 and two DMAC cores to transmit different pre-processed data blocks to the DDR.A connected system uses libiio and therefore the iio kernel driver on the linux side for interfacing the device and the two DMA controllers. However, at the moment I have the problem that only one of the two DMA controllers seems to be handled correctly by the linux driver at the same time. I habe monitored the DMAC registers using the kernel debugFS and the functioning controller transmits data in the correct way. The second controller however receives the SAME destination address (register 0x410) as the first controller and no interrupt handling in the 0x8X registers is visible. If I use iio_readdev on that device a timeout is produced.
Do I miss something what has changed in the last year? The old design was based on the Analog HDL library 2018_R1 and Analog Linux kernel 2018_R1 with Vivado 2018.3. The updated design uses the HDL library 2019_R1 and linux kernel 2019_R1 with Vivado 2019.1. The whole design works so far (data looks as expected), but only one DMAC can be read by iio at the moment (and it randomly changes from synthesis to synthesis...).
I'm looking further into this issue. I do not know if the address in register 0x410 or 0x434 is really responsible for this issue. However, I see perfectly fine interrupt handling on the register 0x84 and 0x88 for the first device but no interrupt handling (at least according to 0x84 and 0x88) for the second DMA device. Both DMAs are sending data according to cat /proc/interrupts and the DMA transfer debug register.
what are the base addresses of the two DMACs ?
Also make sure in the device tree you set the interrupt sensitivity to high.
Base addresses are 0x8400_0000 and 0x8402_0000. I'm using GP1 instead of GP0 because there is MIG controller connected to GP0 and using the whole address space from 0x4000_0000 to 0x7FF_FFFF.
The interrupt sensitivity is high. Acutally this is correctly infered by Vivado and automatically set in the pl.dtsi.
This looks more like a driver issue than a hdl problem.
Sergiu or DragosB please could you have a look.
Can you post the device-tree for the 2 DMACs?