Multiple DMAC controllers use the same destination address


I'm currently adapting a design to a different FPGA carrier platform which uses the AD9467 and two DMAC cores to transmit different pre-processed data blocks to the DDR.A connected system uses libiio and therefore the iio kernel driver on the linux side for interfacing the device and the two DMA controllers. However, at the moment I have the problem that only one of the two DMA controllers seems to be handled correctly by the linux driver at the same time. I habe monitored the DMAC registers using the kernel debugFS and the functioning controller transmits data in the correct way. The second controller however receives the SAME destination address (register 0x410) as the first controller and no interrupt handling in the 0x8X registers is visible. If I use iio_readdev on that device a timeout is produced.

Do I miss something what has changed in the last year? The old design was based on the Analog HDL library 2018_R1 and Analog Linux kernel 2018_R1 with Vivado 2018.3. The updated design uses the HDL library 2019_R1 and linux kernel 2019_R1 with Vivado 2019.1. The whole design works so far (data looks as expected), but only one DMAC can be read by iio at the moment (and it randomly changes from synthesis to synthesis...).

Best regards,