We have ADRV9361-Z7035 evaluation board, We have 40 MHz TCXO with higher stability , which has 3.3 V Vdd , I am new to FPGA world, Is it possible to replace 40 MHz rakon TCXO(which is used with 1.8 V Vdd) given in the default ADRV9361-Z7035 evaluation board by our 40 MHz TCXO , which has 3.3 V Vdd and we want enable of TCXO from bank 34 same as given in ADRV9361-Z7035 board.
similarly, at 33.33 MHz for PS clock, we want to replace 33.33 MEMS clock oscillator given in ADRV9361-Z7035 by 3.3 V Vdd 33.33 MHz TCXO, which has higher stability . As in evaluation board, 33.33 MHz oscillator has given Vdd from VCCPCOM-1P8V. We want minimal changes in evaluation board as our agenda is only to change TCXO (which has 3.3 V Vdd instead of 1.8 V Vdd)?
Which is the better idea, whether to use level translator or Change Vdd from different bank?
In my view Changing VDD should be the easier option.
Moving this post to Linux SW driver forum , as this board was developed by the team there.
Thank you for your response.
for 40 MHz TCXO, from bank 34 , rakon TCXO enabled through IO_00_34_AD9361_CLKSEL( this bank voltage range is 1.2-1.8 V), one option is to remove LDO (which is used for rakon TCXO ADM7160) , and provide direct 3.3 V to our TCXO , which can be enabled through bank 34 (IO_00_34_AD9361_CLKSEL)(1.2-1.8 V)?
Can you please give us a part number of the TCXO you want yo use?
We are planning to use sit5156 sitime TCXO, with 3.3 V vdd
You can replace the TCXO but you have to make sure that the output voltage of the new one doesn't exceed 1.3 VP-P.
Also if you use a 3.3 V oscillator you need to remove R54 and drive IO_00_34_AD9361_CLKSEL to 1 logic.
Can you please guide similar for the 33.33 MHz clock oscillator used in evaluation board, if we want to use 3.3 V TCXO for FPGA PS clock, we have to apply 3.3 V to 33.33 MHz TCXO Vdd instead of VCCPCOM_1P8V? how to replace , please guide.