Initialize problem of ADRV9008 Ev board with Arria10 SoC (ARM Linux)

1. We have HW configuration that includes:

- Achilles card with Altera Arria-10 SoC (Reflex company) (mother board)
- ADRV9008-1 Evaluation board (doter board)

2. We prepared ADRV9008 firmware package based on reference design "no-OS/projects/adrv9009"
copied from (at 05 March 2019)
We little bit changed this package. List of the changes:

- The SPI lowest layer driver is used from Altera HAL
- ADIHAL_wait_us() uses alt_busy_sleep() (Altera HAL function)
- mdelay(), based on alt_busy_sleep()
- GPO signals for reset ADRV9008 and AD9528

3. We successfully incorporated ADRV9008 firmware package with our
project with following configuration details (relevant only)

- ARM (Arria-10 SoC) is not in use
- Microprocessor Nios II is used - Altera FPGA IP, Frequency 192 MHz
- SPI - Altera FPGA IP

The project runs on the target (Nios) and ADRV9008 initialization (headless.c/main) is successful.

4. On the next step we migrate this project to ARM (Arria10 SoC) running Linux.

We left the same - SPI (Altera FPGA IP), with the same driver.
The other changes are minor:

- Replace lowest layer of Memory Mapped register access (SPI registers, GPIO etc.)
to mmap() Linux API.
- ADIHAL_wait_us() uses usleep() Linux API.
- mdelay(), uses usleep().

5. In this new project (Arria 10 ARM) we encountered to the following problem.

ERROR: 97: LoadHex() line checksum is invalid
error: TALISE_loadArmFromBinary() failed


a) My additional debugging printf added before "Error: 97" point of code (function TALISE_verifyArmCheckSum)

shows :  buildTimeChecksum=0, calculatedChecksum=0xffffffff

b) We compared several times the new (Arm) and the old (Nios) projects (including firmware folder with ARM's programming code).
The differences are as mentioned above, very minor.
c) We run the new and old projects on the same physical card (Achilles+ADRV9008 Ev. board).

Please help to find the problem.