Hi All,
We are working on custom board which is based on zynqMP. We are using latest 2018.R3 repos.
I have seen that ad9371 is not probed well because of some issues which are mentioned below:
[ 9.132030] axi_adxcvr 84a50000.axi_ad9371_rx_os_xcvr: RX Error: 0[ 9.138209] ad9371 spi1.0: jesd_rx_os_clk enable failed (-5)[ 9.927736] random: crng init done[ 10.871431] WARNING: 239: Clock PLL Lock event timed out in MYKONOS_waitForEvent()[ 10.878994] ad9371 spi1.0: Clock PLL Lock event timed out in MYKONOS_waitForEvent()[ 10.878994] (239)[ 10.888658] ad9371: probe of spi1.0 failed with error -14.
Inside the driver code (ad9371.c), have caught the code snippet which is throwing this error:
if (has_obs_and_en(phy)) { ret = clk_prepare_enable(phy->jesd_rx_os_clk); if (ret < 0) { dev_err(&phy->spi->dev, "jesd_rx_os_clk enable failed (%d)", ret); goto out_disable_rx_clk; } }
pl..dtsi
/* * CAUTION: This file is automatically generated by Xilinx. * Version: * Today is: Wed Jul 31 06:06:43 2019 */ / { amba_pl: amba_pl@0 { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi: axi_jesd204_rx_os_jesd@84ab0000 { clock-names = "s_axi_aclk", "core_clk"; clocks = <&clk 71>, <&misc_clk_0>; compatible = "xlnx,axi-jesd204-rx-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 104 4>; reg = <0x0 0x84ab0000 0x0 0x4000>; }; misc_clk_0: misc_clk_0 { #clock-cells = <0>; clock-frequency = <100000000>; compatible = "fixed-clock"; }; AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi: axi_jesd204_rx@84aa0000 { clock-names = "s_axi_aclk", "core_clk"; clocks = <&clk 71>, <&misc_clk_0>; compatible = "xlnx,axi-jesd204-rx-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 106 4>; reg = <0x0 0x84aa0000 0x0 0x4000>; }; AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi: axi_jesd204_tx@84a90000 { clock-names = "s_axi_aclk", "core_clk"; clocks = <&clk 71>, <&misc_clk_0>; compatible = "xlnx,axi-jesd204-tx-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 105 4>; reg = <0x0 0x84a90000 0x0 0x4000>; }; AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr: axi_ad9371_rx_os_xcvr@84a50000 { clock-names = "s_axi_aclk"; clocks = <&clk 71>; compatible = "xlnx,axi-adxcvr-1.0"; reg = <0x0 0x84a50000 0x0 0x10000>; }; AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr: axi_ad9371_rx_xcvr@84a60000 { clock-names = "s_axi_aclk"; clocks = <&clk 71>; compatible = "xlnx,axi-adxcvr-1.0"; reg = <0x0 0x84a60000 0x0 0x10000>; }; AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr: axi_ad9371_tx_xcvr@84a80000 { clock-names = "s_axi_aclk"; clocks = <&clk 71>; compatible = "xlnx,axi-adxcvr-1.0"; reg = <0x0 0x84a80000 0x0 0x10000>; }; AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_clkgen: axi_ad9371_rx_clkgen@83c10000 { clock-names = "clk", "s_axi_aclk"; clocks = <&misc_clk_1>, <&clk 71>; compatible = "xlnx,axi-clkgen-1.0"; reg = <0x0 0x83c10000 0x0 0x10000>; }; misc_clk_1: misc_clk_1 { #clock-cells = <0>; clock-frequency = <100000000>; compatible = "fixed-clock"; }; AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_os_clkgen: axi_ad9371_rx_os_clkgen@83c20000 { clock-names = "clk", "s_axi_aclk"; clocks = <&misc_clk_1>, <&clk 71>; compatible = "xlnx,axi-clkgen-1.0"; reg = <0x0 0x83c20000 0x0 0x10000>; }; AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen: axi_ad9371_tx_clkgen@83c00000 { clock-names = "clk", "s_axi_aclk"; clocks = <&misc_clk_1>, <&clk 71>; compatible = "xlnx,axi-clkgen-1.0"; reg = <0x0 0x83c00000 0x0 0x10000>; }; AD9371_TOP_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core: ad_ip_jesd204_tpl_adc@84a00000 { clock-names = "link_clk", "s_axi_aclk"; clocks = <&misc_clk_0>, <&clk 71>; compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0"; reg = <0x0 0x84a00000 0x0 0x1000>; }; AD9371_TOP_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core: ad_ip_jesd204_tpl_adc_rx_os@84a08000 { clock-names = "link_clk", "s_axi_aclk"; clocks = <&misc_clk_0>, <&clk 71>; compatible = "xlnx,ad-ip-jesd204-tpl-adc-1.0"; reg = <0x0 0x84a08000 0x0 0x1000>; }; AD9371_TOP_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core: ad_ip_jesd204_tpl_dac_tx@84a04000 { clock-names = "link_clk", "s_axi_aclk"; clocks = <&misc_clk_0>, <&clk 71>; compatible = "xlnx,ad-ip-jesd204-tpl-dac-1.0"; reg = <0x0 0x84a04000 0x0 0x1000>; }; AXI_AD_DMA_TOP_axi_ad9371_rx_dma: axi_ad9371_rx_dma@9c400000 { clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk"; clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>; compatible = "xlnx,axi-dmac-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 109 4>; reg = <0x0 0x9c400000 0x0 0x1000>; }; AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma: axi_ad9371_rx_os_dma@9c440000 { clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk"; clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>; compatible = "xlnx,axi-dmac-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 107 4>; reg = <0x0 0x9c440000 0x0 0x1000>; }; AXI_AD_DMA_TOP_axi_ad9371_tx_dma: axi_ad9371_tx_dma@9c420000 { clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk"; clocks = <&clk 71>, <&clk 72>, <&clk 72>; compatible = "xlnx,axi-dmac-1.0"; interrupt-names = "irq"; interrupt-parent = <&gic>; interrupts = <0 108 4>; reg = <0x0 0x9c420000 0x0 0x1000>; }; psu_ctrl_ipi: PERIPHERAL@ff380000 { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0x0 0xff380000 0x0 0x80000>; }; psu_message_buffers: PERIPHERAL@ff990000 { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0x0 0xff990000 0x0 0x10000>; }; }; };
system-user.dtsi
/include/ "system-conf.dtsi" / { chosen { bootargs = "earlycon clk_ignore_unused root=/dev/mmcblk0p2 rw rootwait uio_pdrv_genirq.of_id=generic-uio loglevel=7"; stdout-path = "serial0:115200n8"; }; }; &dwc3_0 { status = "okay"; dr_mode = "host"; maximum-speed = "super-speed"; snps,usb3_lpm_capable; phy-names = "usb3-phy"; phys = <&lane2 0x4 0x0 0x3 0x18CBA80>; }; &pinctrl0 { pini2c0def:i2c0-default { mux { groups = "i2c0_9_grp"; function = "i2c0"; }; conf { groups = "i2c0_9_grp"; bias-pull-up; slew-rate = <0x1>; io-standard = <0x0>; }; }; pini2c0gp:i2c0-gpio { mux { groups = "gpio0_38_grp", "gpio0_39_grp"; function = "gpio0"; }; conf { groups = "gpio0_38_grp", "gpio0_39_grp"; slew-rate = <0x1>; io-standard = <0x0>; }; }; pini2c1def:i2c1-default { mux { groups = "i2c1_10_grp"; function = "i2c1"; }; conf { groups = "i2c1_10_grp"; bias-pull-up; slew-rate = <0x1>; io-standard = <0x0>; }; }; pini2c1gp:i2c1-gpio { mux { groups = "gpio0_40_grp", "gpio0_41_grp"; function = "gpio0"; }; conf { groups = "gpio0_40_grp", "gpio0_41_grp"; slew-rate = <0x1>; io-standard = <0x0>; }; }; pinuart0def:uart0-default { mux { groups = "uart0_10_grp"; function = "uart0"; }; conf { groups = "uart0_10_grp"; slew-rate = <0x1>; io-standard = <0x0>; }; conf-rx { pins = "MIO42"; bias-high-impedance; }; conf-tx { pins = "MIO43"; bias-disable; }; }; pinuart1def:uart1-default { mux { groups = "uart1_11_grp"; function = "uart1"; }; conf { groups = "uart1_11_grp"; slew-rate = <0x1>; io-standard = <0x0>; }; conf-rx { pins = "MIO45"; bias-high-impedance; }; conf-tx { pins = "MIO44"; bias-disable; }; }; pingem1def:gem1-default { mux-mdio { function = "mdio1"; groups = "mdio1_0_grp"; }; conf-mdio { groups = "mdio1_0_grp"; slew-rate = <0x1>; io-standard = <0x0>; bias-disable; }; }; pingem2def:gem2-default { mux-mdio { function = "mdio2"; groups = "mdio1_1_grp"; }; conf-mdio { groups = "mdio1_1_grp"; slew-rate = <0x1>; io-standard = <0x0>; bias-disable; }; }; pinsdhci:sdhci0-default { mux { groups = "sdio0_0_grp"; function = "sdio0"; }; conf { groups = "sdio0_0_grp"; slew-rate = <0x1>; io-standard = <0x0>; bias-disable; }; }; pingpio:gpio-default { mux-sw { function = "gpio0"; groups = "gpio0_74_grp", "gpio0_75_grp"; }; conf-sw { groups = "gpio0_74_grp", "gpio0_75_grp"; slew-rate = <0x1>; io-standard = <0>; }; conf-pull-up { pins = "MIO74", "MIO75"; bias-pull-up; }; conf-pull-none { pins = "MIO64", "MIO65"; bias-disable; }; }; pinctrl_usb0_default: usb0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0x1>; io-standard = <0>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; pinctrl_qspi0_default: qspi0-default { mux { groups = "usb0_0_grp"; function = "usb0"; }; conf { groups = "usb0_0_grp"; slew-rate = <0x1>; io-standard = <0>; }; conf-rx { pins = "MIO52", "MIO53", "MIO55"; bias-high-impedance; }; conf-tx { pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59", "MIO60", "MIO61", "MIO62", "MIO63"; bias-disable; }; }; }; &gpio{ pinctrl-names = "default"; pinctrl-0 = <&pingpio>; }; &i2c0 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pini2c0def>; pinctrl-1 = <&pini2c0gp>; scl-gpios = <&gpio 0x26 0x0>; sda-gpios = <&gpio 0x27 0x0>; EEPROM:eeprom@50 { compatible = "at,24c256"; reg = <0x50>; #address-cells = <0x1>; #size-cells = <0x1>; board_sn@0 { reg = <0x0 0x14>; }; eth_mac@20 { reg = <0x20 0x6>; }; board_name@d0 { reg = <0xd0 0x6>; }; board_revision@e0 { reg = <0xe0 0x3>; }; }; RTC:rtc@68 { compatible = "dallas,ds1340"; reg = <0x68>; }; FPGATEMP:fpgaTemp@4C { compatible = "adt7461"; reg = <0x4C>; }; i2cswitch@71 { compatible = "nxp,pca9546"; #address-cells = <0x1>; #size-cells = <0x0>; reg = <0x71>; RFM1@0{ #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x0>; }; RFM2@1{ #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x1>; }; PSB@2{ #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x2>; }; hotspot:hotspot@48 { #address-cells = <0x1>; #size-cells = <0x0>; compatible = "ti,tmp112"; reg = <0x48>; }; }; }; &i2c1 { pinctrl-names = "default", "gpio"; pinctrl-0 = <&pini2c1def>; pinctrl-1 = <&pini2c1gp>; scl-gpios = <&gpio 0x28 0x0>; sda-gpios = <&gpio 0x29 0x0>; ina226_1@40 { compatible = "ti,ina226"; reg = <0x40>; #address-cells = <0x1>; #size-cells = <0x0>; shunt-resistor = <0x7d0>; }; ina226_2@41 { compatible = "ti,ina226"; #address-cells = <0x1>; #size-cells = <0x0>; reg = <0x41>; shunt-resistor = <0x1388>; }; ina226_3@44 { compatible = "ti,ina226"; reg = <0x44>; shunt-resistor = <0x1388>; }; ina226_4@45 { compatible = "ti,ina226"; reg = <0x45>; shunt-resistor = <0x1388>; }; i2cswitch@70 { compatible = "nxp,pca9546"; #address-cells = <0x1>; #size-cells = <0x0>; reg = <0x70>; SFP_1:SFP0@0{ #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x0>; }; SFP_2:SFP1@1{ #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x1>; }; SFP_3:SFP2@2 { #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x2>; }; SFP_4:SFP3@3 { #address-cells = <0x1>; #size-cells = <0x0>; compatible = "xxx"; reg = <0x3>; }; }; }; &sdhci0 { pinctrl-names = "default"; pinctrl-0 = <&pinsdhci>; /* broken-mmc-highspeed; */ no-1-8-v; broken-cd; }; &spi1 { spidev1: cpld@0 { #address-cells = <0x1>; #size-cells = <0x0>; #clock-cells = <0x1>; compatible = "spidev"; reg = <0x0>; spi-max-frequency = <0x989680>; }; }; &spi0 { clk0_ad9528: ad9528-1@2 { #address-cells = <0x1>; #size-cells = <0x0>; #clock-cells = <0x1>; compatible = "adi,ad9528"; reg = <0x2>; spi-max-frequency = <0x989680>; clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13"; adi,vcxo-freq = <0x7530000>; adi,refb-enable; adi,refb-r-div = <0x1>; /*adi,refa-cmos-neg-inp-enable;*/ adi,ref-mode = <0x3>; /*adi,osc-in-cmos-neg-inp-enable;*/ adi,pll1-feedback-div = <0x8>; /*adi,pll1-feedback-src-vcxo = <0x1>;*/ adi,pll1-charge-pump-current-nA = <0x1388>; adi,pll2-vco-div-m1 = <0x3>; adi,pll2-n2-div = <0xa>; adi,pll2-r1-div = <0x1>; adi,pll2-charge-pump-current-nA = <0xc4888>; adi,sysref-src = <0x2>; adi,sysref-pattern-mode = <0x1>; adi,sysref-k-div = <2000>; /*adi,sysref-request-enable; see this */ adi,sysref-nshot-mode = <0x3>; adi,sysref-request-trigger-mode = <0x3>; adi,rpole2 = <0x0>; adi,rzero = <0x2>; adi,cpole1 = <0x2>; adi,status-mon-pin0-function-select = <0x1>; adi,status-mon-pin1-function-select = <0x7>; reset-gpios = <&gpio 0x4a 0x0>; channel@0 { reg = <0x0>; adi,extended-name = "DEV_CLK"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x0>; }; channel@1 { reg = <0x1>; adi,extended-name = "DEV_CLK1"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x0>; }; channel@5 { reg = <0x5>; adi,extended-name = "FMC_CLK"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x0>; }; channel@6 { reg = <0x6>; adi,extended-name = "FMC_CLK1"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x0>; }; channel@2 { reg = <0x2>; adi,extended-name = "DEV_SYSREF"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x3>; }; channel@3 { reg = <0x3>; adi,extended-name = "DEV_SYSREF1"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x3>; }; channel@4 { reg = <0x4>; adi,extended-name = "FMC_SYSREF"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0x5>; adi,signal-source = <0x2>; }; channel@13 { reg = <0xd>; adi,extended-name = "TEST_OUT"; adi,driver-mode = <0x0>; adi,divider-phase = <0x0>; adi,channel-divider = <0xa>; adi,signal-source = <0x1>; }; }; trx0_ad9371: ad9371-phy@0 { #address-cells = <0x1>; #size-cells = <0x0>; compatible = "adi,ad9371"; reg = <0>; spi-max-frequency = <0x989680>; clocks = <&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi>, <&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi>, <&AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi>, <&clk0_ad9528 0>,<&clk0_ad9528 5>, <&clk0_ad9528 2>, <&clk0_ad9528 4>; clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk", "dev_clk", "fmc_clk","sysref_dev_clk","sysref_fmc_clk"; #clock-cells = <0x1>; clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk"; adi,clocks-clk-pll-vco-freq_khz = <9830400>; adi,clocks-device-clock_khz = <122880>; adi,clocks-clk-pll-hs-div = <4>; adi,clocks-clk-pll-vco-div = <2>; adi,jesd204-obs-framer-over-sample = <0>; adi,rx-profile-adc-div = <1>; adi,rx-profile-en-high-rej-dec5 = <1>; adi,rx-profile-iq-rate_khz = <122880>; adi,rx-profile-rf-bandwidth_hz = <100000000>; adi,rx-profile-rhb1-decimation = <1>; adi,rx-profile-rx-bbf-3db-corner_khz = <100000>; adi,rx-profile-rx-dec5-decimation = <5>; adi,rx-profile-rx-fir-decimation = <2>; adi,rx-profile-rx-fir-gain_db = <(-6)>; adi,rx-profile-rx-fir-num-fir-coefs = <48>; adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-5) (-26) (32) (51) (-67) (-116) (140) (212) (-252) (-367) (429) (595) (-688) (-931) (1072) (1427) (-1650) (-2188) (2612) (3496) (-4802) (-7591) (9656) (32317) (32317) (9656) (-7591) (-4802) (3496) (2612) (-2188) (-1650) (1427) (1072) (-931) (-688) (595) (429) (-367) (-252) (212) (140) (-116) (-67) (51) (32) (-26) (-5)>; adi,rx-profile-custom-adc-profile = /bits/ 16 <534 386 201 98 1280 491 1591 279 1306 104 792 28 48 39 23 187>; adi,obs-profile-adc-div = <1>; adi,obs-profile-en-high-rej-dec5 = <1>; adi,obs-profile-iq-rate_khz = <245760>; adi,obs-profile-rf-bandwidth_hz = <200000000>; adi,obs-profile-rhb1-decimation = <1>; adi,obs-profile-rx-bbf-3db-corner_khz = <100000>; adi,obs-profile-rx-dec5-decimation = <5>; adi,obs-profile-rx-fir-decimation = <1>; adi,obs-profile-rx-fir-gain_db = <6>; adi,obs-profile-rx-fir-num-fir-coefs = <24>; adi,obs-profile-rx-fir-coefs = /bits/ 16 <(-289) (81) (-23) (-86) (229) (-354) (397) (-233) (-657) (1699) (-4172) (23010) (-4172) (1699) (-657) (-233) (397) (-354) (229) (-86) (-23) (81) (-289) (0)>; adi,obs-profile-custom-adc-profile = /bits/ 16 <450 349 201 98 1280 730 1626 818 1476 732 834 20 41 36 24 200>; adi,obs-settings-custom-loopback-adc-profile = /bits/ 16 <569 369 201 98 1280 291 1541 149 1320 58 807 34 48 40 23 189>; adi,tx-profile-dac-div = <1>; adi,tx-profile-iq-rate_khz = <245760>; adi,tx-profile-primary-sig-bandwidth_hz = <75000000>; adi,tx-profile-rf-bandwidth_hz = <200000000>; adi,tx-profile-thb1-interpolation = <2>; adi,tx-profile-thb2-interpolation = <1>; adi,tx-profile-tx-bbf-3db-corner_khz = <100000>; adi,tx-profile-tx-dac-3db-corner_khz = <187000>; adi,tx-profile-tx-fir-interpolation = <1>; adi,tx-profile-tx-input-hb-interpolation = <1>; adi,tx-profile-tx-fir-gain_db = <6>; adi,tx-profile-tx-fir-num-fir-coefs = <16>; adi,tx-profile-tx-fir-coefs = /bits/ 16 <(6) (-270) (203) (-168) (-84) (983) (-3222) (21143) (-3222) (983) (-84) (-168) (203) (-270) (6) (0)>; adi,sniffer-profile-adc-div = <1>; adi,sniffer-profile-en-high-rej-dec5 = <0>; adi,sniffer-profile-iq-rate_khz = <30720>; adi,sniffer-profile-rf-bandwidth_hz = <20000000>; adi,sniffer-profile-rhb1-decimation = <2>; adi,sniffer-profile-rx-bbf-3db-corner_khz = <100000>; adi,sniffer-profile-rx-dec5-decimation = <5>; adi,sniffer-profile-rx-fir-decimation = <4>; reset-gpios = <&gpio 130 0>; test-gpios = <&gpio 131 0>; sysref_req-gpios = <&gpio 136 0>; rx2_enable-gpios = <&gpio 132 0>; rx1_enable-gpios = <&gpio 133 0>; tx2_enable-gpios = <&gpio 134 0>; tx1_enable-gpios = <&gpio 135 0>; adi,jesd204-deframer-eq-setting = <3>; }; }; &amba_pl { #address-cells = <0x1>; #size-cells = <0x1>; interrupt-parent = <&gic>; ranges = <0 0 0 0xffffffff>; }; /* TBD */ /* &axi_dma_0{ reg = <0x80001000 0x1000>; }; &axi_ethernet_0{ reg = <0x80000000 0x1000>; }; */ //2018.v2: axi_ad9371_core: axi_ad9371@84a00000 //2018v3: This "AD9371_TOP_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core" has same address like old one axi_ad9371_core: // This "AD9371_TOP_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core" is a new block // This "AD9371_TOP_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core" is a new block // &AD9371_TOP_ad9371_tpl_core_rx_ad9371_tpl_core_tpl_core { compatible = "adi,axi-ad9371-rx-1.0"; reg = <0x84a00000 0x10000>; //clock-names = "link_clk", "s_axi_aclk"; //clocks = <&misc_clk_0>, <&clk 71>; dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_dma 0>; dma-names = "rx"; spibus-connected = <&trx0_ad9371>; }; &AD9371_TOP_ad9371_tpl_core_rx_os_ad9371_tpl_core_tpl_core { compatible = "adi,axi-ad9371-rx-1.0"; reg = <0x84a08000 0x10000>; //clock-names = "link_clk", "s_axi_aclk"; //clocks = <&misc_clk_0>, <&clk 71>; dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_dma 0>; dma-names = "rx"; spibus-connected = <&trx0_ad9371>; }; &AD9371_TOP_ad9371_tpl_core_tx_ad9371_tpl_core_tpl_core { compatible = "adi,axi-ad9371-rx-1.0"; reg = <0x84a04000 0x10000>; //clock-names = "link_clk", "s_axi_aclk"; //clocks = <&misc_clk_0>, <&clk 71>; dmas = <&AXI_AD_DMA_TOP_axi_ad9371_rx_dma 0>; dma-names = "rx"; spibus-connected = <&trx0_ad9371>; }; &misc_clk_0 { #clock-cells = <0>; clock-frequency = <100000000>; compatible = "fixed-clock"; }; &misc_clk_1 { #clock-cells = <0>; clock-frequency = <100000000>; compatible = "fixed-clock"; }; /* &axi_ddc_rx_dma { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c400000 0x1000>; #dma-cells = <1>; #clock-cells = <0>; clocks = <&clk 73>; adi,channels { #size-cells = <0>; #address-cells = <1>; dma-channel@0 { reg = <0>; adi,source-bus-width = <60>; adi,source-bus-type = <2>; adi,destination-bus-width = <60>; adi,destination-bus-type = <0>; }; }; }; */ //2019.v2: axi_ad9371_rx_dma //2018.v3: AXI_AD_DMA_TOP_axi_ad9371_rx_dma &AXI_AD_DMA_TOP_axi_ad9371_rx_dma { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c400000 0x1000>; #dma-cells = <1>; #clock-cells = <0>; //2018.v2: Input Clock Configuration clocks = <&clk 73>; //2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk"; //clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>; adi,channels { #size-cells = <0>; #address-cells = <1>; dma-channel@0 { reg = <0>; adi,source-bus-width = <64>; adi,source-bus-type = <2>; adi,destination-bus-width = <64>; adi,destination-bus-type = <0>; }; }; }; //2018.v2: axi_ad9371_rx_jesd_rx_axi //2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi &AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_rx_axi { compatible = "adi,axi-jesd204-rx-1.0"; reg = <0x84aa0000 0x4000>; //2018.v2: Input Clock Configuration //clocks = <&clk 71>, <&axi_ad9371_rx_clkgen>, <&axi_ad9371_rx_xcvr 0>; clocks = <&clk 71>, <&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_clkgen>,<&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr 0>; clock-names = "s_axi_aclk", "device_clk", "lane_clk"; //2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk", "core_clk"; //clocks = <&clk 71>, <&misc_clk_0>; #clock-cells = <0>; clock-output-names = "jesd_rx_lane_clk"; adi,octets-per-frame = <4>; adi,frames-per-multiframe = <32>; }; //2018.v2: axi_ad9371_rx_os_dma //2018.v3: AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma &AXI_AD_DMA_TOP_axi_ad9371_rx_os_dma { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c440000 0x1000>; #dma-cells = <1>; #clock-cells = <0>; //2018.v2: Input Clock Configuration clocks = <&clk 73>; //2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk", "m_dest_axi_aclk", "fifo_wr_clk"; //clocks = <&clk 71>, <&clk 72>, <&misc_clk_0>; adi,channels { #size-cells = <0>; #address-cells = <1>; dma-channel@0 { reg = <0>; adi,source-bus-width = <64>; adi,source-bus-type = <2>; adi,destination-bus-width = <64>; adi,destination-bus-type = <0>; }; }; }; //2018.v2: axi_ad9371_rx_os_jesd_rx_axi //2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi &AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_rx_jesd_axi_ad9371_rx_os_jesd_rx_axi{ compatible = "adi,axi-jesd204-rx-1.0"; reg = <0x84ab0000 0x4000>; // 2018.v2: The clock configuration // clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>, <&axi_ad9371_rx_os_xcvr 0>; clocks = <&clk 71>, <&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen>,<&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr 0>; clock-names = "s_axi_aclk", "device_clk", "lane_clk"; // 2018.v3: New Clock Configuration //clock-names = "s_axi_aclk", "core_clk"; //clocks = <&clk 71>, <&misc_clk_0>; //Clock Output: No Change #clock-cells = <0>; clock-output-names = "jesd_rx_os_lane_clk"; adi,octets-per-frame = <2>; adi,frames-per-multiframe = <32>; }; //2018.v2: axi_ad9371_rx_os_xcvr //2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr &AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_os_xcvr { compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a50000 0x10000>; // 2018.v2: The clock configuration //clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>; clocks = <&clk0_ad9528 5>, <&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen>; clock-names = "conv", "div40"; // 2018.v3: New Clock Configuration //clock-names = "s_axi_aclk"; //clocks = <&clk 71>; #clock-cells = <1>; clock-output-names = "rx_os_gt_clk", "rx_os_out_clk"; adi,sys-clk-select = <0>; adi,out-clk-select = <3>; adi,use-lpm-enable; adi,use-cpll-enable; }; //2018.v2: axi_ad9371_rx_xcvr //2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr &AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_rx_xcvr { compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a60000 0x10000>; // 2018.v2: Input clock configuration //clocks = <&clk0_ad9528 5>, <&axi_ad9371_rx_clkgen 0>; clocks = <&clk0_ad9528 5>, <&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_clkgen 0>; clock-names = "conv", "div40"; // 2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk"; //clocks = <&clk 71>; #clock-cells = <1>; clock-output-names = "rx_gt_clk", "rx_out_clk"; adi,sys-clk-select = <0>; adi,out-clk-select = <3>; adi,use-lpm-enable; adi,use-cpll-enable; }; //2018.v2: axi_ad9371_rx_clkgen //2018.v3: AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_clkgen &AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_clkgen { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c10000 0x10000>; // 2018.v2: Input clock configuration clocks = <&clk0_ad9528 5>; // 2018.v3: Input Clock Configuration //clock-names = "clk", "s_axi_aclk"; //clocks = <&misc_clk_1>, <&clk 71>; #clock-cells = <0>; clock-output-names = "axi_rx_clkgen"; }; //2018.v3: AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_os_clkgen // Its a newly added block which is not present in 2018.v2 &AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_rx_os_clkgen { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c20000 0x10000>; clocks = <&clk0_ad9528 5>; //clock-names = "clk", "s_axi_aclk"; //clocks = <&misc_clk_1>, <&clk 71>; #clock-cells = <0x0>; clock-output-names = "axi_rx_os_clkgen"; }; //2018.v2: axi_ad9371_tx_clkgen //2018.v3: AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen //Depend: ?? &AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen { compatible = "adi,axi-clkgen-2.00.a"; reg = <0x83c00000 0x10000>; // 2018.v2: Input clock configuration clocks = <&clk0_ad9528 5>; // 2018.v3: Input Clock Configuration //clock-names = "clk", "s_axi_aclk"; //clocks = <&misc_clk_1>, <&clk 71>; clock-output-names = "axi_tx_clkgen"; #clock-cells = <0x0>; }; //2018.v2: axi_ad9371_tx_dma //2018.v3: AXI_AD_DMA_TOP_axi_ad9371_tx_dma &AXI_AD_DMA_TOP_axi_ad9371_tx_dma { compatible = "adi,axi-dmac-1.00.a"; reg = <0x9c420000 0x1000>; #dma-cells = <1>; #clock-cells = <0>; // 2018.v2: Input clock configuration clocks = <&clk 73>; // 2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk", "m_src_axi_aclk", "m_axis_aclk"; //clocks = <&clk 71>, <&clk 72>, <&clk 72>; adi,channels { #size-cells = <0>; #address-cells = <1>; dma-channel@0 { reg = <0>; adi,source-bus-width = <64>; adi,source-bus-type = <0>; adi,destination-bus-width = <128>; adi,destination-bus-type = <1>; }; }; }; //2018.v2: axi_ad9371_tx_jesd_tx_axi //2018.v3: AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi &AD9371_TOP_JESD_TOP_jesd_ctrl_top_axi_ad9371_tx_jesd_tx_axi { compatible = "adi,axi-jesd204-tx-1.0"; reg = <0x84a90000 0x4000>; //2018.v2: Input Clock Configuration //clocks = <&clk 71>, <&axi_ad9371_tx_clkgen>,<&axi_ad9371_tx_xcvr 0>; clocks = <&clk 71>,<&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen>,<&AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr 0>; clock-names = "s_axi_aclk", "device_clk", "lane_clk"; //2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk", "core_clk"; //clocks = <&clk 71>, <&misc_clk_0>; #clock-cells = <0>; clock-output-names = "jesd_tx_lane_clk"; adi,octets-per-frame = <2>; adi,frames-per-multiframe = <32>; adi,converter-resolution = <14>; adi,bits-per-sample = <16>; adi,converters-per-device = <4>; adi,control-bits-per-sample = <2>; }; //2018.v2: axi_ad9371_tx_xcvr //2018.v3: AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr &AD9371_TOP_JESD_TOP_xcvr_top_axi_ad9371_tx_xcvr{ compatible = "adi,axi-adxcvr-1.0"; reg = <0x84a80000 0x10000>; //2018.v2: Input Clock Configuration //clocks = <&clk0_ad9528 5>, <&axi_ad9371_tx_clkgen>; clocks = <&clk0_ad9528 5>, <&AD9371_TOP_ad9371_clk_rst_gen_top_axi_ad9371_tx_clkgen>; clock-names = "conv", "div40"; //2018.v3: Input Clock Configuration //clock-names = "s_axi_aclk"; //clocks = <&clk 71>; #clock-cells = <1>; clock-output-names = "tx_gt_clk", "tx_out_clk"; adi,sys-clk-select = <3>; adi,out-clk-select = <3>; }; /* &cpri_zcu102_0{ reg = <0x80004000 0x1000>; compatible = "generic-uio"; }; &axi_iic_0{ reg = <0x80003000 0x1000>; }; &user_reg_top_0{ reg = <0x80002000 0x1000>; compatible = "generic-uio"; }; */ &psu_ctrl_ipi { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0xff380000 0x80000>; }; &psu_message_buffers { compatible = "xlnx,PERIPHERAL-1.0"; reg = <0xff990000 0x10000>; };
Kindly see the system-user.dtsi and pl.dtsi if anything which is missing.
Regards,
Manish
We are not reviewing auto-generated device trees. There are many things missing.
Please use the device trees quoted below as your base, and only updated mappings in case they are different.
https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9371.dts
https://github.com/analogdevicesinc/linux/blob/master/arch/arm64/boot/dts/xilinx/adi-adrv9371.dtsi
If you have custom cores simply copy them from the auto-generated device trees.
-Michael
Hey Hi Michael,
It is not auto generated at all. We missed to remove "auto-generated" string. Though, will try with the links that you have shared and will update.
Thanks for the prompt reply.
Hi Michael,
We tried your links of dtsi file and it works.
Thanks,