AD9361 not transmitting when configured for low sampling rates


We are upgrading a working design that interfaces FMCOMMS4 with ZCU102 kit from Xilinx tools v2017.2 to v2018.3.

We used ADI HDL reference design hdl_2018_r2 with Vivado 2018.3 and PetaLinux 2018.3 version tools for generating the design files and boot images.

I was able to build the image and boot the kit successfully. However, I am having an issue that there is no signal coming out of AD9361 transmitter output. I was able to isolate it to use of lower base-band sampling clock rate (288kHz) in my application. The same design is working well, when we change the sampling rate to a higher number like 7.68MHz.

Working AD9361 configuration: 983040000,122880000,61440000,30720000,30720000,7680000
Non-working AD9361 configuration: 884736000,13824000,4608000,2304000,1152000,288000

As the design was working in 2017.2 tools, we compared the driver files and noticed that we had to change the definition MIN_ADC_CLK in ad9361.h from 25MHz to 10MHz in ad9361 driver files. We made the same change in file ad9361_regs.h of 2018.3 tools, However, it did not help.

When we further debugged by reading back the AD9361 configuration in both cases, we noticed that the "ensm_mode" was in "alert" mode rather than "fdd" that we set it to. After changing "ensm_mode" to "fdd" from command prompt, we could see the AD9361 transmitting properly with 288kHz base-band sampling clock.

Could you please suggest what may be causing the "ensm_mode" to change from "fdd" to "alert" during configuration at the time of booting for 288kHz case and suggest a way to rectify it without our having to configure it manually after booting?

Best regards,