ERROR: [IP_Flow 19-3461] on custom platform

I'm porting the FMCOMMS5 to a custom board and every time I build the project I receive the following error:

### ad_ip_instance axi_iic axi_iic_main
### ad_ip_parameter axi_iic_main CONFIG.USE_BOARD_FLOW true
### ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}
ERROR: [IP_Flow 19-3461] Value 'IIC_MAIN' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell 'axi_iic_main' . Valid values are - Custom
INFO: [IP_Flow 19-3438] Customization errors found on 'axi_iic_main'. Restoring to previous valid configuration.
ERROR: [BD 41-245] set_property error - Value 'IIC_MAIN' is out of the range for parameter 'IIC Board Interface(IIC_BOARD_INTERFACE)' for BD Cell 'axi_iic_main' . Valid values are - Custom
Customization errors found on 'axi_iic_main'. Restoring to previous valid configuration.

ERROR: [Common 17-39] 'set_property' failed due to earlier errors.

    while executing
"rdi::set_property CONFIG.IIC_BOARD_INTERFACE IIC_MAIN /axi_iic_main"
    invoked from within
"set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]"
    (procedure "ad_ip_parameter" line 3)
    invoked from within
"ad_ip_parameter axi_iic_main CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}"
    (file "/home/nturner/gemini_hdl/projects/common/custom/custom_system_bd.tcl" line 64)

    while executing
"source $ad_hdl_dir/projects/common/custom/custom_system_bd.tcl"
    (file "system_bd.tcl" line 3)

    while executing
"source system_bd.tcl"
    (procedure "adi_project_xilinx" line 114)
    invoked from within
"adi_project_xilinx fmcomms5_custom"
    (file "system_project.tcl" line 6)
INFO: [Common 17-206] Exiting Vivado at Wed Jun 26 17:43:14 2019...

The project includes some 3rd party IP that includes the following lines:

  <spirit:busInterfaces>
    <spirit:busInterface>
      <spirit:name>EMIO_I2C1</spirit:name>
      <spirit:displayName>EMIO I2C</spirit:displayName>
      <spirit:description>EMIO I2C connection to SC resources</spirit:description>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
      <spirit:slave/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sda_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>scl_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sda_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>scl_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>sda_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>scl_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
    <spirit:busInterface>
      <spirit:name>EXT_I2C</spirit:name>
      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic" spirit:version="1.0"/>
      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="iic_rtl" spirit:version="1.0"/>
      <spirit:master/>
      <spirit:portMaps>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_scl_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_sda_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_sda_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SDA_T</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_sda_t</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_O</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_scl_o</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
        <spirit:portMap>
          <spirit:logicalPort>
            <spirit:name>SCL_I</spirit:name>
          </spirit:logicalPort>
          <spirit:physicalPort>
            <spirit:name>ext_scl_i</spirit:name>
          </spirit:physicalPort>
        </spirit:portMap>
      </spirit:portMaps>
    </spirit:busInterface>
  </spirit:busInterfaces>

Would the way the I2C is implemented in this IP block interfere with how it's implemented in custom_system_bd.tcl? If not is there another reason for this error? Other posts seem to suggest a version mismatch, but I'm using Vivado 2018.2 with the hdl_2018_r2 branch.

Parents
  • Hi,

    This is something new.
    Can you please start a build of the project from the Vivado GUI.
    If you kept the ADI build flow, open GUI. In the tcl console enter:
       cd <your project location>
       source ./system_project.tcl

    After the error occurs, manually remove the AXI_IIC core from the block design and add it back again and take a look at the tcl commands vivado is outputting.

    Let me know if it works, and if you see some differences in the tcl commands, comparing with the ones from the _bd.tcl script.

    Thanks,
    Andrei

Reply
  • Hi,

    This is something new.
    Can you please start a build of the project from the Vivado GUI.
    If you kept the ADI build flow, open GUI. In the tcl console enter:
       cd <your project location>
       source ./system_project.tcl

    After the error occurs, manually remove the AXI_IIC core from the block design and add it back again and take a look at the tcl commands vivado is outputting.

    Let me know if it works, and if you see some differences in the tcl commands, comparing with the ones from the _bd.tcl script.

    Thanks,
    Andrei

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