I am working with an A10 SOC board and the ADRV9371 evaluation board. I changed the oscillator on board the ADRV9371 to have a VCXO = 100MHz so that I may derive a 120MHz device clock. I updated the adi-adrv9371.dtsi file to reflect the new PLL2, PLL1, VCXO, and VCO settings that are required with the new VCXO. I used make to generate the new device tree blob as instructed in the wiki and tried to boot the A10 board. However, it appears that the 9371 driver fails with the following messages:
[ 1.081652] dw_mmc ff808000.dwmmc0: 1 slots initialized[ 1.087215] ledtrig-cpu: registered to indicate activity on CPUs[ 1.093421] usbcore: registered new interface driver usbhid[ 1.098969] usbhid: USB HID core driver[ 1.103227] ad9371 spi32766.1: ad9371_probe : enter[ 1.108733] spi32766.0 supply vcc not found, using dummy regulator[ 1.130581] ad9528 spi32766.0: Feedback calibration divider value (18) out of range[ 1.138308] ad9528: probe of spi32766.0 failed with error -22[ 1.145902] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
Could you please help me to identify what this message means in terms of the 9528 PLL settings that need to be updated?
Thanks very much!
Actually, I was able to change the N2 feedback value such that the 9528 driver is happy. However, I am now facing the following error:
[ 1.093336] usbcore: registered new interface driver usbhid[ 1.098883] usbhid: USB HID core driver[ 1.103136] ad9371 spi32766.1: ad9371_probe : enter[ 1.108637] spi32766.0 supply vcc not found, using dummy regulator[ 1.170259] mmc_host mmc0: Bus speed (slot 0) = 50000000Hz (slot req 50000000Hz, actual 50000000HZ div = 0)[ 1.180015] mmc0: new high speed SDHC card at address 0007[ 1.185863] mmcblk0: mmc0:0007 SD16G 14.4 GiB[ 1.191569] mmcblk0: p1 p2 p3[ 1.197381] random: fast init done[ 4.351911] ad9528: probe of spi32766.0 failed with error -110[ 4.359842] fpga_manager fpga0: SoCFPGA Arria10 FPGA Manager registered
Can I please get some help on this question?
Most likely, at least one of the bits AD9528_VCXO_OK and AD9528_PLL2_LOCKED are not set when the driver tries to read the AD9528_READBACK register. Can you compare the amplitude of your new VCXO to the one of the original one?
Do you mean measure off the board using an oscilloscope? Or is there a way to do it through firmware?
Nevermind, I am dumb and didn't set the N divider value correctly. I was able to print the READBACK bits in the 9528 driver and realized everything was okay except for PLL2_LOCKED. Thanks for pointing me in this direction!