ADRV9009 + ZCU102 axi_adxcvr 84a50000.axi-adxcvr-rx-os: RX Error: 0

HI,

I don't know if this is the right forum.  If not, please move it to the correct forum.

I try to build a system with the latest kernel paired with dev_adrv9009_less_lanes HDF but I got the following errors during boot up:

[   11.264323] axi_adxcvr 84a50000.axi-adxcvr-rx-os: RX Error: 0
[   11.270068] adrv9009 spi1.1: jesd_rx_os_clk enable failed (-5)
[   11.275967] adrv9009 spi1.1: ADIHAL_resetHw at index
[   18.912567] axi_adxcvr 84a50000.axi-adxcvr-rx-os: RX Error: 0
[   18.918318] adrv9009 spi1.1: jesd_rx_os_clk enable failed (-5)
[   18.924172] adrv9009: probe of spi1.1 failed with error -5

Below list the steps to generate the system:

1. Generate the latest kernel, 14.04, from here: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/linux/zynqmp

2. Generate hdf from the dev_adrv9009_less_lanes design.

3. Adapt the adi-adrv9009.dtsi for dev_adrv9009_less_lanes:

adi-adrv9009.dtsi.txt
#include <dt-bindings/iio/frequency/ad9528.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	clocks {
		adrv9009_clkin: clock@0 {
			compatible = "fixed-clock";

			clock-frequency = <12288000>;
			clock-output-names = "adrv9009_ext_refclk";
			#clock-cells = <0>;
		};
	};
};

&fmc_spi {

	clk0_ad9528: ad9528-1@0 {
		compatible = "adi,ad9528";
		reg = <0>;

		#address-cells = <1>;
		#size-cells = <0>;

		spi-max-frequency = <10000000>;
		//adi,spi-3wire-enable;

		clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2",
			"ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6",
			"ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10",
			"ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
		#clock-cells = <1>;

		adi,vcxo-freq = <122880000>;

		adi,refa-enable;
		adi,refa-diff-rcv-enable;
		adi,refa-r-div = <1>;
		adi,osc-in-cmos-neg-inp-enable;

		/* PLL1 config */
		adi,pll1-feedback-div = <4>;
		adi,pll1-charge-pump-current-nA = <5000>;

		/* PLL2 config */
		adi,pll2-vco-div-m1 = <3>; /* use 5 for 184320000 output device clock */
		adi,pll2-n2-div = <10>; /* N / M1 */
		adi,pll2-r1-div = <1>;
		adi,pll2-charge-pump-current-nA = <805000>;

		/* SYSREF config */
		adi,sysref-src = <SYSREF_SRC_INTERNAL>;
		adi,sysref-pattern-mode = <SYSREF_PATTERN_CONTINUOUS>;
		adi,sysref-k-div = <512>;
		adi,sysref-request-enable;
		adi,sysref-nshot-mode = <SYSREF_NSHOT_4_PULSES>;
		adi,sysref-request-trigger-mode = <SYSREF_LEVEL_HIGH>;

		adi,rpole2 = <RPOLE2_900_OHM>;
		adi,rzero = <RZERO_1850_OHM>;
		adi,cpole1 = <CPOLE1_16_PF>;

		adi,status-mon-pin0-function-select = <1>; /* PLL1 & PLL2 Locked */
		adi,status-mon-pin1-function-select = <7>; /* REFA Correct */

		ad9528_0_c13: channel@13 {
			reg = <13>;
			adi,extended-name = "DEV_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <5>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_0_c1: channel@1 {
			reg = <1>;
			adi,extended-name = "FMC_CLK";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <5>;
			adi,signal-source = <SOURCE_VCO>;
		};

		ad9528_0_c12: channel@12 {
			reg = <12>;
			adi,extended-name = "DEV_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <5>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};

		ad9528_0_c3: channel@3 {
			reg = <3>;
			adi,extended-name = "FMC_SYSREF";
			adi,driver-mode = <DRIVER_MODE_LVDS>;
			adi,divider-phase = <0>;
			adi,channel-divider = <5>;
			adi,signal-source = <SOURCE_SYSREF_VCO>;
		};
	};

	trx0_adrv9009: adrv9009-phy@1 {
		compatible = "adrv9009";
		reg = <1>;

		#address-cells = <1>;
		#size-cells = <0>;

		/* SPI Setup */
		spi-max-frequency = <25000000>;

		interrupt-parent = <&gpio>;
		interrupts = <129 IRQ_TYPE_EDGE_RISING>;

		/* Clocks */
		clocks = <&axi_adrv9009_rx_jesd>, <&axi_adrv9009_tx_jesd>,
			<&axi_adrv9009_rx_os_jesd>, <&clk0_ad9528 13>,
			<&clk0_ad9528 1>, <&clk0_ad9528 12>, <&clk0_ad9528 3>;
		clock-names = "jesd_rx_clk", "jesd_tx_clk", "jesd_rx_os_clk",
			"dev_clk", "fmc_clk", "sysref_dev_clk",
			"sysref_fmc_clk";

		clock-output-names = "rx_sampl_clk", "rx_os_sampl_clk", "tx_sampl_clk";
		#clock-cells = <1>;

		/* JESD204 */

		/* JESD204 RX */
		adi,jesd204-framer-a-bank-id = <1>;
		adi,jesd204-framer-a-device-id = <0>;
		adi,jesd204-framer-a-lane0-id = <0>;
		adi,jesd204-framer-a-m = <4>;
		adi,jesd204-framer-a-k = <32>;
		adi,jesd204-framer-a-f = <8>;
		adi,jesd204-framer-a-np = <16>;
		adi,jesd204-framer-a-scramble = <1>;
		adi,jesd204-framer-a-external-sysref = <1>;
		adi,jesd204-framer-a-serializer-lanes-enabled = <0x01>;
		adi,jesd204-framer-a-serializer-lane-crossbar = <0xE4>;
		adi,jesd204-framer-a-lmfc-offset = <31>;
		adi,jesd204-framer-a-new-sysref-on-relink = <0>;
		adi,jesd204-framer-a-syncb-in-select = <0>;
		adi,jesd204-framer-a-over-sample = <0>;
		adi,jesd204-framer-a-syncb-in-lvds-mode = <1>;
		adi,jesd204-framer-a-syncb-in-lvds-pn-invert = <0>;
		adi,jesd204-framer-a-enable-manual-lane-xbar = <0>;

		/* JESD204 OBS */
		adi,jesd204-framer-b-bank-id = <0>;
		adi,jesd204-framer-b-device-id = <0>;
		adi,jesd204-framer-b-lane0-id = <0>;
		adi,jesd204-framer-b-m = <2>;
		adi,jesd204-framer-b-k = <32>;
		adi,jesd204-framer-b-f = <2>;
		adi,jesd204-framer-b-np = <16>;
		adi,jesd204-framer-b-scramble = <1>;
		adi,jesd204-framer-b-external-sysref = <1>;
		adi,jesd204-framer-b-serializer-lanes-enabled = <0x03>;
		adi,jesd204-framer-b-serializer-lane-crossbar = <0xE4>;
		adi,jesd204-framer-b-lmfc-offset = <31>;
		adi,jesd204-framer-b-new-sysref-on-relink = <0>;
		adi,jesd204-framer-b-syncb-in-select = <1>;
		adi,jesd204-framer-b-over-sample = <0>;
		adi,jesd204-framer-b-syncb-in-lvds-mode = <1>;
		adi,jesd204-framer-b-syncb-in-lvds-pn-invert = <0>;
		adi,jesd204-framer-b-enable-manual-lane-xbar = <0>;

		/* JESD204 TX */
		adi,jesd204-deframer-a-bank-id = <0>;
		adi,jesd204-deframer-a-device-id = <0>;
		adi,jesd204-deframer-a-lane0-id = <0>;
		adi,jesd204-deframer-a-m = <4>;
		adi,jesd204-deframer-a-k = <32>;
		adi,jesd204-deframer-a-scramble = <1>;
		adi,jesd204-deframer-a-external-sysref = <1>;
		adi,jesd204-deframer-a-deserializer-lanes-enabled = <0x01>;
		adi,jesd204-deframer-a-deserializer-lane-crossbar = <0xE4>;
		adi,jesd204-deframer-a-lmfc-offset = <17>;
		adi,jesd204-deframer-a-new-sysref-on-relink = <0>;
		adi,jesd204-deframer-a-syncb-out-select = <0>;
		adi,jesd204-deframer-a-np = <16>;
		adi,jesd204-deframer-a-syncb-out-lvds-mode = <1>;
		adi,jesd204-deframer-a-syncb-out-lvds-pn-invert = <0>;
		adi,jesd204-deframer-a-syncb-out-cmos-slew-rate = <0>;
		adi,jesd204-deframer-a-syncb-out-cmos-drive-level = <0>;
		adi,jesd204-deframer-a-enable-manual-lane-xbar = <0>;

		adi,jesd204-ser-amplitude = <15>;
		adi,jesd204-ser-pre-emphasis = <1>;
		adi,jesd204-ser-invert-lane-polarity = <0>;
		adi,jesd204-des-invert-lane-polarity = <0>;
		adi,jesd204-des-eq-setting = <1>;
		adi,jesd204-sysref-lvds-mode = <1>;
		adi,jesd204-sysref-lvds-pn-invert = <0>;

		/* RX */

		adi,rx-profile-rx-fir-gain_db = <(-6)>;
		adi,rx-profile-rx-fir-num-fir-coefs = <48>;
		adi,rx-profile-rx-fir-coefs = /bits/ 16 <(-2) (23) (46) (-17) (-104) (10) (208) (23) (-370) (-97) (607) (240) (-942) (-489) (1407) (910) (-2065) (-1637) (3058) (2995) (-4912) (-6526) (9941) (30489) (30489) (9941) (-6526) (-4912) (2995) (3058) (-1637) (-2065) (910) (1407) (-489) (-942) (240) (607) (-97) (-370) (23) (208) (10) (-104) (-17) (46) (23) (-2)>;

		adi,rx-profile-rx-fir-decimation = <2>;
		adi,rx-profile-rx-dec5-decimation = <4>;
		adi,rx-profile-rhb1-decimation = <1>;
		adi,rx-profile-rx-output-rate_khz = <245760>;
		adi,rx-profile-rf-bandwidth_hz = <200000000>;
		adi,rx-profile-rx-bbf3d-bcorner_khz = <200000>;
		adi,rx-profile-rx-adc-profile = /bits/ 16 <182 142 173 90 1280 982 1335 96 1369 48 1012 18 48 48 37 208 0 0 0 0 52 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
		adi,rx-profile-rx-ddc-mode = <0>;

		adi,rx-nco-shifter-band-a-input-band-width_khz = <0>;
		adi,rx-nco-shifter-band-a-input-center-freq_khz = <0>;
		adi,rx-nco-shifter-band-a-nco1-freq_khz = <0>;
		adi,rx-nco-shifter-band-a-nco2-freq_khz = <0>;
		adi,rx-nco-shifter-band-binput-band-width_khz = <0>;
		adi,rx-nco-shifter-band-binput-center-freq_khz = <0>;
		adi,rx-nco-shifter-band-bnco1-freq_khz = <0>;
		adi,rx-nco-shifter-band-bnco2-freq_khz = <0>;

		adi,rx-gain-control-gain-mode = <0>;
		adi,rx-gain-control-rx1-gain-index = <255>;
		adi,rx-gain-control-rx2-gain-index = <255>;
		adi,rx-gain-control-rx1-max-gain-index = <255>;
		adi,rx-gain-control-rx1-min-gain-index = <195>;
		adi,rx-gain-control-rx2-max-gain-index = <255>;
		adi,rx-gain-control-rx2-min-gain-index = <195>;

		adi,rx-settings-framer-sel = <0>;
		adi,rx-settings-rx-channels = <3>;

		/* ORX */

		adi,orx-profile-rx-fir-gain_db = <6>;
		adi,orx-profile-rx-fir-num-fir-coefs = <24>;
		adi,orx-profile-rx-fir-coefs = /bits/ 16  <(-10) (7) (-10) (-12) (6) (-12) (16) (-16) (1) (63) (-431) (17235) (-431) (63) (1) (-16) (16) (-12) (6) (-12) (-10) (7) (-10) (0)>;
		adi,orx-profile-rx-fir-decimation = <1>;
		adi,orx-profile-rx-dec5-decimation = <4>;
		adi,orx-profile-rhb1-decimation = <2>;
		adi,orx-profile-orx-output-rate_khz = <245760>;
		adi,orx-profile-rf-bandwidth_hz = <200000000>;
		adi,orx-profile-rx-bbf3d-bcorner_khz = <225000>;
		adi,orx-profile-orx-low-pass-adc-profile = /bits/ 16  <185 141 172 90 1280 942 1332 90 1368 46 1016 19 48 48 37 208 0 0 0 0 52 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
		adi,orx-profile-orx-band-pass-adc-profile = /bits/ 16  <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
		adi,orx-profile-orx-ddc-mode = <0>;
		adi,orx-profile-orx-merge-filter = /bits/ 16  <0 0 0 0 0 0 0 0 0 0 0 0>;

		adi,orx-gain-control-gain-mode = <0>;
		adi,orx-gain-control-orx1-gain-index = <255>;
		adi,orx-gain-control-orx2-gain-index = <255>;
		adi,orx-gain-control-orx1-max-gain-index = <255>;
		adi,orx-gain-control-orx1-min-gain-index = <195>;
		adi,orx-gain-control-orx2-max-gain-index = <255>;
		adi,orx-gain-control-orx2-min-gain-index = <195>;

		adi,obs-settings-framer-sel = <1>;
		adi,obs-settings-obs-rx-channels-enable = <3>;
		adi,obs-settings-obs-rx-lo-source = <0>;

		/* TX */

		adi,tx-profile-tx-fir-gain_db = <6>;
		adi,tx-profile-tx-fir-num-fir-coefs = <40>;
		adi,tx-profile-tx-fir-coefs = /bits/ 16  <(-14) (5) (-9) (6) (-4) (19) (-29) (27) (-30) (46) (-63) (77) (-103) (150) (-218) (337) (-599) (1266) (-2718) (19537) (-2718) (1266) (-599) (337) (-218) (150) (-103) (77) (-63) (46) (-30) (27) (-29) (19) (-4) (6) (-9) (5) (-14) (0)>;

		adi,tx-profile-dac-div = <1>;

		adi,tx-profile-tx-fir-interpolation = <1>;
		adi,tx-profile-thb1-interpolation = <2>;
		adi,tx-profile-thb2-interpolation = <2>;
		adi,tx-profile-thb3-interpolation = <2>;
		adi,tx-profile-tx-int5-interpolation = <1>;
		adi,tx-profile-tx-input-rate_khz = <245760>;
		adi,tx-profile-primary-sig-bandwidth_hz = <100000000>;
		adi,tx-profile-rf-bandwidth_hz = <225000000>;
		adi,tx-profile-tx-dac3d-bcorner_khz = <225000>;
		adi,tx-profile-tx-bbf3d-bcorner_khz = <113000>;
		adi,tx-profile-loop-back-adc-profile = /bits/ 16 <206 132 168 90 1280 641 1307 53 1359 28 1039 30 48 48 37 210 0 0 0 0 53 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;

		adi,tx-settings-deframer-sel = <0>;
		adi,tx-settings-tx-channels = <3>;
		adi,tx-settings-tx-atten-step-size = <0>;
		adi,tx-settings-tx1-atten_md-b = <10000>;
		adi,tx-settings-tx2-atten_md-b = <10000>;
		adi,tx-settings-dis-tx-data-if-pll-unlock = <0>;

		/* Clocks */

		adi,dig-clocks-device-clock_khz = <245760>;
		adi,dig-clocks-clk-pll-vco-freq_khz = <9830400>;
		adi,dig-clocks-clk-pll-hs-div = <1>;
		adi,dig-clocks-rf-pll-use-external-lo = <0>;
		adi,dig-clocks-rf-pll-phase-sync-mode = <0>;

		/* AGC */

		adi,rxagc-peak-agc-under-range-low-interval_ns = <205>;
		adi,rxagc-peak-agc-under-range-mid-interval = <2>;
		adi,rxagc-peak-agc-under-range-high-interval = <4>;
		adi,rxagc-peak-apd-high-thresh = <39>;
		adi,rxagc-peak-apd-low-gain-mode-high-thresh = <36>;
		adi,rxagc-peak-apd-low-thresh = <23>;
		adi,rxagc-peak-apd-low-gain-mode-low-thresh = <19>;
		adi,rxagc-peak-apd-upper-thresh-peak-exceeded-cnt = <6>;
		adi,rxagc-peak-apd-lower-thresh-peak-exceeded-cnt = <3>;
		adi,rxagc-peak-apd-gain-step-attack = <4>;
		adi,rxagc-peak-apd-gain-step-recovery = <2>;
		adi,rxagc-peak-enable-hb2-overload = <1>;
		adi,rxagc-peak-hb2-overload-duration-cnt = <1>;
		adi,rxagc-peak-hb2-overload-thresh-cnt = <4>;
		adi,rxagc-peak-hb2-high-thresh = <181>;
		adi,rxagc-peak-hb2-under-range-low-thresh = <45>;
		adi,rxagc-peak-hb2-under-range-mid-thresh = <90>;
		adi,rxagc-peak-hb2-under-range-high-thresh = <128>;
		adi,rxagc-peak-hb2-upper-thresh-peak-exceeded-cnt = <6>;
		adi,rxagc-peak-hb2-lower-thresh-peak-exceeded-cnt = <3>;
		adi,rxagc-peak-hb2-gain-step-high-recovery = <2>;
		adi,rxagc-peak-hb2-gain-step-low-recovery = <4>;
		adi,rxagc-peak-hb2-gain-step-mid-recovery = <8>;
		adi,rxagc-peak-hb2-gain-step-attack = <4>;
		adi,rxagc-peak-hb2-overload-power-mode = <1>;
		adi,rxagc-peak-hb2-ovrg-sel = <0>;
		adi,rxagc-peak-hb2-thresh-config = <3>;

		adi,rxagc-power-power-enable-measurement = <1>;
		adi,rxagc-power-power-use-rfir-out = <1>;
		adi,rxagc-power-power-use-bbdc2 = <0>;
		adi,rxagc-power-under-range-high-power-thresh = <9>;
		adi,rxagc-power-under-range-low-power-thresh = <2>;
		adi,rxagc-power-under-range-high-power-gain-step-recovery = <4>;
		adi,rxagc-power-under-range-low-power-gain-step-recovery = <4>;
		adi,rxagc-power-power-measurement-duration = <5>;
		adi,rxagc-power-rx1-tdd-power-meas-duration = <5>;
		adi,rxagc-power-rx1-tdd-power-meas-delay = <1>;
		adi,rxagc-power-rx2-tdd-power-meas-duration = <5>;
		adi,rxagc-power-rx2-tdd-power-meas-delay = <1>;
		adi,rxagc-power-upper0-power-thresh = <2>;
		adi,rxagc-power-upper1-power-thresh = <0>;
		adi,rxagc-power-power-log-shift = <0>;

		adi,rxagc-agc-peak-wait-time = <4>;
		adi,rxagc-agc-rx1-max-gain-index = <255>;
		adi,rxagc-agc-rx1-min-gain-index = <195>;
		adi,rxagc-agc-rx2-max-gain-index = <255>;
		adi,rxagc-agc-rx2-min-gain-index = <195>;
		adi,rxagc-agc-gain-update-counter_us = <250>;
		adi,rxagc-agc-rx1-attack-delay = <10>;
		adi,rxagc-agc-rx2-attack-delay = <10>;
		adi,rxagc-agc-slow-loop-settling-delay = <16>;
		adi,rxagc-agc-low-thresh-prevent-gain = <0>;
		adi,rxagc-agc-change-gain-if-thresh-high = <1>;
		adi,rxagc-agc-peak-thresh-gain-control-mode = <1>;
		adi,rxagc-agc-reset-on-rxon = <0>;
		adi,rxagc-agc-enable-sync-pulse-for-gain-counter = <0>;
		adi,rxagc-agc-enable-ip3-optimization-thresh = <0>;
		adi,rxagc-ip3-over-range-thresh = <31>;
		adi,rxagc-ip3-over-range-thresh-index = <246>;
		adi,rxagc-ip3-peak-exceeded-cnt = <4>;
		adi,rxagc-agc-enable-fast-recovery-loop = <0>;


		/* Misc */

		adi,aux-dac-enables = <0x00>; /* Mask */

		adi,aux-dac-vref0 = <3>;
		adi,aux-dac-resolution0 = <0>;
		adi,aux-dac-values0 = <0>;
		adi,aux-dac-vref1 = <3>;
		adi,aux-dac-resolution1 = <0>;
		adi,aux-dac-values1 = <0>;
		adi,aux-dac-vref2 = <3>;
		adi,aux-dac-resolution2 = <0>;
		adi,aux-dac-values2 = <0>;
		adi,aux-dac-vref3 = <3>;
		adi,aux-dac-resolution3 = <0>;
		adi,aux-dac-values3 = <0>;
		adi,aux-dac-vref4 = <3>;
		adi,aux-dac-resolution4 = <0>;
		adi,aux-dac-values4 = <0>;
		adi,aux-dac-vref5 = <3>;
		adi,aux-dac-resolution5 = <0>;
		adi,aux-dac-values5 = <0>;
		adi,aux-dac-vref6 = <3>;
		adi,aux-dac-resolution6 = <0>;
		adi,aux-dac-values6 = <0>;
		adi,aux-dac-vref7 = <3>;
		adi,aux-dac-resolution7 = <0>;
		adi,aux-dac-values7 = <0>;
		adi,aux-dac-vref8 = <3>;
		adi,aux-dac-resolution8 = <0>;
		adi,aux-dac-values8 = <0>;
		adi,aux-dac-vref9 = <3>;
		adi,aux-dac-resolution9 = <0>;
		adi,aux-dac-values9 = <0>;
		adi,aux-dac-vref10 = <3>;
		adi,aux-dac-resolution10 = <0>;
		adi,aux-dac-values10 = <0>;
		adi,aux-dac-vref11 = <3>;
		adi,aux-dac-resolution11 = <0>;
		adi,aux-dac-values11 = <0>;

		adi,arm-gpio-config-orx1-tx-sel0-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx1-tx-sel0-pin-polarity = <0>;
		adi,arm-gpio-config-orx1-tx-sel0-pin-enable = <0>;

		adi,arm-gpio-config-orx1-tx-sel1-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx1-tx-sel1-pin-polarity = <0>;
		adi,arm-gpio-config-orx1-tx-sel1-pin-enable = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-polarity = <0>;
		adi,arm-gpio-config-orx2-tx-sel0-pin-enable = <0>;

		adi,arm-gpio-config-orx2-tx-sel1-pin-gpio-pin-sel = <0>;
		adi,arm-gpio-config-orx2-tx-sel1-pin-polarity = <0>;
		adi,arm-gpio-config-orx2-tx-sel1-pin-enable = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-gpio-pin-sel = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-polarity = <0>;
		adi,arm-gpio-config-en-tx-tracking-cals-enable = <0>;

		adi,orx-lo-cfg-disable-aux-pll-relocking = <0>;
		adi,orx-lo-cfg-gpio-select = <19>;

		adi,fhm-config-fhm-gpio-pin = <0>;
		adi,fhm-config-fhm-min-freq_mhz = <2400>;
		adi,fhm-config-fhm-max-freq_mhz = <2500>;

		adi,fhm-mode-fhm-enable = <0>;
		adi,fhm-mode-enable-mcs-sync = <0>;
		adi,fhm-mode-fhm-trigger-mode = <0>;
		adi,fhm-mode-fhm-exit-mode = <1>;
		adi,fhm-mode-fhm-init-frequency_hz = <2450000000>;

		adi,rx1-gain-ctrl-pin-inc-step = <1>;
		adi,rx1-gain-ctrl-pin-dec-step = <1>;
		adi,rx1-gain-ctrl-pin-rx-gain-inc-pin = <0>;
		adi,rx1-gain-ctrl-pin-rx-gain-dec-pin = <1>;
		adi,rx1-gain-ctrl-pin-enable = <0>;

		adi,rx2-gain-ctrl-pin-inc-step = <1>;
		adi,rx2-gain-ctrl-pin-dec-step = <1>;
		adi,rx2-gain-ctrl-pin-rx-gain-inc-pin = <3>;
		adi,rx2-gain-ctrl-pin-rx-gain-dec-pin = <4>;
		adi,rx2-gain-ctrl-pin-enable = <0>;

		adi,tx1-atten-ctrl-pin-step-size = <0>;
		adi,tx1-atten-ctrl-pin-tx-atten-inc-pin = <4>;
		adi,tx1-atten-ctrl-pin-tx-atten-dec-pin = <5>;
		adi,tx1-atten-ctrl-pin-enable = <0>;

		adi,tx2-atten-ctrl-pin-step-size = <0>;
		adi,tx2-atten-ctrl-pin-tx-atten-inc-pin = <6>;
		adi,tx2-atten-ctrl-pin-tx-atten-dec-pin = <7>;
		adi,tx2-atten-ctrl-pin-enable = <0>;

		adi,tx-pa-protection-avg-duration = <3>;
		adi,tx-pa-protection-tx-atten-step = <2>;
		adi,tx-pa-protection-tx1-power-threshold = <4096>;
		adi,tx-pa-protection-tx2-power-threshold = <4096>;
		adi,tx-pa-protection-peak-count = <4>;
		adi,tx-pa-protection-tx1-peak-threshold = <140>;
		adi,tx-pa-protection-tx2-peak-threshold = <140>;
	};
};

4. Generate a boot.bin using the hdf and the modified devicetree.  Then replace the boot.bin on the SD card with the new boot.bin.

I booted up the system with the newly generated image and got the above errors.

I'm wondering is there anything missed in the above procedures.

Thanks,

Henry

  • Hello Henry,

    Sorry for the late reply. Do you still need assistance?

    Is there a reason you're using the dev_adrv9009_less_lanes  branch ?We usually suggest using the latest release branch for best stability or master branch for latest updates.

    Regards,

    Adrian

  • Hi Adrian,

    Thanks for your reply.  The reason to use the less_lanes was a suggestion from Travis that the 4-lane JESD may be a problem of low sampling rate of my design.  (see here: https://ez.analog.com/fpga/f/q-a/111369/2018_r2-iio-does-not-take-profile-from-adrv9009-profile-configuration-wizard-v2-3)

    I had compiled the less-lanes HDF and incorporate in the latest software release but no success.

    At this point, I am still stuck with higher unnecessary sampling rate and wider bandwidth.  I appreciate if you provide any hints to either use the latest greatest release with lower sampling rate or using the less-lanes with a compatible software release.

    Thanks,

    Henry

  • Hi Henry,

    The 6201.Rx_BW20_OR46p8_ORx_BW20_OR46p8 profile requires 1 lane for Rx and 1 lane for Rx-Obs,

    However the 'less lanes' branch you compiled is configured for 1 lane Tx, 1 lane Rx and 2 lanes Rx-Obs.

    The RTL requires further changes so that the Rx-Obs will also use only one lane. Additionally an ad_ip_jesd204_link_dnconv component has to be inserted between the JESD link layer and transport layer of the observation path.

    If you plan to use the Tx , you will have to enable all lanes from the RTL.


    The 2577.Rx_BW25_OR61p44_ORx_BW50_OR61p44 profile can work with 2 lanes for Rx and 2 lanes for Rx-Obs, a configuration that matches the master hdl branch. Did you tried to load that profile with IIO scope?

    Laszlo

  • Hi Henry, 

    I made the previously mentioned changes in the "less lanes" hdl branch so the observation path can use only one lane. Please get the latest version and apply the attached  hdl patch. 

    hdl_less_lanes_Tx4Rx1RxObx1.patch.txt
    diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl
    index 7dddd1ba..309778b6 100644
    --- a/projects/adrv9009/common/adrv9009_bd.tcl
    +++ b/projects/adrv9009/common/adrv9009_bd.tcl
    @@ -2,7 +2,7 @@ set LINK_LAYER_BYTES_PER_BEAT 4
     
     
     # TX parameters
    -set TX_NUM_OF_LANES 1      ; # L
    +set TX_NUM_OF_LANES 4      ; # L
     set TX_NUM_OF_CONVERTERS 4 ; # M
     set TX_SAMPLES_PER_FRAME 1 ; # S
     set TX_SAMPLE_WIDTH 16     ; # N/NP
    @@ -31,8 +31,8 @@ set RX_TPL_BYTES_PER_BEAT [expr max($RX_BYTES_PER_FRAME, $LINK_LAYER_BYTES_PER_B
     set RX_SAMPLES_PER_CHANNEL [expr ($RX_NUM_OF_LANES * 8 * $RX_TPL_BYTES_PER_BEAT) / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
     
     # RX Observation parameters
    -set RX_OS_NUM_OF_LANES 2      ; # L
    -set RX_OS_NUM_OF_CONVERTERS 2 ; # M
    +set RX_OS_NUM_OF_LANES 1      ; # L
    +set RX_OS_NUM_OF_CONVERTERS 4 ; # M
     set RX_OS_SAMPLES_PER_FRAME 1 ; # S
     set RX_OS_SAMPLE_WIDTH 16     ; # N/NP
     
    @@ -256,6 +256,12 @@ for {set i 0} {$i < $RX_OS_NUM_OF_LANES} {incr i} {
     ad_connect  axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd/device_clk
     ad_connect  axi_adrv9009_rx_os_clkgen/clk_0 axi_adrv9009_rx_os_jesd_rstgen/slowest_sync_clk
     
    +# Connect unused CPLL clocks and resets
    +for {set i [expr $RX_NUM_OF_LANES+$RX_OS_NUM_OF_LANES]} {$i < $TX_NUM_OF_LANES} {incr i} {
    +  ad_connect util_adrv9009_xcvr/cpll_ref_clk_$i GND_1/dout
    +  ad_connect util_adrv9009_xcvr/up_cpll_rst_$i GND_1/dout
    +}
    +
     # dma clock & reset
     
     ad_ip_instance proc_sys_reset sys_dma_rstgen
    diff --git a/projects/adrv9009/zcu102/system_constr.xdc b/projects/adrv9009/zcu102/system_constr.xdc
    index 03c18920..0ebe9249 100644
    --- a/projects/adrv9009/zcu102/system_constr.xdc
    +++ b/projects/adrv9009/zcu102/system_constr.xdc
    @@ -9,18 +9,18 @@ set_property  -dict {PACKAGE_PIN  D33} [get_ports rx_data_p[0]]
     set_property  -dict {PACKAGE_PIN  D34} [get_ports rx_data_n[0]]                                        ; ## A03  FMC_HPC1_DP1_M2C_N
     set_property  -dict {PACKAGE_PIN  C31} [get_ports rx_data_p[1]]                                        ; ## A06  FMC_HPC1_DP2_M2C_P
     set_property  -dict {PACKAGE_PIN  C32} [get_ports rx_data_n[1]]                                        ; ## A07  FMC_HPC1_DP2_M2C_N
    -set_property  -dict {PACKAGE_PIN  E31} [get_ports rx_data_p[2]]                                        ; ## C06  FMC_HPC1_DP0_M2C_P
    -set_property  -dict {PACKAGE_PIN  E32} [get_ports rx_data_n[2]]                                        ; ## C07  FMC_HPC1_DP0_M2C_N
    +#set_property  -dict {PACKAGE_PIN  E31} [get_ports rx_data_p[2]]                                        ; ## C06  FMC_HPC1_DP0_M2C_P
    +#set_property  -dict {PACKAGE_PIN  E32} [get_ports rx_data_n[2]]                                        ; ## C07  FMC_HPC1_DP0_M2C_N
     #set_property  -dict {PACKAGE_PIN  B33} [get_ports rx_data_p[3]]                                        ; ## A10  FMC_HPC1_DP3_M2C_P
     #set_property  -dict {PACKAGE_PIN  B34} [get_ports rx_data_n[3]]                                        ; ## A11  FMC_HPC1_DP3_M2C_N
     set_property  -dict {PACKAGE_PIN  D29} [get_ports tx_data_p[0]]                                        ; ## A22  FMC_HPC1_DP1_C2M_P (tx_data_p[0])
     set_property  -dict {PACKAGE_PIN  D30} [get_ports tx_data_n[0]]                                        ; ## A23  FMC_HPC1_DP1_C2M_N (tx_data_n[0])
    -#set_property  -dict {PACKAGE_PIN  B29} [get_ports tx_data_p[1]]                                        ; ## A26  FMC_HPC1_DP2_C2M_P (tx_data_p[3])
    -#set_property  -dict {PACKAGE_PIN  B30} [get_ports tx_data_n[1]]                                        ; ## A27  FMC_HPC1_DP2_C2M_N (tx_data_n[3])
    -#set_property  -dict {PACKAGE_PIN  F29} [get_ports tx_data_p[2]]                                        ; ## C02  FMC_HPC1_DP0_C2M_P (tx_data_p[2])
    -#set_property  -dict {PACKAGE_PIN  F30} [get_ports tx_data_n[2]]                                        ; ## C03  FMC_HPC1_DP0_C2M_N (tx_data_n[2])
    -#set_property  -dict {PACKAGE_PIN  A31} [get_ports tx_data_p[3]]                                        ; ## A30  FMC_HPC1_DP3_C2M_P (tx_data_p[1])
    -#set_property  -dict {PACKAGE_PIN  A32} [get_ports tx_data_n[3]]                                        ; ## A31  FMC_HPC1_DP3_C2M_N (tx_data_n[1])
    +set_property  -dict {PACKAGE_PIN  B29} [get_ports tx_data_p[1]]                                        ; ## A26  FMC_HPC1_DP2_C2M_P (tx_data_p[3])
    +set_property  -dict {PACKAGE_PIN  B30} [get_ports tx_data_n[1]]                                        ; ## A27  FMC_HPC1_DP2_C2M_N (tx_data_n[3])
    +set_property  -dict {PACKAGE_PIN  F29} [get_ports tx_data_p[2]]                                        ; ## C02  FMC_HPC1_DP0_C2M_P (tx_data_p[2])
    +set_property  -dict {PACKAGE_PIN  F30} [get_ports tx_data_n[2]]                                        ; ## C03  FMC_HPC1_DP0_C2M_N (tx_data_n[2])
    +set_property  -dict {PACKAGE_PIN  A31} [get_ports tx_data_p[3]]                                        ; ## A30  FMC_HPC1_DP3_C2M_P (tx_data_p[1])
    +set_property  -dict {PACKAGE_PIN  A32} [get_ports tx_data_n[3]]                                        ; ## A31  FMC_HPC1_DP3_C2M_N (tx_data_n[1])
     set_property  -dict {PACKAGE_PIN  AH1  IOSTANDARD LVDS} [get_ports rx_sync_p]                          ; ## G09  FMC_HPC1_LA03_P
     set_property  -dict {PACKAGE_PIN  AJ1  IOSTANDARD LVDS} [get_ports rx_sync_n]                          ; ## G10  FMC_HPC1_LA03_N
     set_property  -dict {PACKAGE_PIN  AE10 IOSTANDARD LVDS} [get_ports rx_os_sync_p]                       ; ## G27  FMC_HPC1_LA25_P (Sniffer)
    diff --git a/projects/adrv9009/zcu102/system_top.v b/projects/adrv9009/zcu102/system_top.v
    index 6a2a0d89..e8e0333d 100644
    --- a/projects/adrv9009/zcu102/system_top.v
    +++ b/projects/adrv9009/zcu102/system_top.v
    @@ -47,10 +47,10 @@ module system_top (
       input                   ref_clk0_n,
       input                   ref_clk1_p,
       input                   ref_clk1_n,
    -  input       [ 2:0]      rx_data_p,
    -  input       [ 2:0]      rx_data_n,
    -  output      [ 0:0]      tx_data_p,
    -  output      [ 0:0]      tx_data_n,
    +  input       [ 1:0]      rx_data_p,
    +  input       [ 1:0]      rx_data_n,
    +  output      [ 3:0]      tx_data_p,
    +  output      [ 3:0]      tx_data_n,
       output                  rx_sync_p,
       output                  rx_sync_n,
       output                  rx_os_sync_p,
    @@ -215,8 +215,8 @@ module system_top (
         .rx_data_0_p (rx_data_p[0]),
         .rx_data_1_n (rx_data_n[1]),
         .rx_data_1_p (rx_data_p[1]),
    -    .rx_data_2_n (rx_data_n[2]),
    -    .rx_data_2_p (rx_data_p[2]),
    +//    .rx_data_2_n (rx_data_n[2]),
    +//    .rx_data_2_p (rx_data_p[2]),
     //    .rx_data_3_n (rx_data_n[3]),
     //    .rx_data_3_p (rx_data_p[3]),
         .rx_ref_clk_0 (ref_clk1),
    @@ -235,12 +235,12 @@ module system_top (
         .spi1_mosi (),
         .tx_data_0_n (tx_data_n[0]),
         .tx_data_0_p (tx_data_p[0]),
    -//    .tx_data_1_n (tx_data_n[1]),
    -//    .tx_data_1_p (tx_data_p[1]),
    -//    .tx_data_2_n (tx_data_n[2]),
    -//    .tx_data_2_p (tx_data_p[2]),
    -//    .tx_data_3_n (tx_data_n[3]),
    -//    .tx_data_3_p (tx_data_p[3]),
    +    .tx_data_1_n (tx_data_n[1]),
    +    .tx_data_1_p (tx_data_p[1]),
    +    .tx_data_2_n (tx_data_n[2]),
    +    .tx_data_2_p (tx_data_p[2]),
    +    .tx_data_3_n (tx_data_n[3]),
    +    .tx_data_3_p (tx_data_p[3]),
         .tx_ref_clk_0 (ref_clk1),
         .tx_sync_0 (tx_sync),
         .tx_sysref_0 (sysref));
    

    I tested it with a 100MHz Rx profile, see the attached Linux patch, however I could not get a working  with lower bandwidth profile. We still need to look into that

    linux_master_Tx4Rx1RxObx1.patch.txt
    diff --git a/arch/arm64/boot/dts/xilinx/adi-adrv9009.dtsi b/arch/arm64/boot/dts/xilinx/adi-adrv9009.dtsi
    index 2756dd033189..7d89a4ae5918 100644
    --- a/arch/arm64/boot/dts/xilinx/adi-adrv9009.dtsi
    +++ b/arch/arm64/boot/dts/xilinx/adi-adrv9009.dtsi
    @@ -134,11 +134,11 @@
     		adi,jesd204-framer-a-lane0-id = <0>;
     		adi,jesd204-framer-a-m = <4>;
     		adi,jesd204-framer-a-k = <32>;
    -		adi,jesd204-framer-a-f = <4>;
    +		adi,jesd204-framer-a-f = <8>;
     		adi,jesd204-framer-a-np = <16>;
     		adi,jesd204-framer-a-scramble = <1>;
     		adi,jesd204-framer-a-external-sysref = <1>;
    -		adi,jesd204-framer-a-serializer-lanes-enabled = <0x03>;
    +		adi,jesd204-framer-a-serializer-lanes-enabled = <0x01>;
     		adi,jesd204-framer-a-serializer-lane-crossbar = <0xE4>;
     		adi,jesd204-framer-a-lmfc-offset = <31>;
     		adi,jesd204-framer-a-new-sysref-on-relink = <0>;
    @@ -154,11 +154,11 @@
     		adi,jesd204-framer-b-lane0-id = <0>;
     		adi,jesd204-framer-b-m = <4>;
     		adi,jesd204-framer-b-k = <32>;
    -		adi,jesd204-framer-b-f = <4>;
    +		adi,jesd204-framer-b-f = <8>;
     		adi,jesd204-framer-b-np = <16>;
     		adi,jesd204-framer-b-scramble = <1>;
     		adi,jesd204-framer-b-external-sysref = <1>;
    -		adi,jesd204-framer-b-serializer-lanes-enabled = <0x0C>;
    +		adi,jesd204-framer-b-serializer-lanes-enabled = <0x02>;
     		adi,jesd204-framer-b-serializer-lane-crossbar = <0xE4>;
     		adi,jesd204-framer-b-lmfc-offset = <31>;
     		adi,jesd204-framer-b-new-sysref-on-relink = <0>;
    @@ -204,10 +204,10 @@
     
     		adi,rx-profile-rx-fir-decimation = <2>;
     		adi,rx-profile-rx-dec5-decimation = <4>;
    -		adi,rx-profile-rhb1-decimation = <1>;
    -		adi,rx-profile-rx-output-rate_khz = <245760>;
    -		adi,rx-profile-rf-bandwidth_hz = <200000000>;
    -		adi,rx-profile-rx-bbf3d-bcorner_khz = <200000>;
    +		adi,rx-profile-rhb1-decimation = <2>;
    +		adi,rx-profile-rx-output-rate_khz = <122880>;
    +		adi,rx-profile-rf-bandwidth_hz = <100000000>;
    +		adi,rx-profile-rx-bbf3d-bcorner_khz = <100000>;
     		adi,rx-profile-rx-adc-profile = /bits/ 16 <182 142 173 90 1280 982 1335 96 1369 48 1012 18 48 48 37 208 0 0 0 0 52 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
     		adi,rx-profile-rx-ddc-mode = <0>;
     
    @@ -236,11 +236,11 @@
     		adi,orx-profile-rx-fir-gain_db = <6>;
     		adi,orx-profile-rx-fir-num-fir-coefs = <24>;
     		adi,orx-profile-rx-fir-coefs = /bits/ 16  <(-10) (7) (-10) (-12) (6) (-12) (16) (-16) (1) (63) (-431) (17235) (-431) (63) (1) (-16) (16) (-12) (6) (-12) (-10) (7) (-10) (0)>;
    -		adi,orx-profile-rx-fir-decimation = <1>;
    +		adi,orx-profile-rx-fir-decimation = <2>;
     		adi,orx-profile-rx-dec5-decimation = <4>;
     		adi,orx-profile-rhb1-decimation = <2>;
    -		adi,orx-profile-orx-output-rate_khz = <245760>;
    -		adi,orx-profile-rf-bandwidth_hz = <200000000>;
    +		adi,orx-profile-orx-output-rate_khz = <122880>;
    +		adi,orx-profile-rf-bandwidth_hz = <100000000>;
     		adi,orx-profile-rx-bbf3d-bcorner_khz = <225000>;
     		adi,orx-profile-orx-low-pass-adc-profile = /bits/ 16  <185 141 172 90 1280 942 1332 90 1368 46 1016 19 48 48 37 208 0 0 0 0 52 0 7 6 42 0 7 6 42 0 25 27 0 0 25 27 0 0 165 44 31 905>;
     		adi,orx-profile-orx-band-pass-adc-profile = /bits/ 16  <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>;
    diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts
    index ced167079c94..6ba8f43ba178 100644
    --- a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts
    +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-adrv9009.dts
    @@ -120,18 +120,18 @@
     			spibus-connected = <&trx0_adrv9009>;
     		};
     
    -		axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@84a08000 {
    +		axi_adrv9009_core_rx_obs: axi-adrv9009-rx-obs-hpc@84a20000 {
     			compatible = "adi,axi-adrv9009-obs-1.0";
    -			reg = <0x84a08000 0x1000>;
    +			reg = <0x84a20000 0x1000>;
     			dmas = <&rx_obs_dma 0>;
     			dma-names = "rx";
     			clocks = <&trx0_adrv9009 1>;
     			clock-names = "sampl_clk";
     		};
     
    -		axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@84a04000 {
    +		axi_adrv9009_core_tx: axi-adrv9009-tx-hpc@84a14000 {
     			compatible = "adi,axi-adrv9009-tx-1.0";
    -			reg = <0x84a04000 0x4000>;
    +			reg = <0x84a14000 0x4000>;
     			dmas = <&tx_dma 0>;
     			dma-names = "tx";
     			clocks = <&trx0_adrv9009 2>;
    @@ -152,7 +152,7 @@
     			#clock-cells = <0>;
     			clock-output-names = "jesd_rx_lane_clk";
     
    -			adi,octets-per-frame = <4>;
    +			adi,octets-per-frame = <8>;
     			adi,frames-per-multiframe = <32>;
     		};
     
    @@ -188,7 +188,7 @@
     			#clock-cells = <0>;
     			clock-output-names = "jesd_rx_os_lane_clk";
     
    -			adi,octets-per-frame = <4>;
    +			adi,octets-per-frame = <8>;
     			adi,frames-per-multiframe = <32>;
     		};
     
    

    Laszlo