Can't set AD9361 LO Freq above 4.29Ghz

Hi,

We build a custom board with 2xAD9361 via SPI. Our Linux Kernel is 4.1.53. T1042 CPU (PowerPC, Big-Endian)

To be close as possible, We used your 2015_R2 branch that fits Kernel 4.0 (next commit version is 4.4)

We've got the driver loaded (including SysFS) but can't set an LO frequency above 4.29Ghz for both Tx and Rx.

In some LO values, we read (sysFS cat) different values than we set (echo)

Attach our device tree: 

		abc_fpga: abc-fpga {
			compatible = "abc,abc-fpga";
			reg = <0x1df0000 0x1000>;
		};

		abc_spi: abc-spi {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "abc,abc-spi";
			reg = <1000000 0>;

			ad9361-phy@0 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				compatible = "adi,ad9361";
				reg = <0x0 0>;
				spi-cpha;
				/*spi-tx-bus-width = <2>;*/
				/*spi-rx-bus-width = <1>;*/
				//spi-bits-per-word = <16>;
				spi-max-frequency = <1000000>;
				clock-names = "ad9361_ext_refclk";

				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
				clocks = <&ad9361_clkin 0>;
                                adi,digital-interface-tune-skip-mode = <0x0>;
                                adi,pp-tx-swap-enable;
                                adi,pp-rx-swap-enable;
                                adi,rx-frame-pulse-mode-enable;
                                adi,lvds-mode-enable;
                                adi,lvds-bias-mV = <0x96>;
                                adi,lvds-rx-onchip-termination-enable;
                                adi,rx-data-delay = <0x4>;
                                adi,tx-fb-clock-delay = <0x7>;
                                adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
                                adi,2rx-2tx-mode-enable;
                                adi,frequency-division-duplex-mode-enable;
                                adi,rx-rf-port-input-select = <0x0>;
                                adi,tx-rf-port-input-select = <0x0>;
                                adi,tx-attenuation-mdB = <0x2710>;
                                adi,rf-rx-bandwidth-hz = <0x112a880>;
                                adi,rf-tx-bandwidth-hz = <0x112a880>;
                                adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
                                adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
                                adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
                                adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
                                adi,gc-rx1-mode = <0x2>;
                                adi,gc-rx2-mode = <0x2>;
                                adi,gc-adc-ovr-sample-size = <0x4>;
                                adi,gc-adc-small-overload-thresh = <0x2f>;
                                adi,gc-adc-large-overload-thresh = <0x3a>;
                                adi,gc-lmt-overload-high-thresh = <0x320>;
                                adi,gc-lmt-overload-low-thresh = <0x2c0>;
                                adi,gc-dec-pow-measurement-duration = <0x2000>;
                                adi,gc-low-power-thresh = <0x18>;
                                adi,mgc-inc-gain-step = <0x2>;
                                adi,mgc-dec-gain-step = <0x2>;
                                adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
                                adi,agc-attack-delay-extra-margin-us = <0x1>;
                                adi,agc-outer-thresh-high = <0x5>;
                                adi,agc-outer-thresh-high-dec-steps = <0x2>;
                                adi,agc-inner-thresh-high = <0xa>;
                                adi,agc-inner-thresh-high-dec-steps = <0x1>;
                                adi,agc-inner-thresh-low = <0xc>;
                                adi,agc-inner-thresh-low-inc-steps = <0x1>;
                                adi,agc-outer-thresh-low = <0x12>;
                                adi,agc-outer-thresh-low-inc-steps = <0x2>;
                                adi,agc-adc-small-overload-exceed-counter = <0xa>;
                                adi,agc-adc-large-overload-exceed-counter = <0xa>;
                                adi,agc-adc-large-overload-inc-steps = <0x2>;
                                adi,agc-lmt-overload-large-exceed-counter = <0xa>;
                                adi,agc-lmt-overload-small-exceed-counter = <0xa>;
                                adi,agc-lmt-overload-large-inc-steps = <0x2>;
                                adi,agc-gain-update-interval-us = <0x3e8>;
                                adi,fagc-dec-pow-measurement-duration = <0x40>;
                                adi,fagc-lp-thresh-increment-steps = <0x1>;
                                adi,fagc-lp-thresh-increment-time = <0x5>;
                                adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
                                adi,fagc-final-overrange-count = <0x3>;
                                adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
                                adi,fagc-lmt-final-settling-steps = <0x1>;
                                adi,fagc-lock-level = <0xa>;
                                adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
                                adi,fagc-lock-level-lmt-gain-increase-enable;
                                adi,fagc-lpf-final-settling-steps = <0x1>;
                                adi,fagc-optimized-gain-offset = <0x5>;
                                adi,fagc-power-measurement-duration-in-state5 = <0x40>;
                                adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
                                adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
                                adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
                                adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
                                adi,fagc-rst-gla-large-adc-overload-enable;
                                adi,fagc-rst-gla-large-lmt-overload-enable;
                                adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
                                adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
                                adi,fagc-state-wait-time-ns = <0x104>;
                                adi,fagc-use-last-lock-level-for-set-gain-enable;
                                adi,rssi-restart-mode = <0x3>;
                                adi,rssi-delay = <0x1>;
                                adi,rssi-wait = <0x1>;
                                adi,rssi-duration = <0x3e8>;
                                adi,ctrl-outs-index = <0x0>;
                                adi,ctrl-outs-enable-mask = <0xff>;
                                adi,temp-sense-measurement-interval-ms = <0x3e8>;
                                adi,temp-sense-offset-signed = <0xce>;
                                adi,temp-sense-periodic-measurement-enable;
                                adi,aux-dac-manual-mode-enable;
                                adi,aux-dac1-default-value-mV = <0x0>;
                                adi,aux-dac1-rx-delay-us = <0x0>;
                                adi,aux-dac1-tx-delay-us = <0x0>;
                                adi,aux-dac2-default-value-mV = <0x0>;
                                adi,aux-dac2-rx-delay-us = <0x0>;
                                adi,aux-dac2-tx-delay-us = <0x0>;
			};

			ad9361-phy@1 {
				#address-cells = <0x1>;
				#size-cells = <0x0>;
				#clock-cells = <0x1>;
				compatible = "adi,ad9361";
				reg = <0x1 0>;
				spi-cpha;
				/*spi-tx-bus-width = <2>;*/
				/*spi-rx-bus-width = <1>;*/
				//spi-bits-per-word = <16>;
				spi-max-frequency = <1000000>;
				clock-names = "ad9361_ext_refclk";

				clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
				clocks = <&ad9361_clkin 0>;
                                adi,digital-interface-tune-skip-mode = <0x0>;
                                adi,pp-tx-swap-enable;
                                adi,pp-rx-swap-enable;
                                adi,rx-frame-pulse-mode-enable;
                                adi,lvds-mode-enable;
                                adi,lvds-bias-mV = <0x96>;
                                adi,lvds-rx-onchip-termination-enable;
                                adi,rx-data-delay = <0x4>;
                                adi,tx-fb-clock-delay = <0x7>;
                                adi,dcxo-coarse-and-fine-tune = <0x8 0x1720>;
                                adi,2rx-2tx-mode-enable;
                                adi,frequency-division-duplex-mode-enable;
                                adi,rx-rf-port-input-select = <0x0>;
                                adi,tx-rf-port-input-select = <0x0>;
                                adi,tx-attenuation-mdB = <0x2710>;
                                adi,rf-rx-bandwidth-hz = <0x112a880>;
                                adi,rf-tx-bandwidth-hz = <0x112a880>;
                                adi,rx-synthesizer-frequency-hz = <0x0 0x8f0d1800>;
                                adi,tx-synthesizer-frequency-hz = <0x0 0x92080880>;
                                adi,rx-path-clock-frequencies = <0x3a980000 0xea60000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
                                adi,tx-path-clock-frequencies = <0x3a980000 0x7530000 0x7530000 0x3a98000 0x1d4c000 0x1d4c000>;
                                adi,gc-rx1-mode = <0x2>;
                                adi,gc-rx2-mode = <0x2>;
                                adi,gc-adc-ovr-sample-size = <0x4>;
                                adi,gc-adc-small-overload-thresh = <0x2f>;
                                adi,gc-adc-large-overload-thresh = <0x3a>;
                                adi,gc-lmt-overload-high-thresh = <0x320>;
                                adi,gc-lmt-overload-low-thresh = <0x2c0>;
                                adi,gc-dec-pow-measurement-duration = <0x2000>;
                                adi,gc-low-power-thresh = <0x18>;
                                adi,mgc-inc-gain-step = <0x2>;
                                adi,mgc-dec-gain-step = <0x2>;
                                adi,mgc-split-table-ctrl-inp-gain-mode = <0x0>;
                                adi,agc-attack-delay-extra-margin-us = <0x1>;
                                adi,agc-outer-thresh-high = <0x5>;
                                adi,agc-outer-thresh-high-dec-steps = <0x2>;
                                adi,agc-inner-thresh-high = <0xa>;
                                adi,agc-inner-thresh-high-dec-steps = <0x1>;
                                adi,agc-inner-thresh-low = <0xc>;
                                adi,agc-inner-thresh-low-inc-steps = <0x1>;
                                adi,agc-outer-thresh-low = <0x12>;
                                adi,agc-outer-thresh-low-inc-steps = <0x2>;
                                adi,agc-adc-small-overload-exceed-counter = <0xa>;
                                adi,agc-adc-large-overload-exceed-counter = <0xa>;
                                adi,agc-adc-large-overload-inc-steps = <0x2>;
                                adi,agc-lmt-overload-large-exceed-counter = <0xa>;
                                adi,agc-lmt-overload-small-exceed-counter = <0xa>;
                                adi,agc-lmt-overload-large-inc-steps = <0x2>;
                                adi,agc-gain-update-interval-us = <0x3e8>;
                                adi,fagc-dec-pow-measurement-duration = <0x40>;
                                adi,fagc-lp-thresh-increment-steps = <0x1>;
                                adi,fagc-lp-thresh-increment-time = <0x5>;
                                adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt = <0x8>;
                                adi,fagc-final-overrange-count = <0x3>;
                                adi,fagc-gain-index-type-after-exit-rx-mode = <0x0>;
                                adi,fagc-lmt-final-settling-steps = <0x1>;
                                adi,fagc-lock-level = <0xa>;
                                adi,fagc-lock-level-gain-increase-upper-limit = <0x5>;
                                adi,fagc-lock-level-lmt-gain-increase-enable;
                                adi,fagc-lpf-final-settling-steps = <0x1>;
                                adi,fagc-optimized-gain-offset = <0x5>;
                                adi,fagc-power-measurement-duration-in-state5 = <0x40>;
                                adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable;
                                adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll = <0xa>;
                                adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable;
                                adi,fagc-rst-gla-if-en-agc-pulled-high-mode = <0x0>;
                                adi,fagc-rst-gla-large-adc-overload-enable;
                                adi,fagc-rst-gla-large-lmt-overload-enable;
                                adi,fagc-rst-gla-stronger-sig-thresh-above-ll = <0xa>;
                                adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable;
                                adi,fagc-state-wait-time-ns = <0x104>;
                                adi,fagc-use-last-lock-level-for-set-gain-enable;
                                adi,rssi-restart-mode = <0x3>;
                                adi,rssi-delay = <0x1>;
                                adi,rssi-wait = <0x1>;
                                adi,rssi-duration = <0x3e8>;
                                adi,ctrl-outs-index = <0x0>;
                                adi,ctrl-outs-enable-mask = <0xff>;
                                adi,temp-sense-measurement-interval-ms = <0x3e8>;
                                adi,temp-sense-offset-signed = <0xce>;
                                adi,temp-sense-periodic-measurement-enable;
                                adi,aux-dac-manual-mode-enable;
                                adi,aux-dac1-default-value-mV = <0x0>;
                                adi,aux-dac1-rx-delay-us = <0x0>;
                                adi,aux-dac1-tx-delay-us = <0x0>;
                                adi,aux-dac2-default-value-mV = <0x0>;
                                adi,aux-dac2-rx-delay-us = <0x0>;
                                adi,aux-dac2-tx-delay-us = <0x0>;
			};
		};

	};

        clocks {
                ad9361_clkin: clock@0 {
                        #clock-cells = <0x00>;
                        compatible = "fixed-clock";
                        clock-frequency = <40000000>;
                        clock-output-names = "ad9361_ext_refclk";
                };
	};

Clock summery:

   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 ad9361_ext_refclk                       16           16    40000000          0 0
    spi32765.1-bb_refclk                  0            0    40000000          0 0
       spi32765.1-bbpll_clk               0            0   960000000          0 0
          spi32765.1-adc_clk              0            0   240000000          0 0
             spi32765.1-dac_clk           0            0   120000000          0 0
                spi32765.1-t2_clk           0            0   120000000          0 0
                   spi32765.1-t1_clk           0            0    60000000          0 0
                      spi32765.1-clktf_clk           0            0    30000000          0 0
                         spi32765.1-tx_sampl_clk           0            0    30000000          0 0
             spi32765.1-r2_clk            0            0   120000000          0 0
                spi32765.1-r1_clk           0            0    60000000          0 0
                   spi32765.1-clkrf_clk           0            0    30000000          0 0
                      spi32765.1-rx_sampl_clk           0            0    30000000          0 0
    spi32765.1-rx_refclk                  1            1    80000000          0 0
       spi32765.1-rx_rfpll_int            1            1  1200000000          0 0
          spi32765.1-rx_rfpll             1            1  1200000000          0 0
    spi32765.1-tx_refclk                  1            1    80000000          0 0
       spi32765.1-tx_rfpll_int            1            1  2409843767          0 0
          spi32765.1-tx_rfpll             1            1  2409843767          0 0
    spi32765.0-bb_refclk                  0            0    40000000          0 0
       spi32765.0-bbpll_clk               0            0   960000000          0 0
          spi32765.0-adc_clk              0            0   240000000          0 0
             spi32765.0-dac_clk           0            0   120000000          0 0
                spi32765.0-t2_clk           0            0   120000000          0 0
                   spi32765.0-t1_clk           0            0    60000000          0 0
                      spi32765.0-clktf_clk           0            0    30000000          0 0
                         spi32765.0-tx_sampl_clk           0            0    30000000          0 0
             spi32765.0-r2_clk            0            0   120000000          0 0
                spi32765.0-r1_clk           0            0    60000000          0 0
                   spi32765.0-clkrf_clk           0            0    30000000          0 0
                      spi32765.0-rx_sampl_clk           0            0    30000000          0 0
    spi32765.0-rx_refclk                  1            1    80000000          0 0
       spi32765.0-rx_rfpll_int            1            1  1200000000          0 0
          spi32765.0-rx_rfpll             1            1  1200000000          0 0
    spi32765.0-tx_refclk                  1            1    80000000          0 0
       spi32765.0-tx_rfpll_int            1            1  2409843767          0 0
          spi32765.0-tx_rfpll             1            1  2409843767          0 0
 cg-sysclk                                0            0   100000000          0 0
    cg-pll2-div4                          0            0   375000000          0 0
    cg-pll2-div3                          0            0   500000000          0 0
    cg-pll2-div2                          0            0   750000000          0 0
    cg-pll2-div1                          0            0  1500000000          0 0
    cg-pll1-div4                          0            0   375000000          0 0
    cg-pll1-div3                          0            0   500000000          0 0
    cg-pll1-div2                          0            0   750000000          0 0
    cg-pll1-div1                          0            0  1500000000          0 0
       cg-cmux3                           0            0  1500000000          0 0
       cg-cmux2                           0            0  1500000000          0 0
       cg-cmux1                           0            0  1500000000          0 0
       cg-cmux0                           0            0  1500000000          0 0
    cg-pll0-div4                          0            0   150000000          0 0
    cg-pll0-div3                          0            0   200000000          0 0
    cg-pll0-div2                          0            0   300000000          0 0
    cg-pll0-div1                          0            0   600000000          0 0
 spi32765.1-tx_lo_dummy                   0            0           0          0 0
 spi32765.1-rx_lo_dummy                   0            0           0          0 0
 spi32765.0-tx_lo_dummy                   0            0           0          0 0
 spi32765.0-rx_lo_dummy                   0            0           0          0 0

Could you help us with understanding the cause of this issue? 

Is it something with 2^32 clock values?

Is it coming from using 4.0 driver will a 4.1.53 kernel+IIO? big/little endian?

Could you suggest mitigation or another version that will better work with our system?

Thanks in advance,

Yoni



added the updated DT
[edited by: YoniH at 6:56 AM (GMT 0) on 22 May 2019]