We are using two AD9371 with one AD9528 chip. For now, we have connected one AD9371.
Our problem is sysref is not coming from the AD9528 output channels. We have configured AD9528 channel 0 and channel 2 for AD9371 DEV_CLK and SYSREF. And at the same time channel4 and channel5 for FPGA Clk and sysref. Our device tree is looking OK. And we have probed the sysref-req in ad9371 driver also. All configuration looks OK. But we are not getting sysref and at the same time peak to peak device clock is 900 mV. AD9371 driver is also printing the ILAS mismatch error.Which section we should look?
First make sure you're getting sysref pulses whenever the sysref request strobe is asserted.
We have configured
adi,sysref-src = <0x2>; adi,sysref-pattern-mode = <0x1>; adi,sysref-k-div = <0x200>; adi,sysref-request-enable; adi,sysref-nshot-mode = <0x3>; adi,sysref-request-trigger-mode = <0x0>;
in AD9528 section and sysref_req-gpios = <0x1f 0x88 0x0>; in AD9371 section. While the AD9371 driver probes the sysref strobe is coming on this gpio.
One more observation when we specify only two channels output for AD9371 clk and sysref. AD9371 driver is not loading because we are not giving fmc_clk but sysref is visible on AD9528 output channel.
If you fmc clock is not generated by the AD9528, create a fixed frequency clock and give it as fmc_clk.
Please provide your entire device tree.
We are getting fmc clock but only for isolation of the problem we have removed it.
No we have configured all clocks and sysrefs for AD9371 and FPGA.
Now we are getting JESD status as below:
Link is enabled
Measured Link Clock: 122.878 MHz:
Reported Link Clock: 122.880 :MHz
Lane rate 4915.200 :MHz
Lane rate / 40: 122.880 MHz
Link Status: DATA
SYSREF alignment error: yes